\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
MDMA global interrupt/status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GIF0 : GIF0
bits : 0 - 0 (1 bit)
GIF1 : GIF1
bits : 1 - 1 (1 bit)
GIF2 : GIF2
bits : 2 - 2 (1 bit)
GIF3 : GIF3
bits : 3 - 3 (1 bit)
GIF4 : GIF4
bits : 4 - 4 (1 bit)
GIF5 : GIF5
bits : 5 - 5 (1 bit)
GIF6 : GIF6
bits : 6 - 6 (1 bit)
GIF7 : GIF7
bits : 7 - 7 (1 bit)
GIF8 : GIF8
bits : 8 - 8 (1 bit)
GIF9 : GIF9
bits : 9 - 9 (1 bit)
GIF10 : GIF10
bits : 10 - 10 (1 bit)
GIF11 : GIF11
bits : 11 - 11 (1 bit)
GIF12 : GIF12
bits : 12 - 12 (1 bit)
GIF13 : GIF13
bits : 13 - 13 (1 bit)
GIF14 : GIF14
bits : 14 - 14 (1 bit)
GIF15 : GIF15
bits : 15 - 15 (1 bit)
GIF16 : GIF16
bits : 16 - 16 (1 bit)
GIF17 : GIF17
bits : 17 - 17 (1 bit)
GIF18 : GIF18
bits : 18 - 18 (1 bit)
GIF19 : GIF19
bits : 19 - 19 (1 bit)
GIF20 : GIF20
bits : 20 - 20 (1 bit)
GIF21 : GIF21
bits : 21 - 21 (1 bit)
GIF22 : GIF22
bits : 22 - 22 (1 bit)
GIF23 : GIF23
bits : 23 - 23 (1 bit)
GIF24 : GIF24
bits : 24 - 24 (1 bit)
GIF25 : GIF25
bits : 25 - 25 (1 bit)
GIF26 : GIF26
bits : 26 - 26 (1 bit)
GIF27 : GIF27
bits : 27 - 27 (1 bit)
GIF28 : GIF28
bits : 28 - 28 (1 bit)
GIF29 : GIF29
bits : 29 - 29 (1 bit)
GIF30 : GIF30
bits : 30 - 30 (1 bit)
GIF31 : GIF31
bits : 31 - 31 (1 bit)
MDMA channel 3 interrupt/status register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 3 interrupt flag clear register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 3 error status register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA channel 4 interrupt/status register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 4 interrupt flag clear register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 4 error status register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA channel 5 interrupt/status register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 5 interrupt flag clear register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 5 error status register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA channel 6 interrupt/status register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 6 interrupt flag clear register
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 6 error status register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA channel 7 interrupt/status register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 7 interrupt flag clear register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 7 error status register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA channel 8 interrupt/status register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 8 interrupt flag clear register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 8 error status register
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA channel 9 interrupt/status register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 9 interrupt flag clear register
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 9 error status register
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA channel 10 interrupt/status register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 10 interrupt flag clear register
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 10 error status register
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA channel 11 interrupt/status register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 11 interrupt flag clear register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 11 error status register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA channel 12 interrupt/status register
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 12 interrupt flag clear register
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 12 error status register
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA channel 13 interrupt/status register
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 13 interrupt flag clear register
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 13 error status register
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA channel 14 interrupt/status register
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 14 interrupt flag clear register
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 14 error status register
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x3CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA channel 0 interrupt/status register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 15 interrupt/status register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 15 interrupt flag clear register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 15 error status register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA channel 0 interrupt flag clear register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 16 interrupt/status register
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 16 interrupt flag clear register
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 16 error status register
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x45C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA channel 0 error status register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
MDMA channel 17 interrupt/status register
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 17 interrupt flag clear register
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 17 error status register
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
This register is used to control the concerned channel.
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
MDMA channel 18 interrupt/status register
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 18 interrupt flag clear register
address_offset : 0x4C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 18 error status register
address_offset : 0x4C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x4CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x4D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x4D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x4DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x4E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x4E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x4F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
MDMA channel 19 interrupt/status register
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 19 interrupt flag clear register
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 19 error status register
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x524 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x534 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
MDMA channel 20 interrupt/status register
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 20 interrupt flag clear register
address_offset : 0x544 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 20 error status register
address_offset : 0x548 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x54C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x554 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x558 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x55C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
MDMA channel 21 interrupt/status register
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 21 interrupt flag clear register
address_offset : 0x584 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 21 error status register
address_offset : 0x588 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x594 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x598 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x59C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x5A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
MDMA channel 22 interrupt/status register
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 22 interrupt flag clear register
address_offset : 0x5C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 22 error status register
address_offset : 0x5C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x5CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x5D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x5D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x5DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x5E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x5E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x5F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
MDMA channel 23 interrupt/status register
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 23 interrupt flag clear register
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 23 error status register
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x60C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x618 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x61C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x624 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
MDMA channel 24 interrupt/status register
address_offset : 0x640 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 24 interrupt flag clear register
address_offset : 0x644 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 24 error status register
address_offset : 0x648 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x64C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x654 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x65C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x674 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
MDMA channel 25 interrupt/status register
address_offset : 0x680 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 25 interrupt flag clear register
address_offset : 0x684 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 25 error status register
address_offset : 0x688 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x68C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x694 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x69C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x6A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x6A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x6B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x6B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA channel 26 interrupt/status register
address_offset : 0x6C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 26 interrupt flag clear register
address_offset : 0x6C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 26 error status register
address_offset : 0x6C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x6CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x6D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x6D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x6D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x6DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x6E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x6E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x6E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x6F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x6F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
MDMA channel 27 interrupt/status register
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 27 interrupt flag clear register
address_offset : 0x704 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 27 error status register
address_offset : 0x708 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x70C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x718 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x71C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA channel 28 interrupt/status register
address_offset : 0x740 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 28 interrupt flag clear register
address_offset : 0x744 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 28 error status register
address_offset : 0x748 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x74C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x750 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x754 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x758 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x75C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x760 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x764 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x768 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x770 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x774 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA channel 29 interrupt/status register
address_offset : 0x780 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 29 interrupt flag clear register
address_offset : 0x784 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 29 error status register
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x78C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x794 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x798 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x79C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x7A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x7A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x7A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x7B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x7B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA channel 30 interrupt/status register
address_offset : 0x7C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 30 interrupt flag clear register
address_offset : 0x7C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 30 error status register
address_offset : 0x7C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x7CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x7D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x7D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x7D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x7DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x7E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x7E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x7E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x7F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x7F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA secure global interrupt/status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GIF0 : GIF0
bits : 0 - 0 (1 bit)
GIF1 : GIF1
bits : 1 - 1 (1 bit)
GIF2 : GIF2
bits : 2 - 2 (1 bit)
GIF3 : GIF3
bits : 3 - 3 (1 bit)
GIF4 : GIF4
bits : 4 - 4 (1 bit)
GIF5 : GIF5
bits : 5 - 5 (1 bit)
GIF6 : GIF6
bits : 6 - 6 (1 bit)
GIF7 : GIF7
bits : 7 - 7 (1 bit)
GIF8 : GIF8
bits : 8 - 8 (1 bit)
GIF9 : GIF9
bits : 9 - 9 (1 bit)
GIF10 : GIF10
bits : 10 - 10 (1 bit)
GIF11 : GIF11
bits : 11 - 11 (1 bit)
GIF12 : GIF12
bits : 12 - 12 (1 bit)
GIF13 : GIF13
bits : 13 - 13 (1 bit)
GIF14 : GIF14
bits : 14 - 14 (1 bit)
GIF15 : GIF15
bits : 15 - 15 (1 bit)
GIF16 : GIF16
bits : 16 - 16 (1 bit)
GIF17 : GIF17
bits : 17 - 17 (1 bit)
GIF18 : GIF18
bits : 18 - 18 (1 bit)
GIF19 : GIF19
bits : 19 - 19 (1 bit)
GIF20 : GIF20
bits : 20 - 20 (1 bit)
GIF21 : GIF21
bits : 21 - 21 (1 bit)
GIF22 : GIF22
bits : 22 - 22 (1 bit)
GIF23 : GIF23
bits : 23 - 23 (1 bit)
GIF24 : GIF24
bits : 24 - 24 (1 bit)
GIF25 : GIF25
bits : 25 - 25 (1 bit)
GIF26 : GIF26
bits : 26 - 26 (1 bit)
GIF27 : GIF27
bits : 27 - 27 (1 bit)
GIF28 : GIF28
bits : 28 - 28 (1 bit)
GIF29 : GIF29
bits : 29 - 29 (1 bit)
GIF30 : GIF30
bits : 30 - 30 (1 bit)
GIF31 : GIF31
bits : 31 - 31 (1 bit)
MDMA channel 1 interrupt/status register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 31 interrupt/status register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 31 interrupt flag clear register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 31 error status register
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0x824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0x834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA channel 1 interrupt flag clear register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 1 error status register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
MDMA channel 2 interrupt/status register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : TEIF
bits : 0 - 0 (1 bit)
CTCIF : CTCIF
bits : 1 - 1 (1 bit)
BRTIF : BRTIF
bits : 2 - 2 (1 bit)
BTIF : BTIF
bits : 3 - 3 (1 bit)
TCIF : TCIF
bits : 4 - 4 (1 bit)
CRQA : CRQA
bits : 16 - 16 (1 bit)
MDMA channel 2 interrupt flag clear register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEIF : CTEIF
bits : 0 - 0 (1 bit)
CCTCIF : CCTCIF
bits : 1 - 1 (1 bit)
CBRTIF : CBRTIF
bits : 2 - 2 (1 bit)
CBTIF : CBTIF
bits : 3 - 3 (1 bit)
CLTCIF : CLTCIF
bits : 4 - 4 (1 bit)
MDMA channel 2 error status register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEA : TEA
bits : 0 - 6 (7 bit)
TED : TED
bits : 7 - 7 (1 bit)
TELD : TELD
bits : 8 - 8 (1 bit)
TEMD : TEMD
bits : 9 - 9 (1 bit)
ASE : ASE
bits : 10 - 10 (1 bit)
BSE : BSE
bits : 11 - 11 (1 bit)
This register is used to control the concerned channel.
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
TEIE : TEIE
bits : 1 - 1 (1 bit)
access : read-write
CTCIE : CTCIE
bits : 2 - 2 (1 bit)
access : read-write
BRTIE : BRTIE
bits : 3 - 3 (1 bit)
access : read-write
BTIE : BTIE
bits : 4 - 4 (1 bit)
access : read-write
TCIE : TCIE
bits : 5 - 5 (1 bit)
access : read-write
PL : PL
bits : 6 - 7 (2 bit)
access : read-write
BEX : BEX
bits : 12 - 12 (1 bit)
access : read-write
HEX : HEX
bits : 13 - 13 (1 bit)
access : read-write
WEX : WEX
bits : 14 - 14 (1 bit)
access : read-write
SWRQ : SWRQ
bits : 16 - 16 (1 bit)
access : write-only
This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINC : SINC
bits : 0 - 1 (2 bit)
DINC : DINC
bits : 2 - 3 (2 bit)
SSIZE : SSIZE
bits : 4 - 5 (2 bit)
DSIZE : DSIZE
bits : 6 - 7 (2 bit)
SINCOS : SINCOS
bits : 8 - 9 (2 bit)
DINCOS : DINCOS
bits : 10 - 11 (2 bit)
SBURST : SBURST
bits : 12 - 14 (3 bit)
DBURST : DBURST
bits : 15 - 17 (3 bit)
TLEN : TLEN
bits : 18 - 24 (7 bit)
PKE : PKE
bits : 25 - 25 (1 bit)
PAM : PAM
bits : 26 - 27 (2 bit)
TRGM : TRGM
bits : 28 - 29 (2 bit)
SWRM : SWRM
bits : 30 - 30 (1 bit)
BWM : BWM
bits : 31 - 31 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNDT : BNDT
bits : 0 - 16 (17 bit)
BRSUM : BRSUM
bits : 18 - 18 (1 bit)
BRDUM : BRDUM
bits : 19 - 19 (1 bit)
BRC : BRC
bits : 20 - 31 (12 bit)
In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUV : SUV
bits : 0 - 15 (16 bit)
DUV : DUV
bits : 16 - 31 (16 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LAR : LAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL : TSEL
bits : 0 - 5 (6 bit)
SBUS : SBUS
bits : 16 - 16 (1 bit)
DBUS : DBUS
bits : 17 - 17 (1 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAR : MAR
bits : 0 - 31 (32 bit)
In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDR : MDR
bits : 0 - 31 (32 bit)
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