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SAI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

SAI_GCR

SAI_ASLOTR

SAI_AIM

SAI_ASR

SAI_ACLRFR

SAI_ADR

SAI_BCR1

SAI_BCR2

SAI_BFRCR

SAI_BSLOTR

SAI_BIM

SAI_BSR

SAI_BCLRFR

SAI_HWCFGR

SAI_VERR

SAI_IPIDR

SAI_SIDR

SAI_ACR1

SAI_BDR

SAI_PDMCR

SAI_PDMDLY

SAI_ACR2

SAI_AFRCR


SAI_GCR

Global configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_GCR SAI_GCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNCIN SYNCOUT

SYNCIN : SYNCIN
bits : 0 - 1 (2 bit)

SYNCOUT : SYNCOUT
bits : 4 - 5 (2 bit)


SAI_ASLOTR

This register has no meaning in and SPDIF audio protocol
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_ASLOTR SAI_ASLOTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FBOFF SLOTSZ NBSLOT SLOTEN

FBOFF : FBOFF
bits : 0 - 4 (5 bit)

SLOTSZ : SLOTSZ
bits : 6 - 7 (2 bit)

NBSLOT : NBSLOT
bits : 8 - 11 (4 bit)

SLOTEN : SLOTEN
bits : 16 - 31 (16 bit)


SAI_AIM

Interrupt mask register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_AIM SAI_AIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVRUDRIE MUTEDETIE WCKCFGIE FREQIE CNRDYIE AFSDETIE LFSDETIE

OVRUDRIE : OVRUDRIE
bits : 0 - 0 (1 bit)

MUTEDETIE : MUTEDETIE
bits : 1 - 1 (1 bit)

WCKCFGIE : WCKCFGIE
bits : 2 - 2 (1 bit)

FREQIE : FREQIE
bits : 3 - 3 (1 bit)

CNRDYIE : CNRDYIE
bits : 4 - 4 (1 bit)

AFSDETIE : AFSDETIE
bits : 5 - 5 (1 bit)

LFSDETIE : LFSDETIE
bits : 6 - 6 (1 bit)


SAI_ASR

Status register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SAI_ASR SAI_ASR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVRUDR MUTEDET WCKCFG FREQ CNRDY AFSDET LFSDET FLVL

OVRUDR : OVRUDR
bits : 0 - 0 (1 bit)

MUTEDET : MUTEDET
bits : 1 - 1 (1 bit)

WCKCFG : WCKCFG
bits : 2 - 2 (1 bit)

FREQ : FREQ
bits : 3 - 3 (1 bit)

CNRDY : CNRDY
bits : 4 - 4 (1 bit)

AFSDET : AFSDET
bits : 5 - 5 (1 bit)

LFSDET : LFSDET
bits : 6 - 6 (1 bit)

FLVL : FLVL
bits : 16 - 18 (3 bit)


SAI_ACLRFR

Clear flag register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SAI_ACLRFR SAI_ACLRFR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COVRUDR CMUTEDET CWCKCFG CCNRDY CAFSDET CLFSDET

COVRUDR : COVRUDR
bits : 0 - 0 (1 bit)

CMUTEDET : CMUTEDET
bits : 1 - 1 (1 bit)

CWCKCFG : CWCKCFG
bits : 2 - 2 (1 bit)

CCNRDY : CCNRDY
bits : 4 - 4 (1 bit)

CAFSDET : CAFSDET
bits : 5 - 5 (1 bit)

CLFSDET : CLFSDET
bits : 6 - 6 (1 bit)


SAI_ADR

Data register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_ADR SAI_ADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA
bits : 0 - 31 (32 bit)


SAI_BCR1

Configuration register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_BCR1 SAI_BCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE PRTCFG DS LSBFIRST CKSTR SYNCEN MONO OUTDRIV SAIEN DMAEN NODIV MCKDIV OSR MCKEN

MODE : MODE
bits : 0 - 1 (2 bit)

PRTCFG : PRTCFG
bits : 2 - 3 (2 bit)

DS : DS
bits : 5 - 7 (3 bit)

LSBFIRST : LSBFIRST
bits : 8 - 8 (1 bit)

CKSTR : CKSTR
bits : 9 - 9 (1 bit)

SYNCEN : SYNCEN
bits : 10 - 11 (2 bit)

MONO : MONO
bits : 12 - 12 (1 bit)

OUTDRIV : OUTDRIV
bits : 13 - 13 (1 bit)

SAIEN : SAIEN
bits : 16 - 16 (1 bit)

DMAEN : DMAEN
bits : 17 - 17 (1 bit)

NODIV : NODIV
bits : 19 - 19 (1 bit)

MCKDIV : MCKDIV
bits : 20 - 25 (6 bit)

OSR : OSR
bits : 26 - 26 (1 bit)

MCKEN : MCKEN
bits : 27 - 27 (1 bit)


SAI_BCR2

Configuration register 2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_BCR2 SAI_BCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH FFLUSH TRIS MUTE MUTEVAL MUTECNT CPL COMP

FTH : FTH
bits : 0 - 2 (3 bit)
access : read-write

FFLUSH : FFLUSH
bits : 3 - 3 (1 bit)
access : write-only

TRIS : TRIS
bits : 4 - 4 (1 bit)
access : read-write

MUTE : MUTE
bits : 5 - 5 (1 bit)
access : read-write

MUTEVAL : MUTEVAL
bits : 6 - 6 (1 bit)
access : read-write

MUTECNT : MUTECNT
bits : 7 - 12 (6 bit)
access : read-write

CPL : CPL
bits : 13 - 13 (1 bit)
access : read-write

COMP : COMP
bits : 14 - 15 (2 bit)
access : read-write


SAI_BFRCR

This register has no meaning in and SPDIF audio protocol
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_BFRCR SAI_BFRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRL FSALL FSDEF FSPOL FSOFF

FRL : FRL
bits : 0 - 7 (8 bit)
access : read-write

FSALL : FSALL
bits : 8 - 14 (7 bit)
access : read-write

FSDEF : FSDEF
bits : 16 - 16 (1 bit)
access : read-only

FSPOL : FSPOL
bits : 17 - 17 (1 bit)
access : read-write

FSOFF : FSOFF
bits : 18 - 18 (1 bit)
access : read-write


SAI_BSLOTR

This register has no meaning in and SPDIF audio protocol
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_BSLOTR SAI_BSLOTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FBOFF SLOTSZ NBSLOT SLOTEN

FBOFF : FBOFF
bits : 0 - 4 (5 bit)

SLOTSZ : SLOTSZ
bits : 6 - 7 (2 bit)

NBSLOT : NBSLOT
bits : 8 - 11 (4 bit)

SLOTEN : SLOTEN
bits : 16 - 31 (16 bit)


SAI_BIM

Interrupt mask register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_BIM SAI_BIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVRUDRIE MUTEDETIE WCKCFGIE FREQIE CNRDYIE AFSDETIE LFSDETIE

OVRUDRIE : OVRUDRIE
bits : 0 - 0 (1 bit)

MUTEDETIE : MUTEDETIE
bits : 1 - 1 (1 bit)

WCKCFGIE : WCKCFGIE
bits : 2 - 2 (1 bit)

FREQIE : FREQIE
bits : 3 - 3 (1 bit)

CNRDYIE : CNRDYIE
bits : 4 - 4 (1 bit)

AFSDETIE : AFSDETIE
bits : 5 - 5 (1 bit)

LFSDETIE : LFSDETIE
bits : 6 - 6 (1 bit)


SAI_BSR

Status register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SAI_BSR SAI_BSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVRUDR MUTEDET WCKCFG FREQ CNRDY AFSDET LFSDET FLVL

OVRUDR : OVRUDR
bits : 0 - 0 (1 bit)

MUTEDET : MUTEDET
bits : 1 - 1 (1 bit)

WCKCFG : WCKCFG
bits : 2 - 2 (1 bit)

FREQ : FREQ
bits : 3 - 3 (1 bit)

CNRDY : CNRDY
bits : 4 - 4 (1 bit)

AFSDET : AFSDET
bits : 5 - 5 (1 bit)

LFSDET : LFSDET
bits : 6 - 6 (1 bit)

FLVL : FLVL
bits : 16 - 18 (3 bit)


SAI_BCLRFR

Clear flag register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SAI_BCLRFR SAI_BCLRFR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COVRUDR CMUTEDET CWCKCFG CCNRDY CAFSDET CLFSDET

COVRUDR : COVRUDR
bits : 0 - 0 (1 bit)

CMUTEDET : CMUTEDET
bits : 1 - 1 (1 bit)

CWCKCFG : CWCKCFG
bits : 2 - 2 (1 bit)

CCNRDY : CCNRDY
bits : 4 - 4 (1 bit)

CAFSDET : CAFSDET
bits : 5 - 5 (1 bit)

CLFSDET : CLFSDET
bits : 6 - 6 (1 bit)


SAI_HWCFGR

SAI hardware configuration register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SAI_HWCFGR SAI_HWCFGR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO_SIZE SPDIF_PDM OPTION_REGOUT

FIFO_SIZE : FIFO_SIZE
bits : 0 - 7 (8 bit)

SPDIF_PDM : SPDIF_PDM
bits : 8 - 11 (4 bit)

OPTION_REGOUT : OPTION_REGOUT
bits : 12 - 19 (8 bit)


SAI_VERR

SAI version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SAI_VERR SAI_VERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINREV MAJREV

MINREV : MINREV
bits : 0 - 3 (4 bit)

MAJREV : MAJREV
bits : 4 - 7 (4 bit)


SAI_IPIDR

SAI identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SAI_IPIDR SAI_IPIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID

ID : ID
bits : 0 - 31 (32 bit)


SAI_SIDR

SAI size identification register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SAI_SIDR SAI_SIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SID

SID : SID
bits : 0 - 31 (32 bit)


SAI_ACR1

Configuration register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_ACR1 SAI_ACR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE PRTCFG DS LSBFIRST CKSTR SYNCEN MONO OUTDRIV SAIEN DMAEN NODIV MCKDIV OSR MCKEN

MODE : MODE
bits : 0 - 1 (2 bit)

PRTCFG : PRTCFG
bits : 2 - 3 (2 bit)

DS : DS
bits : 5 - 7 (3 bit)

LSBFIRST : LSBFIRST
bits : 8 - 8 (1 bit)

CKSTR : CKSTR
bits : 9 - 9 (1 bit)

SYNCEN : SYNCEN
bits : 10 - 11 (2 bit)

MONO : MONO
bits : 12 - 12 (1 bit)

OUTDRIV : OUTDRIV
bits : 13 - 13 (1 bit)

SAIEN : SAIEN
bits : 16 - 16 (1 bit)

DMAEN : DMAEN
bits : 17 - 17 (1 bit)

NODIV : NODIV
bits : 19 - 19 (1 bit)

MCKDIV : MCKDIV
bits : 20 - 25 (6 bit)

OSR : OSR
bits : 26 - 26 (1 bit)

MCKEN : MCKEN
bits : 27 - 27 (1 bit)


SAI_BDR

Data register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_BDR SAI_BDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA
bits : 0 - 31 (32 bit)


SAI_PDMCR

PDM control register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_PDMCR SAI_PDMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMEN MICNBR CKEN1 CKEN2 CKEN3 CKEN4

PDMEN : PDMEN
bits : 0 - 0 (1 bit)

MICNBR : MICNBR
bits : 4 - 5 (2 bit)

CKEN1 : CKEN1
bits : 8 - 8 (1 bit)

CKEN2 : CKEN2
bits : 9 - 9 (1 bit)

CKEN3 : CKEN3
bits : 10 - 10 (1 bit)

CKEN4 : CKEN4
bits : 11 - 11 (1 bit)


SAI_PDMDLY

PDM delay register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_PDMDLY SAI_PDMDLY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLYM1L DLYM1R DLYM2L DLYM2R DLYM3L DLYM3R DLYM4L DLYM4R

DLYM1L : DLYM1L
bits : 0 - 2 (3 bit)

DLYM1R : DLYM1R
bits : 4 - 6 (3 bit)

DLYM2L : DLYM2L
bits : 8 - 10 (3 bit)

DLYM2R : DLYM2R
bits : 12 - 14 (3 bit)

DLYM3L : DLYM3L
bits : 16 - 18 (3 bit)

DLYM3R : DLYM3R
bits : 20 - 22 (3 bit)

DLYM4L : DLYM4L
bits : 24 - 26 (3 bit)

DLYM4R : DLYM4R
bits : 28 - 30 (3 bit)


SAI_ACR2

Configuration register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_ACR2 SAI_ACR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH FFLUSH TRIS MUTE MUTEVAL MUTECNT CPL COMP

FTH : FTH
bits : 0 - 2 (3 bit)
access : read-write

FFLUSH : FFLUSH
bits : 3 - 3 (1 bit)
access : write-only

TRIS : TRIS
bits : 4 - 4 (1 bit)
access : read-write

MUTE : MUTE
bits : 5 - 5 (1 bit)
access : read-write

MUTEVAL : MUTEVAL
bits : 6 - 6 (1 bit)
access : read-write

MUTECNT : MUTECNT
bits : 7 - 12 (6 bit)
access : read-write

CPL : CPL
bits : 13 - 13 (1 bit)
access : read-write

COMP : COMP
bits : 14 - 15 (2 bit)
access : read-write


SAI_AFRCR

This register has no meaning in and SPDIF audio protocol
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAI_AFRCR SAI_AFRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRL FSALL FSDEF FSPOL FSOFF

FRL : FRL
bits : 0 - 7 (8 bit)
access : read-write

FSALL : FSALL
bits : 8 - 14 (7 bit)
access : read-write

FSDEF : FSDEF
bits : 16 - 16 (1 bit)
access : read-only

FSPOL : FSPOL
bits : 17 - 17 (1 bit)
access : read-write

FSOFF : FSOFF
bits : 18 - 18 (1 bit)
access : read-write



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