\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
LPTIM interrupt and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMPM : CMPM
bits : 0 - 0 (1 bit)
ARRM : ARRM
bits : 1 - 1 (1 bit)
EXTTRIG : EXTTRIG
bits : 2 - 2 (1 bit)
CMPOK : CMPOK
bits : 3 - 3 (1 bit)
ARROK : ARROK
bits : 4 - 4 (1 bit)
UP : UP
bits : 5 - 5 (1 bit)
DOWN : DOWN
bits : 6 - 6 (1 bit)
LPTIM control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : ENABLE
bits : 0 - 0 (1 bit)
SNGSTRT : SNGSTRT
bits : 1 - 1 (1 bit)
CNTSTRT : CNTSTRT
bits : 2 - 2 (1 bit)
COUNTRST : COUNTRST
bits : 3 - 3 (1 bit)
RSTARE : RSTARE
bits : 4 - 4 (1 bit)
LPTIM compare register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : CMP
bits : 0 - 15 (16 bit)
LPTIM autoreload register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARR : ARR
bits : 0 - 15 (16 bit)
LPTIM counter register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : CNT
bits : 0 - 15 (16 bit)
LPTIM configuration register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN1SEL : IN1SEL
bits : 0 - 1 (2 bit)
IN2SEL : IN2SEL
bits : 4 - 5 (2 bit)
LPTIM 2 peripheral hardware configuration register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFG1 : CFG1
bits : 0 - 7 (8 bit)
CFG2 : CFG2
bits : 8 - 15 (8 bit)
CFG3 : CFG3
bits : 16 - 19 (4 bit)
CFG4 : CFG4
bits : 24 - 31 (8 bit)
LPTIM peripheral version identification register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINREV : MINREV
bits : 0 - 3 (4 bit)
MAJREV : MAJREV
bits : 4 - 7 (4 bit)
LPTIM peripheral type identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P_ID : P_ID
bits : 0 - 31 (32 bit)
LPTIM registers map size identification register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
S_ID : S_ID
bits : 0 - 31 (32 bit)
LPTIM interrupt clear register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CMPMCF : CMPMCF
bits : 0 - 0 (1 bit)
ARRMCF : ARRMCF
bits : 1 - 1 (1 bit)
EXTTRIGCF : EXTTRIGCF
bits : 2 - 2 (1 bit)
CMPOKCF : CMPOKCF
bits : 3 - 3 (1 bit)
ARROKCF : ARROKCF
bits : 4 - 4 (1 bit)
UPCF : UPCF
bits : 5 - 5 (1 bit)
DOWNCF : DOWNCF
bits : 6 - 6 (1 bit)
LPTIM interrupt enable register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPMIE : CMPMIE
bits : 0 - 0 (1 bit)
ARRMIE : ARRMIE
bits : 1 - 1 (1 bit)
EXTTRIGIE : EXTTRIGIE
bits : 2 - 2 (1 bit)
CMPOKIE : CMPOKIE
bits : 3 - 3 (1 bit)
ARROKIE : ARROKIE
bits : 4 - 4 (1 bit)
UPIE : UPIE
bits : 5 - 5 (1 bit)
DOWNIE : DOWNIE
bits : 6 - 6 (1 bit)
LPTIM configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKSEL : CKSEL
bits : 0 - 0 (1 bit)
CKPOL : CKPOL
bits : 1 - 2 (2 bit)
CKFLT : CKFLT
bits : 3 - 4 (2 bit)
TRGFLT : TRGFLT
bits : 6 - 7 (2 bit)
PRESC : PRESC
bits : 9 - 11 (3 bit)
TRIGSEL : TRIGSEL
bits : 13 - 15 (3 bit)
TRIGEN : TRIGEN
bits : 17 - 18 (2 bit)
TIMOUT : TIMOUT
bits : 19 - 19 (1 bit)
WAVE : WAVE
bits : 20 - 20 (1 bit)
WAVPOL : WAVPOL
bits : 21 - 21 (1 bit)
PRELOAD : PRELOAD
bits : 22 - 22 (1 bit)
COUNTMODE : COUNTMODE
bits : 23 - 23 (1 bit)
ENC : ENC
bits : 24 - 24 (1 bit)
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