\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Reset on any system reset. This register provides write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPDS : LPDS
bits : 0 - 0 (1 bit)
LPCFG : LPCFG
bits : 1 - 1 (1 bit)
LVDS : LVDS
bits : 2 - 2 (1 bit)
PVDEN : PVDEN
bits : 4 - 4 (1 bit)
PLS : PLS
bits : 5 - 7 (3 bit)
DBP : DBP
bits : 8 - 8 (1 bit)
AVDEN : AVDEN
bits : 16 - 16 (1 bit)
ALS : ALS
bits : 17 - 18 (2 bit)
See individual bits for reset condition. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDDS : PDDS
bits : 0 - 0 (1 bit)
access : read-write
CSTBYDIS : CSTBYDIS
bits : 3 - 3 (1 bit)
access : read-write
STOPF : STOPF
bits : 5 - 5 (1 bit)
access : read-only
SBF : SBF
bits : 6 - 6 (1 bit)
access : read-only
SBFMPU : SBFMPU
bits : 7 - 7 (1 bit)
access : read-only
CSSF : CSSF
bits : 9 - 9 (1 bit)
access : read-write
STANDBYWFIL2 : STANDBYWFIL2
bits : 15 - 15 (1 bit)
access : read-only
See individual bits for reset condition. Access 6 wait states when writing this register. This register is always non-secure. When a system reset occurs during the register write cycle the written data is not guaranteed.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDDS : PDDS
bits : 0 - 0 (1 bit)
access : read-write
STOPF : STOPF
bits : 5 - 5 (1 bit)
access : read-only
SBF : SBF
bits : 6 - 6 (1 bit)
access : read-only
CSSF : CSSF
bits : 9 - 9 (1 bit)
access : read-write
DEEPSLEEP : DEEPSLEEP
bits : 15 - 15 (1 bit)
access : read-only
Not reset by wakeup from Standby mode, but by any application reset (such as NRST, IWDG). Access 6 wait states when writing this register (when clearing a WKUPF, the AHB write access completes after the WKUPF has cleared). This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access on individual WKUPC[6:1], WKUPP[6:1] bits and WKUPPUPD[6:1] bit pairs are discarded when the corresponding WKUPEN[6:1] bit in PWR MPU wakeup enable register (PWR_MPUWKUPENR) is set. No bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKUPC1 : WKUPC1
bits : 0 - 0 (1 bit)
WKUPC2 : WKUPC2
bits : 1 - 1 (1 bit)
WKUPC3 : WKUPC3
bits : 2 - 2 (1 bit)
WKUPC4 : WKUPC4
bits : 3 - 3 (1 bit)
WKUPC5 : WKUPC5
bits : 4 - 4 (1 bit)
WKUPC6 : WKUPC6
bits : 5 - 5 (1 bit)
WKUPP1 : WKUPP1
bits : 8 - 8 (1 bit)
WKUPP2 : WKUPP2
bits : 9 - 9 (1 bit)
WKUPP3 : WKUPP3
bits : 10 - 10 (1 bit)
WKUPP4 : WKUPP4
bits : 11 - 11 (1 bit)
WKUPP5 : WKUPP5
bits : 12 - 12 (1 bit)
WKUPP6 : WKUPP6
bits : 13 - 13 (1 bit)
WKUPPUPD1 : WKUPPUPD1
bits : 16 - 17 (2 bit)
WKUPPUPD2 : WKUPPUPD2
bits : 18 - 19 (2 bit)
WKUPPUPD3 : WKUPPUPD3
bits : 20 - 21 (2 bit)
WKUPPUPD4 : WKUPPUPD4
bits : 22 - 23 (2 bit)
WKUPPUPD5 : WKUPPUPD5
bits : 24 - 25 (2 bit)
WKUPPUPD6 : WKUPPUPD6
bits : 26 - 27 (2 bit)
Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WKUPF1 : WKUPF1
bits : 0 - 0 (1 bit)
WKUPF2 : WKUPF2
bits : 1 - 1 (1 bit)
WKUPF3 : WKUPF3
bits : 2 - 2 (1 bit)
WKUPF4 : WKUPF4
bits : 3 - 3 (1 bit)
WKUPF5 : WKUPF5
bits : 4 - 4 (1 bit)
WKUPF6 : WKUPF6
bits : 5 - 5 (1 bit)
Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...). Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access is discarded and a bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKUPEN1 : WKUPEN1
bits : 0 - 0 (1 bit)
WKUPEN2 : WKUPEN2
bits : 1 - 1 (1 bit)
WKUPEN3 : WKUPEN3
bits : 2 - 2 (1 bit)
WKUPEN4 : WKUPEN4
bits : 3 - 3 (1 bit)
WKUPEN5 : WKUPEN5
bits : 4 - 4 (1 bit)
WKUPEN6 : WKUPEN6
bits : 5 - 5 (1 bit)
Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...) Access 6 wait states when writing this register. When a system reset occurs during the register write cycle the written data is not guaranteed.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKUPEN1 : WKUPEN1
bits : 0 - 0 (1 bit)
WKUPEN2 : WKUPEN2
bits : 1 - 1 (1 bit)
WKUPEN3 : WKUPEN3
bits : 2 - 2 (1 bit)
WKUPEN4 : WKUPEN4
bits : 3 - 3 (1 bit)
WKUPEN5 : WKUPEN5
bits : 4 - 4 (1 bit)
WKUPEN6 : WKUPEN6
bits : 5 - 5 (1 bit)
PWR IP version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINREV : MINREV
bits : 0 - 3 (4 bit)
MAJREV : MAJREV
bits : 4 - 7 (4 bit)
PWR IP identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPID : IPID
bits : 0 - 31 (32 bit)
PWR size ID register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SID : SID
bits : 0 - 31 (32 bit)
Reset on any system reset.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PVDO : PVDO
bits : 4 - 4 (1 bit)
AVDO : AVDO
bits : 16 - 16 (1 bit)
Not reset by wakeup from Standby mode, Application reset (NRST, IWDG, ...) and VDD POR, but reset only by VSW POR and VSWRST. Access 6 wait states when writing this register. After reset the register is write-protected and the DBP bit in the PWR control register 1 (PWR_CR1) has to be set before it can be written. When DBP is cleared, there is no bus errors generated when writing this register. This register shall not be accessed when the RCC VSWRST register bit in Section10.7.89: RCC Backup Domain Control Register (RCC_BDCR) resets the VSW domain. This register provides Write access security when enabled by TZEN register bit in Section10.7.2: RCC TrustZone Control Register (RCC_TZCR). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BREN : BREN
bits : 0 - 0 (1 bit)
access : read-write
RREN : RREN
bits : 1 - 1 (1 bit)
access : read-write
MONEN : MONEN
bits : 4 - 4 (1 bit)
access : read-write
BRRDY : BRRDY
bits : 16 - 16 (1 bit)
access : read-only
RRRDY : RRRDY
bits : 17 - 17 (1 bit)
access : read-only
VBATL : VBATL
bits : 20 - 20 (1 bit)
access : read-only
VBATH : VBATH
bits : 21 - 21 (1 bit)
access : read-only
TEMPL : TEMPL
bits : 22 - 22 (1 bit)
access : read-only
TEMPH : TEMPH
bits : 23 - 23 (1 bit)
access : read-only
Not reset by wakeup from Standby mode and Application reset (such as NRST, IWDG) but only reset by VDD POR. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBE : VBE
bits : 8 - 8 (1 bit)
access : read-write
VBRS : VBRS
bits : 9 - 9 (1 bit)
access : read-write
DDRSREN : DDRSREN
bits : 10 - 10 (1 bit)
access : read-write
DDRSRDIS : DDRSRDIS
bits : 11 - 11 (1 bit)
access : read-write
DDRRETEN : DDRRETEN
bits : 12 - 12 (1 bit)
access : read-write
POPL : POPL
bits : 17 - 21 (5 bit)
access : read-write
USB33DEN : USB33DEN
bits : 24 - 24 (1 bit)
access : read-write
USB33RDY : USB33RDY
bits : 26 - 26 (1 bit)
access : read-only
REG18EN : REG18EN
bits : 28 - 28 (1 bit)
access : read-write
REG18RDY : REG18RDY
bits : 29 - 29 (1 bit)
access : read-only
REG11EN : REG11EN
bits : 30 - 30 (1 bit)
access : read-write
REG11RDY : REG11RDY
bits : 31 - 31 (1 bit)
access : read-only
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