\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
RCC_TZAHB6RSTSETR (TZAHB6RSTSETR)
RCC_TZAHB6RSTCLRR (TZAHB6RSTCLRR)
RCC_MP_APB4ENSETR (MP_APB4ENSETR)
RCC_MP_APB4ENCLRR (MP_APB4ENCLRR)
RCC_MP_APB5ENSETR (MP_APB5ENSETR)
RCC_MP_APB5ENCLRR (MP_APB5ENCLRR)
RCC_MP_AHB5ENSETR (MP_AHB5ENSETR)
RCC_MP_AHB5ENCLRR (MP_AHB5ENCLRR)
RCC_MP_AHB6ENSETR (MP_AHB6ENSETR)
RCC_MP_AHB6ENCLRR (MP_AHB6ENCLRR)
RCC_MP_TZAHB6ENSETR (MP_TZAHB6ENSETR)
RCC_MP_TZAHB6ENCLRR (MP_TZAHB6ENCLRR)
RCC_MC_APB4ENSETR (MC_APB4ENSETR)
RCC_MC_APB4ENCLRR (MC_APB4ENCLRR)
RCC_MC_APB5ENSETR (MC_APB5ENSETR)
RCC_MC_APB5ENCLRR (MC_APB5ENCLRR)
RCC_MC_AHB5ENSETR (MC_AHB5ENSETR)
RCC_MC_AHB5ENCLRR (MC_AHB5ENCLRR)
RCC_MC_AHB6ENSETR (MC_AHB6ENSETR)
RCC_MC_AHB6ENCLRR (MC_AHB6ENCLRR)
RCC_MP_APB4LPENSETR (MP_APB4LPENSETR)
RCC_MP_APB4LPENCLRR (MP_APB4LPENCLRR)
RCC_MP_APB5LPENSETR (MP_APB5LPENSETR)
RCC_MP_APB5LPENCLRR (MP_APB5LPENCLRR)
RCC_MP_AHB5LPENSETR (MP_AHB5LPENSETR)
RCC_MP_AHB5LPENCLRR (MP_AHB5LPENCLRR)
RCC_MP_AHB6LPENSETR (MP_AHB6LPENSETR)
RCC_MP_AHB6LPENCLRR (MP_AHB6LPENCLRR)
RCC_MP_TZAHB6LPENSETR (MP_TZAHB6LPENSETR)
RCC_MP_TZAHB6LPENCLRR (MP_TZAHB6LPENCLRR)
RCC_MC_APB4LPENSETR (MC_APB4LPENSETR)
RCC_MC_APB4LPENCLRR (MC_APB4LPENCLRR)
RCC_MC_APB5LPENSETR (MC_APB5LPENSETR)
RCC_MC_APB5LPENCLRR (MC_APB5LPENCLRR)
RCC_MC_AHB5LPENSETR (MC_AHB5LPENSETR)
RCC_MC_AHB5LPENCLRR (MC_AHB5LPENCLRR)
RCC_MC_AHB6LPENSETR (MC_AHB6LPENSETR)
RCC_MC_AHB6LPENCLRR (MC_AHB6LPENCLRR)
RCC_MP_GRSTCSETR (MP_GRSTCSETR)
RCC_MP_IWDGFZSETR (MP_IWDGFZSETR)
RCC_MP_IWDGFZCLRR (MP_IWDGFZCLRR)
RCC_SPI2S1CKSELR (SPI2S1CKSELR)
RCC_SPI2S23CKSELR (SPI2S23CKSELR)
RCC_UART24CKSELR (UART24CKSELR)
RCC_UART35CKSELR (UART35CKSELR)
RCC_UART78CKSELR (UART78CKSELR)
RCC_SDMMC12CKSELR (SDMMC12CKSELR)
RCC_SDMMC3CKSELR (SDMMC3CKSELR)
RCC_LPTIM45CKSELR (LPTIM45CKSELR)
RCC_LPTIM23CKSELR (LPTIM23CKSELR)
RCC_LPTIM1CKSELR (LPTIM1CKSELR)
RCC_MP_APB1ENSETR (MP_APB1ENSETR)
RCC_MP_APB1ENCLRR (MP_APB1ENCLRR)
RCC_MP_APB2ENSETR (MP_APB2ENSETR)
RCC_MP_APB2ENCLRR (MP_APB2ENCLRR)
RCC_MP_APB3ENSETR (MP_APB3ENSETR)
RCC_MP_APB3ENCLRR (MP_APB3ENCLRR)
RCC_MP_AHB2ENSETR (MP_AHB2ENSETR)
RCC_MP_AHB2ENCLRR (MP_AHB2ENCLRR)
RCC_MP_AHB3ENSETR (MP_AHB3ENSETR)
RCC_MP_AHB3ENCLRR (MP_AHB3ENCLRR)
RCC_MP_AHB4ENSETR (MP_AHB4ENSETR)
RCC_MP_AHB4ENCLRR (MP_AHB4ENCLRR)
RCC_MP_MLAHBENSETR (MP_MLAHBENSETR)
RCC_MP_MLAHBENCLRR (MP_MLAHBENCLRR)
RCC_MC_APB1ENSETR (MC_APB1ENSETR)
RCC_MC_APB1ENCLRR (MC_APB1ENCLRR)
RCC_MC_APB2ENSETR (MC_APB2ENSETR)
RCC_MC_APB2ENCLRR (MC_APB2ENCLRR)
RCC_MC_APB3ENSETR (MC_APB3ENSETR)
RCC_MC_APB3ENCLRR (MC_APB3ENCLRR)
RCC_MC_AHB2ENSETR (MC_AHB2ENSETR)
RCC_MC_AHB2ENCLRR (MC_AHB2ENCLRR)
RCC_MC_AHB3ENSETR (MC_AHB3ENSETR)
RCC_MC_AHB3ENCLRR (MC_AHB3ENCLRR)
RCC_MC_AHB4ENSETR (MC_AHB4ENSETR)
RCC_MC_AHB4ENCLRR (MC_AHB4ENCLRR)
RCC_MC_AXIMENSETR (MC_AXIMENSETR)
RCC_MC_AXIMENCLRR (MC_AXIMENCLRR)
RCC_MC_MLAHBENSETR (MC_MLAHBENSETR)
RCC_MC_MLAHBENCLRR (MC_MLAHBENCLRR)
RCC_MP_APB1LPENSETR (MP_APB1LPENSETR)
RCC_MP_APB1LPENCLRR (MP_APB1LPENCLRR)
RCC_MP_APB2LPENSETR (MP_APB2LPENSETR)
RCC_MP_APB2LPENCLRR (MP_APB2LPENCLRR)
RCC_MP_APB3LPENSETR (MP_APB3LPENSETR)
RCC_MP_APB3LPENCLRR (MP_APB3LPENCLRR)
RCC_MP_AHB2LPENSETR (MP_AHB2LPENSETR)
RCC_MP_AHB2LPENCLRR (MP_AHB2LPENCLRR)
RCC_MP_AHB3LPENSETR (MP_AHB3LPENSETR)
RCC_MP_AHB3LPENCLRR (MP_AHB3LPENCLRR)
RCC_MP_AHB4LPENSETR (MP_AHB4LPENSETR)
RCC_MP_AHB4LPENCLRR (MP_AHB4LPENCLRR)
RCC_MP_AXIMLPENSETR (MP_AXIMLPENSETR)
RCC_MP_AXIMLPENCLRR (MP_AXIMLPENCLRR)
RCC_MP_MLAHBLPENSETR (MP_MLAHBLPENSETR)
RCC_MP_MLAHBLPENCLRR (MP_MLAHBLPENCLRR)
RCC_MC_APB1LPENSETR (MC_APB1LPENSETR)
RCC_MC_APB1LPENCLRR (MC_APB1LPENCLRR)
RCC_MC_APB2LPENSETR (MC_APB2LPENSETR)
RCC_MC_APB2LPENCLRR (MC_APB2LPENCLRR)
RCC_MC_APB3LPENSETR (MC_APB3LPENSETR)
RCC_MC_APB3LPENCLRR (MC_APB3LPENCLRR)
RCC_MC_AHB2LPENSETR (MC_AHB2LPENSETR)
RCC_MC_AHB2LPENCLRR (MC_AHB2LPENCLRR)
RCC_MC_AHB3LPENSETR (MC_AHB3LPENSETR)
RCC_MC_AHB3LPENCLRR (MC_AHB3LPENCLRR)
RCC_MC_AHB4LPENSETR (MC_AHB4LPENSETR)
RCC_MC_AHB4LPENCLRR (MC_AHB4LPENCLRR)
RCC_MC_AXIMLPENSETR (MC_AXIMLPENSETR)
RCC_MC_AXIMLPENCLRR (MC_AXIMLPENCLRR)
RCC_MC_MLAHBLPENSETR (MC_MLAHBLPENSETR)
RCC_MC_MLAHBLPENCLRR (MC_MLAHBLPENCLRR)
This register is used to switch the RCC into secure mode. This register can only be accessed in secure mode.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TZEN : TZEN
bits : 0 - 0 (1 bit)
MCKPROT : MCKPROT
bits : 1 - 1 (1 bit)
This register is used to control the oscillators.Writing to this register has no effect, writing will clear the corresponding bits. Reading will give the effective values of the enable bits.If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSION : HSION
bits : 0 - 0 (1 bit)
HSIKERON : HSIKERON
bits : 1 - 1 (1 bit)
CSION : CSION
bits : 4 - 4 (1 bit)
CSIKERON : CSIKERON
bits : 5 - 5 (1 bit)
DIGBYP : DIGBYP
bits : 7 - 7 (1 bit)
HSEON : HSEON
bits : 8 - 8 (1 bit)
HSEKERON : HSEKERON
bits : 9 - 9 (1 bit)
HSEBYP : HSEBYP
bits : 10 - 10 (1 bit)
This register is used to control the HOLD boot function when the system exits from Standby. Refer to Section: MCU HOLD_BOOT after processor reset. This register is reset when a system reset occurs, but not when the circuit exits from Standby (app_rst reset).If TZEN = , this register can only be modified in secure mode. This register can only be accessed by the MPU.
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_BEN : MCU_BEN
bits : 0 - 0 (1 bit)
MPU_BEN : MPU_BEN
bits : 1 - 1 (1 bit)
Writing has no effect, reading will return the values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STPREQ_P0 : STPREQ_P0
bits : 0 - 0 (1 bit)
STPREQ_P1 : STPREQ_P1
bits : 1 - 1 (1 bit)
Writing has no effect, reading will return the effective values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STPREQ_P0 : STPREQ_P0
bits : 0 - 0 (1 bit)
STPREQ_P1 : STPREQ_P1
bits : 1 - 1 (1 bit)
The register contains global control bits. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOT_MCU : BOOT_MCU
bits : 0 - 0 (1 bit)
This register is used to control the behavior of the warm reset. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDCTLEN : RDCTLEN
bits : 0 - 0 (1 bit)
RSTTO : RSTTO
bits : 8 - 14 (7 bit)
This register provides a status of the RDCTL. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSTTOV : RSTTOV
bits : 8 - 14 (7 bit)
This register is used to control the LSE function. Wait states are inserted in case of successive write accesses to this register. The number of wait states may be up to 7 cycles of AHB4 clock.After a system reset, the register RCC_BDCR is write-protected. In order to modify this register, the DBP bit in the PWR control register 1 (PWR_CR1) has to be set to . Bits of RCC_BDCR register are only reset after a backup domain reset: nreset_vsw (see Section10.3.6: Backup domain reset). Any other internal or external reset will not have any effect on these bits.This register is located into the VSW domain. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSEON : LSEON
bits : 0 - 0 (1 bit)
access : read-write
LSEBYP : LSEBYP
bits : 1 - 1 (1 bit)
access : read-write
LSERDY : LSERDY
bits : 2 - 2 (1 bit)
access : read-only
DIGBYP : DIGBYP
bits : 3 - 3 (1 bit)
access : read-only
LSEDRV : LSEDRV
bits : 4 - 5 (2 bit)
access : read-write
LSECSSON : LSECSSON
bits : 8 - 8 (1 bit)
access : read-write
LSECSSD : LSECSSD
bits : 9 - 9 (1 bit)
access : read-only
RTCSRC : RTCSRC
bits : 16 - 17 (2 bit)
access : read-only
RTCCKEN : RTCCKEN
bits : 20 - 20 (1 bit)
access : read-write
VSWRST : VSWRST
bits : 31 - 31 (1 bit)
access : read-write
This register is used to control the minimum NRST active duration and LSI function.0 to 7 wait states are inserted for word, half-word and byte accesses. Wait states are inserted in case of successive accesses to this register.This register is reset by the por_rst reset, and it is located into the VDD domain. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSION : LSION
bits : 0 - 0 (1 bit)
access : read-write
LSIRDY : LSIRDY
bits : 1 - 1 (1 bit)
access : read-only
MRD : MRD
bits : 16 - 20 (5 bit)
access : read-write
EADLY : EADLY
bits : 24 - 26 (3 bit)
access : read-write
SPARE : SPARE
bits : 27 - 31 (5 bit)
access : read-write
This register is used to configure the HSI. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSIDIV : HSIDIV
bits : 0 - 1 (2 bit)
access : read-write
HSITRIM : HSITRIM
bits : 8 - 14 (7 bit)
access : read-write
HSICAL : HSICAL
bits : 16 - 27 (12 bit)
access : read-only
This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCRST : LTDCRST
bits : 0 - 0 (1 bit)
DSIRST : DSIRST
bits : 4 - 4 (1 bit)
DDRPERFMRST : DDRPERFMRST
bits : 8 - 8 (1 bit)
USBPHYRST : USBPHYRST
bits : 16 - 16 (1 bit)
This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral.
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCRST : LTDCRST
bits : 0 - 0 (1 bit)
DSIRST : DSIRST
bits : 4 - 4 (1 bit)
DDRPERFMRST : DDRPERFMRST
bits : 8 - 8 (1 bit)
USBPHYRST : USBPHYRST
bits : 16 - 16 (1 bit)
This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6RST : SPI6RST
bits : 0 - 0 (1 bit)
I2C4RST : I2C4RST
bits : 2 - 2 (1 bit)
I2C6RST : I2C6RST
bits : 3 - 3 (1 bit)
USART1RST : USART1RST
bits : 4 - 4 (1 bit)
STGENRST : STGENRST
bits : 20 - 20 (1 bit)
This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6RST : SPI6RST
bits : 0 - 0 (1 bit)
I2C4RST : I2C4RST
bits : 2 - 2 (1 bit)
I2C6RST : I2C6RST
bits : 3 - 3 (1 bit)
USART1RST : USART1RST
bits : 4 - 4 (1 bit)
STGENRST : STGENRST
bits : 20 - 20 (1 bit)
This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOZRST : GPIOZRST
bits : 0 - 0 (1 bit)
CRYP1RST : CRYP1RST
bits : 4 - 4 (1 bit)
HASH1RST : HASH1RST
bits : 5 - 5 (1 bit)
RNG1RST : RNG1RST
bits : 6 - 6 (1 bit)
AXIMCRST : AXIMCRST
bits : 16 - 16 (1 bit)
This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOZRST : GPIOZRST
bits : 0 - 0 (1 bit)
CRYP1RST : CRYP1RST
bits : 4 - 4 (1 bit)
HASH1RST : HASH1RST
bits : 5 - 5 (1 bit)
RNG1RST : RNG1RST
bits : 6 - 6 (1 bit)
AXIMCRST : AXIMCRST
bits : 16 - 16 (1 bit)
This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPURST : GPURST
bits : 5 - 5 (1 bit)
ETHMACRST : ETHMACRST
bits : 10 - 10 (1 bit)
FMCRST : FMCRST
bits : 12 - 12 (1 bit)
QSPIRST : QSPIRST
bits : 14 - 14 (1 bit)
SDMMC1RST : SDMMC1RST
bits : 16 - 16 (1 bit)
SDMMC2RST : SDMMC2RST
bits : 17 - 17 (1 bit)
CRC1RST : CRC1RST
bits : 20 - 20 (1 bit)
USBHRST : USBHRST
bits : 24 - 24 (1 bit)
This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral.
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETHMACRST : ETHMACRST
bits : 10 - 10 (1 bit)
FMCRST : FMCRST
bits : 12 - 12 (1 bit)
QSPIRST : QSPIRST
bits : 14 - 14 (1 bit)
SDMMC1RST : SDMMC1RST
bits : 16 - 16 (1 bit)
SDMMC2RST : SDMMC2RST
bits : 17 - 17 (1 bit)
CRC1RST : CRC1RST
bits : 20 - 20 (1 bit)
USBHRST : USBHRST
bits : 24 - 24 (1 bit)
This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMARST : MDMARST
bits : 0 - 0 (1 bit)
This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMARST : MDMARST
bits : 0 - 0 (1 bit)
This register is used to fine-tune the CSI frequency. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See The clock restore sequence description for details.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSITRIM : CSITRIM
bits : 8 - 12 (5 bit)
access : read-write
CSICAL : CSICAL
bits : 16 - 23 (8 bit)
access : read-only
This register is used to select the clock source for the MPU. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPUSRC : MPUSRC
bits : 0 - 1 (2 bit)
access : read-write
MPUSRCRDY : MPUSRCRDY
bits : 31 - 31 (1 bit)
access : read-only
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCEN : LTDCEN
bits : 0 - 0 (1 bit)
DSIEN : DSIEN
bits : 4 - 4 (1 bit)
DDRPERFMEN : DDRPERFMEN
bits : 8 - 8 (1 bit)
IWDG2APBEN : IWDG2APBEN
bits : 15 - 15 (1 bit)
USBPHYEN : USBPHYEN
bits : 16 - 16 (1 bit)
STGENROEN : STGENROEN
bits : 20 - 20 (1 bit)
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCEN : LTDCEN
bits : 0 - 0 (1 bit)
DSIEN : DSIEN
bits : 4 - 4 (1 bit)
DDRPERFMEN : DDRPERFMEN
bits : 8 - 8 (1 bit)
IWDG2APBEN : IWDG2APBEN
bits : 15 - 15 (1 bit)
USBPHYEN : USBPHYEN
bits : 16 - 16 (1 bit)
STGENROEN : STGENROEN
bits : 20 - 20 (1 bit)
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6EN : SPI6EN
bits : 0 - 0 (1 bit)
I2C4EN : I2C4EN
bits : 2 - 2 (1 bit)
I2C6EN : I2C6EN
bits : 3 - 3 (1 bit)
USART1EN : USART1EN
bits : 4 - 4 (1 bit)
RTCAPBEN : RTCAPBEN
bits : 8 - 8 (1 bit)
TZC1EN : TZC1EN
bits : 11 - 11 (1 bit)
TZC2EN : TZC2EN
bits : 12 - 12 (1 bit)
TZPCEN : TZPCEN
bits : 13 - 13 (1 bit)
IWDG1APBEN : IWDG1APBEN
bits : 15 - 15 (1 bit)
BSECEN : BSECEN
bits : 16 - 16 (1 bit)
STGENEN : STGENEN
bits : 20 - 20 (1 bit)
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6EN : SPI6EN
bits : 0 - 0 (1 bit)
I2C4EN : I2C4EN
bits : 2 - 2 (1 bit)
I2C6EN : I2C6EN
bits : 3 - 3 (1 bit)
USART1EN : USART1EN
bits : 4 - 4 (1 bit)
RTCAPBEN : RTCAPBEN
bits : 8 - 8 (1 bit)
TZC1EN : TZC1EN
bits : 11 - 11 (1 bit)
TZC2EN : TZC2EN
bits : 12 - 12 (1 bit)
TZPCEN : TZPCEN
bits : 13 - 13 (1 bit)
IWDG1APBEN : IWDG1APBEN
bits : 15 - 15 (1 bit)
BSECEN : BSECEN
bits : 16 - 16 (1 bit)
STGENEN : STGENEN
bits : 20 - 20 (1 bit)
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOZEN : GPIOZEN
bits : 0 - 0 (1 bit)
CRYP1EN : CRYP1EN
bits : 4 - 4 (1 bit)
HASH1EN : HASH1EN
bits : 5 - 5 (1 bit)
RNG1EN : RNG1EN
bits : 6 - 6 (1 bit)
BKPSRAMEN : BKPSRAMEN
bits : 8 - 8 (1 bit)
AXIMCEN : AXIMCEN
bits : 16 - 16 (1 bit)
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOZEN : GPIOZEN
bits : 0 - 0 (1 bit)
CRYP1EN : CRYP1EN
bits : 4 - 4 (1 bit)
HASH1EN : HASH1EN
bits : 5 - 5 (1 bit)
RNG1EN : RNG1EN
bits : 6 - 6 (1 bit)
BKPSRAMEN : BKPSRAMEN
bits : 8 - 8 (1 bit)
AXIMCEN : AXIMCEN
bits : 16 - 16 (1 bit)
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMAEN : MDMAEN
bits : 0 - 0 (1 bit)
GPUEN : GPUEN
bits : 5 - 5 (1 bit)
ETHCKEN : ETHCKEN
bits : 7 - 7 (1 bit)
ETHTXEN : ETHTXEN
bits : 8 - 8 (1 bit)
ETHRXEN : ETHRXEN
bits : 9 - 9 (1 bit)
ETHMACEN : ETHMACEN
bits : 10 - 10 (1 bit)
FMCEN : FMCEN
bits : 12 - 12 (1 bit)
QSPIEN : QSPIEN
bits : 14 - 14 (1 bit)
SDMMC1EN : SDMMC1EN
bits : 16 - 16 (1 bit)
SDMMC2EN : SDMMC2EN
bits : 17 - 17 (1 bit)
CRC1EN : CRC1EN
bits : 20 - 20 (1 bit)
USBHEN : USBHEN
bits : 24 - 24 (1 bit)
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMAEN : MDMAEN
bits : 0 - 0 (1 bit)
GPUEN : GPUEN
bits : 5 - 5 (1 bit)
ETHCKEN : ETHCKEN
bits : 7 - 7 (1 bit)
ETHTXEN : ETHTXEN
bits : 8 - 8 (1 bit)
ETHRXEN : ETHRXEN
bits : 9 - 9 (1 bit)
ETHMACEN : ETHMACEN
bits : 10 - 10 (1 bit)
FMCEN : FMCEN
bits : 12 - 12 (1 bit)
QSPIEN : QSPIEN
bits : 14 - 14 (1 bit)
SDMMC1EN : SDMMC1EN
bits : 16 - 16 (1 bit)
SDMMC2EN : SDMMC2EN
bits : 17 - 17 (1 bit)
CRC1EN : CRC1EN
bits : 20 - 20 (1 bit)
USBHEN : USBHEN
bits : 24 - 24 (1 bit)
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMAEN : MDMAEN
bits : 0 - 0 (1 bit)
This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMAEN : MDMAEN
bits : 0 - 0 (1 bit)
This register is used to select the clock source for the AXI sub-system. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AXISSRC : AXISSRC
bits : 0 - 2 (3 bit)
access : read-write
AXISSRCRDY : AXISSRCRDY
bits : 31 - 31 (1 bit)
access : read-only
This register is used to select the reference clock for PLL1 and PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL12SRC : PLL12SRC
bits : 0 - 1 (2 bit)
access : read-write
PLL12SRCRDY : PLL12SRCRDY
bits : 31 - 31 (1 bit)
access : read-only
This register is used to set the peripheral clock enable bit
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCEN : LTDCEN
bits : 0 - 0 (1 bit)
DSIEN : DSIEN
bits : 4 - 4 (1 bit)
DDRPERFMEN : DDRPERFMEN
bits : 8 - 8 (1 bit)
USBPHYEN : USBPHYEN
bits : 16 - 16 (1 bit)
STGENROEN : STGENROEN
bits : 20 - 20 (1 bit)
This register is used to clear the peripheral clock enable bit
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCEN : LTDCEN
bits : 0 - 0 (1 bit)
DSIEN : DSIEN
bits : 4 - 4 (1 bit)
DDRPERFMEN : DDRPERFMEN
bits : 8 - 8 (1 bit)
USBPHYEN : USBPHYEN
bits : 16 - 16 (1 bit)
STGENROEN : STGENROEN
bits : 20 - 20 (1 bit)
This register is used to set the peripheral clock enable bit
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6EN : SPI6EN
bits : 0 - 0 (1 bit)
I2C4EN : I2C4EN
bits : 2 - 2 (1 bit)
I2C6EN : I2C6EN
bits : 3 - 3 (1 bit)
USART1EN : USART1EN
bits : 4 - 4 (1 bit)
RTCAPBEN : RTCAPBEN
bits : 8 - 8 (1 bit)
TZC1EN : TZC1EN
bits : 11 - 11 (1 bit)
TZC2EN : TZC2EN
bits : 12 - 12 (1 bit)
TZPCEN : TZPCEN
bits : 13 - 13 (1 bit)
BSECEN : BSECEN
bits : 16 - 16 (1 bit)
STGENEN : STGENEN
bits : 20 - 20 (1 bit)
This register is used to clear the peripheral clock enable bit
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6EN : SPI6EN
bits : 0 - 0 (1 bit)
I2C4EN : I2C4EN
bits : 2 - 2 (1 bit)
I2C6EN : I2C6EN
bits : 3 - 3 (1 bit)
USART1EN : USART1EN
bits : 4 - 4 (1 bit)
RTCAPBEN : RTCAPBEN
bits : 8 - 8 (1 bit)
TZC1EN : TZC1EN
bits : 11 - 11 (1 bit)
TZC2EN : TZC2EN
bits : 12 - 12 (1 bit)
TZPCEN : TZPCEN
bits : 13 - 13 (1 bit)
BSECEN : BSECEN
bits : 16 - 16 (1 bit)
STGENEN : STGENEN
bits : 20 - 20 (1 bit)
This register is used to set the peripheral clock enable bit If TZEN = , this register can only be modified in secure mode.
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOZEN : GPIOZEN
bits : 0 - 0 (1 bit)
CRYP1EN : CRYP1EN
bits : 4 - 4 (1 bit)
HASH1EN : HASH1EN
bits : 5 - 5 (1 bit)
RNG1EN : RNG1EN
bits : 6 - 6 (1 bit)
BKPSRAMEN : BKPSRAMEN
bits : 8 - 8 (1 bit)
This register is used to clear the peripheral clock enable bit If TZEN = , this register can only be modified in secure mode.
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOZEN : GPIOZEN
bits : 0 - 0 (1 bit)
CRYP1EN : CRYP1EN
bits : 4 - 4 (1 bit)
HASH1EN : HASH1EN
bits : 5 - 5 (1 bit)
RNG1EN : RNG1EN
bits : 6 - 6 (1 bit)
BKPSRAMEN : BKPSRAMEN
bits : 8 - 8 (1 bit)
This register is used to set the peripheral clock enable bit
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMAEN : MDMAEN
bits : 0 - 0 (1 bit)
GPUEN : GPUEN
bits : 5 - 5 (1 bit)
ETHCKEN : ETHCKEN
bits : 7 - 7 (1 bit)
ETHTXEN : ETHTXEN
bits : 8 - 8 (1 bit)
ETHRXEN : ETHRXEN
bits : 9 - 9 (1 bit)
ETHMACEN : ETHMACEN
bits : 10 - 10 (1 bit)
FMCEN : FMCEN
bits : 12 - 12 (1 bit)
QSPIEN : QSPIEN
bits : 14 - 14 (1 bit)
SDMMC1EN : SDMMC1EN
bits : 16 - 16 (1 bit)
SDMMC2EN : SDMMC2EN
bits : 17 - 17 (1 bit)
CRC1EN : CRC1EN
bits : 20 - 20 (1 bit)
USBHEN : USBHEN
bits : 24 - 24 (1 bit)
This register is used to clear the peripheral clock enable bit
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMAEN : MDMAEN
bits : 0 - 0 (1 bit)
GPUEN : GPUEN
bits : 5 - 5 (1 bit)
ETHCKEN : ETHCKEN
bits : 7 - 7 (1 bit)
ETHTXEN : ETHTXEN
bits : 8 - 8 (1 bit)
ETHRXEN : ETHRXEN
bits : 9 - 9 (1 bit)
ETHMACEN : ETHMACEN
bits : 10 - 10 (1 bit)
FMCEN : FMCEN
bits : 12 - 12 (1 bit)
QSPIEN : QSPIEN
bits : 14 - 14 (1 bit)
SDMMC1EN : SDMMC1EN
bits : 16 - 16 (1 bit)
SDMMC2EN : SDMMC2EN
bits : 17 - 17 (1 bit)
CRC1EN : CRC1EN
bits : 20 - 20 (1 bit)
USBHEN : USBHEN
bits : 24 - 24 (1 bit)
This register is used to control the MPU clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPUDIV : MPUDIV
bits : 0 - 2 (3 bit)
access : read-write
MPUDIVRDY : MPUDIVRDY
bits : 31 - 31 (1 bit)
access : read-only
This register is used to control the AXI Matrix clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AXIDIV : AXIDIV
bits : 0 - 2 (3 bit)
access : read-write
AXIDIVRDY : AXIDIVRDY
bits : 31 - 31 (1 bit)
access : read-only
This register is used by the MCU in order to clear the PERxLPEN bits
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCLPEN : LTDCLPEN
bits : 0 - 0 (1 bit)
DSILPEN : DSILPEN
bits : 4 - 4 (1 bit)
DDRPERFMLPEN : DDRPERFMLPEN
bits : 8 - 8 (1 bit)
IWDG2APBLPEN : IWDG2APBLPEN
bits : 15 - 15 (1 bit)
USBPHYLPEN : USBPHYLPEN
bits : 16 - 16 (1 bit)
STGENROLPEN : STGENROLPEN
bits : 20 - 20 (1 bit)
STGENROSTPEN : STGENROSTPEN
bits : 21 - 21 (1 bit)
This register is used by the MCU
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCLPEN : LTDCLPEN
bits : 0 - 0 (1 bit)
DSILPEN : DSILPEN
bits : 4 - 4 (1 bit)
DDRPERFMLPEN : DDRPERFMLPEN
bits : 8 - 8 (1 bit)
IWDG2APBLPEN : IWDG2APBLPEN
bits : 15 - 15 (1 bit)
USBPHYLPEN : USBPHYLPEN
bits : 16 - 16 (1 bit)
STGENROLPEN : STGENROLPEN
bits : 20 - 20 (1 bit)
STGENROSTPEN : STGENROSTPEN
bits : 21 - 21 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6LPEN : SPI6LPEN
bits : 0 - 0 (1 bit)
I2C4LPEN : I2C4LPEN
bits : 2 - 2 (1 bit)
I2C6LPEN : I2C6LPEN
bits : 3 - 3 (1 bit)
USART1LPEN : USART1LPEN
bits : 4 - 4 (1 bit)
RTCAPBLPEN : RTCAPBLPEN
bits : 8 - 8 (1 bit)
TZC1LPEN : TZC1LPEN
bits : 11 - 11 (1 bit)
TZC2LPEN : TZC2LPEN
bits : 12 - 12 (1 bit)
TZPCLPEN : TZPCLPEN
bits : 13 - 13 (1 bit)
IWDG1APBLPEN : IWDG1APBLPEN
bits : 15 - 15 (1 bit)
BSECLPEN : BSECLPEN
bits : 16 - 16 (1 bit)
STGENLPEN : STGENLPEN
bits : 20 - 20 (1 bit)
STGENSTPEN : STGENSTPEN
bits : 21 - 21 (1 bit)
This register is used by the Mpu.
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6LPEN : SPI6LPEN
bits : 0 - 0 (1 bit)
I2C4LPEN : I2C4LPEN
bits : 2 - 2 (1 bit)
I2C6LPEN : I2C6LPEN
bits : 3 - 3 (1 bit)
USART1LPEN : USART1LPEN
bits : 4 - 4 (1 bit)
RTCAPBLPEN : RTCAPBLPEN
bits : 8 - 8 (1 bit)
TZC1LPEN : TZC1LPEN
bits : 11 - 11 (1 bit)
TZC2LPEN : TZC2LPEN
bits : 12 - 12 (1 bit)
TZPCLPEN : TZPCLPEN
bits : 13 - 13 (1 bit)
IWDG1APBLPEN : IWDG1APBLPEN
bits : 15 - 15 (1 bit)
BSECLPEN : BSECLPEN
bits : 16 - 16 (1 bit)
STGENLPEN : STGENLPEN
bits : 20 - 20 (1 bit)
STGENSTPEN : STGENSTPEN
bits : 21 - 21 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOZLPEN : GPIOZLPEN
bits : 0 - 0 (1 bit)
CRYP1LPEN : CRYP1LPEN
bits : 4 - 4 (1 bit)
HASH1LPEN : HASH1LPEN
bits : 5 - 5 (1 bit)
RNG1LPEN : RNG1LPEN
bits : 6 - 6 (1 bit)
BKPSRAMLPEN : BKPSRAMLPEN
bits : 8 - 8 (1 bit)
This register is used by the MCU
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOZLPEN : GPIOZLPEN
bits : 0 - 0 (1 bit)
CRYP1LPEN : CRYP1LPEN
bits : 4 - 4 (1 bit)
HASH1LPEN : HASH1LPEN
bits : 5 - 5 (1 bit)
RNG1LPEN : RNG1LPEN
bits : 6 - 6 (1 bit)
BKPSRAMLPEN : BKPSRAMLPEN
bits : 8 - 8 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bits
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMALPEN : MDMALPEN
bits : 0 - 0 (1 bit)
GPULPEN : GPULPEN
bits : 5 - 5 (1 bit)
ETHCKLPEN : ETHCKLPEN
bits : 7 - 7 (1 bit)
ETHTXLPEN : ETHTXLPEN
bits : 8 - 8 (1 bit)
ETHRXLPEN : ETHRXLPEN
bits : 9 - 9 (1 bit)
ETHMACLPEN : ETHMACLPEN
bits : 10 - 10 (1 bit)
ETHSTPEN : ETHSTPEN
bits : 11 - 11 (1 bit)
FMCLPEN : FMCLPEN
bits : 12 - 12 (1 bit)
QSPILPEN : QSPILPEN
bits : 14 - 14 (1 bit)
SDMMC1LPEN : SDMMC1LPEN
bits : 16 - 16 (1 bit)
SDMMC2LPEN : SDMMC2LPEN
bits : 17 - 17 (1 bit)
CRC1LPEN : CRC1LPEN
bits : 20 - 20 (1 bit)
USBHLPEN : USBHLPEN
bits : 24 - 24 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bits
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMALPEN : MDMALPEN
bits : 0 - 0 (1 bit)
GPULPEN : GPULPEN
bits : 5 - 5 (1 bit)
ETHCKLPEN : ETHCKLPEN
bits : 7 - 7 (1 bit)
ETHTXLPEN : ETHTXLPEN
bits : 8 - 8 (1 bit)
ETHRXLPEN : ETHRXLPEN
bits : 9 - 9 (1 bit)
ETHMACLPEN : ETHMACLPEN
bits : 10 - 10 (1 bit)
ETHSTPEN : ETHSTPEN
bits : 11 - 11 (1 bit)
FMCLPEN : FMCLPEN
bits : 12 - 12 (1 bit)
QSPILPEN : QSPILPEN
bits : 14 - 14 (1 bit)
SDMMC1LPEN : SDMMC1LPEN
bits : 16 - 16 (1 bit)
SDMMC2LPEN : SDMMC2LPEN
bits : 17 - 17 (1 bit)
CRC1LPEN : CRC1LPEN
bits : 20 - 20 (1 bit)
USBHLPEN : USBHLPEN
bits : 24 - 24 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMALPEN : MDMALPEN
bits : 0 - 0 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMALPEN : MDMALPEN
bits : 0 - 0 (1 bit)
This register is used by the MCU in order to set the PERxLPEN bit.
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCLPEN : LTDCLPEN
bits : 0 - 0 (1 bit)
DSILPEN : DSILPEN
bits : 4 - 4 (1 bit)
DDRPERFMLPEN : DDRPERFMLPEN
bits : 8 - 8 (1 bit)
USBPHYLPEN : USBPHYLPEN
bits : 16 - 16 (1 bit)
STGENROLPEN : STGENROLPEN
bits : 20 - 20 (1 bit)
STGENROSTPEN : STGENROSTPEN
bits : 21 - 21 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bit
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCLPEN : LTDCLPEN
bits : 0 - 0 (1 bit)
DSILPEN : DSILPEN
bits : 4 - 4 (1 bit)
DDRPERFMLPEN : DDRPERFMLPEN
bits : 8 - 8 (1 bit)
USBPHYLPEN : USBPHYLPEN
bits : 16 - 16 (1 bit)
STGENROLPEN : STGENROLPEN
bits : 20 - 20 (1 bit)
STGENROSTPEN : STGENROSTPEN
bits : 21 - 21 (1 bit)
This register is used by the MCU in order to set the PERxLPEN bit.
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6LPEN : SPI6LPEN
bits : 0 - 0 (1 bit)
I2C4LPEN : I2C4LPEN
bits : 2 - 2 (1 bit)
I2C6LPEN : I2C6LPEN
bits : 3 - 3 (1 bit)
USART1LPEN : USART1LPEN
bits : 4 - 4 (1 bit)
RTCAPBLPEN : RTCAPBLPEN
bits : 8 - 8 (1 bit)
TZC1LPEN : TZC1LPEN
bits : 11 - 11 (1 bit)
TZC2LPEN : TZC2LPEN
bits : 12 - 12 (1 bit)
TZPCLPEN : TZPCLPEN
bits : 13 - 13 (1 bit)
BSECLPEN : BSECLPEN
bits : 16 - 16 (1 bit)
STGENLPEN : STGENLPEN
bits : 20 - 20 (1 bit)
STGENSTPEN : STGENSTPEN
bits : 21 - 21 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bit
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6LPEN : SPI6LPEN
bits : 0 - 0 (1 bit)
I2C4LPEN : I2C4LPEN
bits : 2 - 2 (1 bit)
I2C6LPEN : I2C6LPEN
bits : 3 - 3 (1 bit)
USART1LPEN : USART1LPEN
bits : 4 - 4 (1 bit)
RTCAPBLPEN : RTCAPBLPEN
bits : 8 - 8 (1 bit)
TZC1LPEN : TZC1LPEN
bits : 11 - 11 (1 bit)
TZC2LPEN : TZC2LPEN
bits : 12 - 12 (1 bit)
TZPCLPEN : TZPCLPEN
bits : 13 - 13 (1 bit)
BSECLPEN : BSECLPEN
bits : 16 - 16 (1 bit)
STGENLPEN : STGENLPEN
bits : 20 - 20 (1 bit)
STGENSTPEN : STGENSTPEN
bits : 21 - 21 (1 bit)
This register is used by the MCU in order to set the PERxLPEN bit. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOZLPEN : GPIOZLPEN
bits : 0 - 0 (1 bit)
CRYP1LPEN : CRYP1LPEN
bits : 4 - 4 (1 bit)
HASH1LPEN : HASH1LPEN
bits : 5 - 5 (1 bit)
RNG1LPEN : RNG1LPEN
bits : 6 - 6 (1 bit)
BKPSRAMLPEN : BKPSRAMLPEN
bits : 8 - 8 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bit If TZEN = , this register can only be modified in secure mode.
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOZLPEN : GPIOZLPEN
bits : 0 - 0 (1 bit)
CRYP1LPEN : CRYP1LPEN
bits : 4 - 4 (1 bit)
HASH1LPEN : HASH1LPEN
bits : 5 - 5 (1 bit)
RNG1LPEN : RNG1LPEN
bits : 6 - 6 (1 bit)
BKPSRAMLPEN : BKPSRAMLPEN
bits : 8 - 8 (1 bit)
This register is used by the MCU in order to set the PERxLPEN bit.
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMALPEN : MDMALPEN
bits : 0 - 0 (1 bit)
GPULPEN : GPULPEN
bits : 5 - 5 (1 bit)
ETHCKLPEN : ETHCKLPEN
bits : 7 - 7 (1 bit)
ETHTXLPEN : ETHTXLPEN
bits : 8 - 8 (1 bit)
ETHRXLPEN : ETHRXLPEN
bits : 9 - 9 (1 bit)
ETHMACLPEN : ETHMACLPEN
bits : 10 - 10 (1 bit)
ETHSTPEN : ETHSTPEN
bits : 11 - 11 (1 bit)
FMCLPEN : FMCLPEN
bits : 12 - 12 (1 bit)
QSPILPEN : QSPILPEN
bits : 14 - 14 (1 bit)
SDMMC1LPEN : SDMMC1LPEN
bits : 16 - 16 (1 bit)
SDMMC2LPEN : SDMMC2LPEN
bits : 17 - 17 (1 bit)
CRC1LPEN : CRC1LPEN
bits : 20 - 20 (1 bit)
USBHLPEN : USBHLPEN
bits : 24 - 24 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bit
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDMALPEN : MDMALPEN
bits : 0 - 0 (1 bit)
GPULPEN : GPULPEN
bits : 5 - 5 (1 bit)
ETHCKLPEN : ETHCKLPEN
bits : 7 - 7 (1 bit)
ETHTXLPEN : ETHTXLPEN
bits : 8 - 8 (1 bit)
ETHRXLPEN : ETHRXLPEN
bits : 9 - 9 (1 bit)
ETHMACLPEN : ETHMACLPEN
bits : 10 - 10 (1 bit)
ETHSTPEN : ETHSTPEN
bits : 11 - 11 (1 bit)
FMCLPEN : FMCLPEN
bits : 12 - 12 (1 bit)
QSPILPEN : QSPILPEN
bits : 14 - 14 (1 bit)
SDMMC1LPEN : SDMMC1LPEN
bits : 16 - 16 (1 bit)
SDMMC2LPEN : SDMMC2LPEN
bits : 17 - 17 (1 bit)
CRC1LPEN : CRC1LPEN
bits : 20 - 20 (1 bit)
USBHLPEN : USBHLPEN
bits : 24 - 24 (1 bit)
This register is used to control the APB4 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APB4DIV : APB4DIV
bits : 0 - 2 (3 bit)
access : read-write
APB4DIVRDY : APB4DIVRDY
bits : 31 - 31 (1 bit)
access : read-only
This register is used to control the APB5 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APB5DIV : APB5DIV
bits : 0 - 2 (3 bit)
access : read-write
APB5DIVRDY : APB5DIVRDY
bits : 31 - 31 (1 bit)
access : read-only
This register is used by the BOOTROM to check the reset source. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . In order to identify the reset source, the MPU application must use RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). Refer to Section10.3.13: Reset source identification for details.This register except MPUP[1:0]RSTF flags is located into VDD domain, and is reset by por_rst reset. The MPUP[1:0]RSTF flags are located into VDDCORE and are reset by nreset. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORRSTF : PORRSTF
bits : 0 - 0 (1 bit)
BORRSTF : BORRSTF
bits : 1 - 1 (1 bit)
PADRSTF : PADRSTF
bits : 2 - 2 (1 bit)
HCSSRSTF : HCSSRSTF
bits : 3 - 3 (1 bit)
VCORERSTF : VCORERSTF
bits : 4 - 4 (1 bit)
MPSYSRSTF : MPSYSRSTF
bits : 6 - 6 (1 bit)
MCSYSRSTF : MCSYSRSTF
bits : 7 - 7 (1 bit)
IWDG1RSTF : IWDG1RSTF
bits : 8 - 8 (1 bit)
IWDG2RSTF : IWDG2RSTF
bits : 9 - 9 (1 bit)
MPUP0RSTF : MPUP0RSTF
bits : 13 - 13 (1 bit)
MPUP1RSTF : MPUP1RSTF
bits : 14 - 14 (1 bit)
This register is used by the MPU in order to generate either a MCU reset or a system reset or a reset of one of the two MPU processors. Writing has no effect, reading returns the effective values of the corresponding bits. Writing a activates the reset.
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSYSRST : MPSYSRST
bits : 0 - 0 (1 bit)
MCURST : MCURST
bits : 1 - 1 (1 bit)
MPUP0RST : MPUP0RST
bits : 4 - 4 (1 bit)
MPUP1RST : MPUP1RST
bits : 5 - 5 (1 bit)
This register is used by the MPU to check the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from Standby or CStandby.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to .Refer to Section10.3.13: Reset source identification for details.The register is located in VDDCORE.If TZEN = , this register can only be modified in secure mode.
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORRSTF : PORRSTF
bits : 0 - 0 (1 bit)
BORRSTF : BORRSTF
bits : 1 - 1 (1 bit)
PADRSTF : PADRSTF
bits : 2 - 2 (1 bit)
HCSSRSTF : HCSSRSTF
bits : 3 - 3 (1 bit)
VCORERSTF : VCORERSTF
bits : 4 - 4 (1 bit)
MPSYSRSTF : MPSYSRSTF
bits : 6 - 6 (1 bit)
MCSYSRSTF : MCSYSRSTF
bits : 7 - 7 (1 bit)
IWDG1RSTF : IWDG1RSTF
bits : 8 - 8 (1 bit)
IWDG2RSTF : IWDG2RSTF
bits : 9 - 9 (1 bit)
STDBYRSTF : STDBYRSTF
bits : 11 - 11 (1 bit)
CSTDBYRSTF : CSTDBYRSTF
bits : 12 - 12 (1 bit)
MPUP0RSTF : MPUP0RSTF
bits : 13 - 13 (1 bit)
MPUP1RSTF : MPUP1RSTF
bits : 14 - 14 (1 bit)
SPARE : SPARE
bits : 15 - 15 (1 bit)
This register is used by the BOOTROM in order to freeze the IWDGs clocks. After a system reset or Standby reset (nreset), or a CStandby reset (cstby_rst) the MPU is allowed to write it once.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FZ_IWDG1 : FZ_IWDG1
bits : 0 - 0 (1 bit)
FZ_IWDG2 : FZ_IWDG2
bits : 1 - 1 (1 bit)
This register is used by the BOOTROM in order to unfreeze the IWDGs clocks. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FZ_IWDG1 : FZ_IWDG1
bits : 0 - 0 (1 bit)
FZ_IWDG2 : FZ_IWDG2
bits : 1 - 1 (1 bit)
This register shall be used by the MPU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSIRDYIE : LSIRDYIE
bits : 0 - 0 (1 bit)
LSERDYIE : LSERDYIE
bits : 1 - 1 (1 bit)
HSIRDYIE : HSIRDYIE
bits : 2 - 2 (1 bit)
HSERDYIE : HSERDYIE
bits : 3 - 3 (1 bit)
CSIRDYIE : CSIRDYIE
bits : 4 - 4 (1 bit)
PLL1DYIE : PLL1DYIE
bits : 8 - 8 (1 bit)
PLL2DYIE : PLL2DYIE
bits : 9 - 9 (1 bit)
PLL3DYIE : PLL3DYIE
bits : 10 - 10 (1 bit)
PLL4DYIE : PLL4DYIE
bits : 11 - 11 (1 bit)
LSECSSIE : LSECSSIE
bits : 16 - 16 (1 bit)
WKUPIE : WKUPIE
bits : 20 - 20 (1 bit)
This register shall be used by the MPU in order to read and clear the interrupt flags.Writing has no effect, writing will clear the corresponding flag.Refer to Section10.5: RCC interrupts for more details. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSIRDYF : LSIRDYF
bits : 0 - 0 (1 bit)
LSERDYF : LSERDYF
bits : 1 - 1 (1 bit)
HSIRDYF : HSIRDYF
bits : 2 - 2 (1 bit)
HSERDYF : HSERDYF
bits : 3 - 3 (1 bit)
CSIRDYF : CSIRDYF
bits : 4 - 4 (1 bit)
PLL1DYF : PLL1DYF
bits : 8 - 8 (1 bit)
PLL2DYF : PLL2DYF
bits : 9 - 9 (1 bit)
PLL3DYF : PLL3DYF
bits : 10 - 10 (1 bit)
PLL4DYF : PLL4DYF
bits : 11 - 11 (1 bit)
LSECSSF : LSECSSF
bits : 16 - 16 (1 bit)
WKUPF : WKUPF
bits : 20 - 20 (1 bit)
This register is used to program the delay between the moment where the system exits from one of the Stop modes, and the moment where it is allowed to enable the PLLs and provide a clock to bridges and processors. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWRLP_DLY : PWRLP_DLY
bits : 0 - 21 (22 bit)
MCTMPSKP : MCTMPSKP
bits : 24 - 24 (1 bit)
This register is dedicated to the BOOTROM code in order to update the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from Standby or CStandby. The application software shall not use this register. In order to identify the reset source, the MPU application must use RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR).Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .Refer to Section10.3.13: Reset source identification for details.The register is located in VDDCORE.If TZEN = , this register can only be modified in secure mode.
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORRSTF : PORRSTF
bits : 0 - 0 (1 bit)
BORRSTF : BORRSTF
bits : 1 - 1 (1 bit)
PADRSTF : PADRSTF
bits : 2 - 2 (1 bit)
HCSSRSTF : HCSSRSTF
bits : 3 - 3 (1 bit)
VCORERSTF : VCORERSTF
bits : 4 - 4 (1 bit)
MPSYSRSTF : MPSYSRSTF
bits : 6 - 6 (1 bit)
MCSYSRSTF : MCSYSRSTF
bits : 7 - 7 (1 bit)
IWDG1RSTF : IWDG1RSTF
bits : 8 - 8 (1 bit)
IWDG2RSTF : IWDG2RSTF
bits : 9 - 9 (1 bit)
STDBYRSTF : STDBYRSTF
bits : 11 - 11 (1 bit)
CSTDBYRSTF : CSTDBYRSTF
bits : 12 - 12 (1 bit)
MPUP0RSTF : MPUP0RSTF
bits : 13 - 13 (1 bit)
MPUP1RSTF : MPUP1RSTF
bits : 14 - 14 (1 bit)
SPARE : SPARE
bits : 15 - 15 (1 bit)
This register is used to divide the HSE clock for RTC. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTCDIV : RTCDIV
bits : 0 - 5 (6 bit)
This register is used to select the clock source for the MCU sub-system, including the MCU itself. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCUSSRC : MCUSSRC
bits : 0 - 1 (2 bit)
access : read-write
MCUSSRCRDY : MCUSSRCRDY
bits : 31 - 31 (1 bit)
access : read-only
This register is used to control the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLON : PLLON
bits : 0 - 0 (1 bit)
access : read-write
PLL1RDY : PLL1RDY
bits : 1 - 1 (1 bit)
access : read-only
SSCG_CTRL : SSCG_CTRL
bits : 2 - 2 (1 bit)
access : read-write
DIVPEN : DIVPEN
bits : 4 - 4 (1 bit)
access : read-write
DIVQEN : DIVQEN
bits : 5 - 5 (1 bit)
access : read-write
DIVREN : DIVREN
bits : 6 - 6 (1 bit)
access : read-write
This register is used to select the clock generated on MCO1 output.
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCO1SEL : MCO1SEL
bits : 0 - 2 (3 bit)
MCO1DIV : MCO1DIV
bits : 4 - 7 (4 bit)
MCO1ON : MCO1ON
bits : 12 - 12 (1 bit)
This register is used to select the clock generated on MCO2 output.
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCO2SEL : MCO2SEL
bits : 0 - 2 (3 bit)
MCO2DIV : MCO2DIV
bits : 4 - 7 (4 bit)
MCO2ON : MCO2ON
bits : 12 - 12 (1 bit)
This is a read-only access register, It contains the status flags of oscillators. Writing has no effect.
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HSIRDY : HSIRDY
bits : 0 - 0 (1 bit)
HSIDIVRDY : HSIDIVRDY
bits : 2 - 2 (1 bit)
CSIRDY : CSIRDY
bits : 4 - 4 (1 bit)
HSERDY : HSERDY
bits : 8 - 8 (1 bit)
MPUCKRDY : MPUCKRDY
bits : 23 - 23 (1 bit)
AXICKRDY : AXICKRDY
bits : 24 - 24 (1 bit)
CKREST : CKREST
bits : 25 - 25 (1 bit)
This is register contains the enable control of the debug and trace function, and the clock divider for the trace function.
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRACEDIV : TRACEDIV
bits : 0 - 2 (3 bit)
DBGCKEN : DBGCKEN
bits : 8 - 8 (1 bit)
TRACECKEN : TRACECKEN
bits : 9 - 9 (1 bit)
DBGRST : DBGRST
bits : 12 - 12 (1 bit)
This register is used to select the reference clock for PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL3SRC : PLL3SRC
bits : 0 - 1 (2 bit)
access : read-write
PLL3SRCRDY : PLL3SRCRDY
bits : 31 - 31 (1 bit)
access : read-only
This register is used to select the reference clock for PLL4.
address_offset : 0x824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL4SRC : PLL4SRC
bits : 0 - 1 (2 bit)
access : read-write
PLL4SRCRDY : PLL4SRCRDY
bits : 31 - 31 (1 bit)
access : read-only
This register is used to control the prescaler value of timers located into APB1 domain. It concerns TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13 and TIM14. Refer to Section: Sub-system clock generation for additional information.
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMG1PRE : TIMG1PRE
bits : 0 - 0 (1 bit)
access : read-write
TIMG1PRERDY : TIMG1PRERDY
bits : 31 - 31 (1 bit)
access : read-only
This register is used to control the prescaler value of timers located into APB2 domain. It concerns TIM1, TIM8, TIM15, TIM16, and TIM17. Refer to Section: Sub-system clock generation for additional information.
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMG2PRE : TIMG2PRE
bits : 0 - 0 (1 bit)
access : read-write
TIMG2PRERDY : TIMG2PRERDY
bits : 31 - 31 (1 bit)
access : read-only
This register is used to control the MCU sub-system clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCUDIV : MCUDIV
bits : 0 - 3 (4 bit)
access : read-write
MCUDIVRDY : MCUDIVRDY
bits : 31 - 31 (1 bit)
access : read-only
This register is used to control the APB1 clock prescaler. Refer to section Section1.4.6.3: Sub-System Clock Generation for additional information.
address_offset : 0x834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APB1DIV : APB1DIV
bits : 0 - 2 (3 bit)
access : read-write
APB1DIVRDY : APB1DIVRDY
bits : 31 - 31 (1 bit)
access : read-only
This register is used to control the APB2 clock prescaler. Refer to Section: Sub-system clock generation for additional information.
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APB2DIV : APB2DIV
bits : 0 - 2 (3 bit)
access : read-write
APB2DIVRDY : APB2DIVRDY
bits : 31 - 31 (1 bit)
access : read-only
This register is used to control the APB3 clock prescaler. Refer to Section: Sub-system clock generation for additional information.
address_offset : 0x83C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APB3DIV : APB3DIV
bits : 0 - 2 (3 bit)
access : read-write
APB3DIVRDY : APB3DIVRDY
bits : 31 - 31 (1 bit)
access : read-only
This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVN : DIVN
bits : 0 - 8 (9 bit)
DIVM1 : DIVM1
bits : 16 - 21 (6 bit)
This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVP : DIVP
bits : 0 - 6 (7 bit)
DIVQ : DIVQ
bits : 8 - 14 (7 bit)
DIVR : DIVR
bits : 16 - 22 (7 bit)
This register is used to control the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
address_offset : 0x880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLON : PLLON
bits : 0 - 0 (1 bit)
access : read-write
PLL3RDY : PLL3RDY
bits : 1 - 1 (1 bit)
access : read-only
SSCG_CTRL : SSCG_CTRL
bits : 2 - 2 (1 bit)
access : read-write
DIVPEN : DIVPEN
bits : 4 - 4 (1 bit)
access : read-write
DIVQEN : DIVQEN
bits : 5 - 5 (1 bit)
access : read-write
DIVREN : DIVREN
bits : 6 - 6 (1 bit)
access : read-write
This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
address_offset : 0x884 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVN : DIVN
bits : 0 - 8 (9 bit)
DIVM3 : DIVM3
bits : 16 - 21 (6 bit)
IFRGE : IFRGE
bits : 24 - 25 (2 bit)
This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
address_offset : 0x888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVP : DIVP
bits : 0 - 6 (7 bit)
DIVQ : DIVQ
bits : 8 - 14 (7 bit)
DIVR : DIVR
bits : 16 - 22 (7 bit)
This register is used to fine-tune the frequency of the PLL3 VCO. If TZEN = MCKPROT = , this register can only be modified in secure mode.
address_offset : 0x88C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACV : FRACV
bits : 3 - 15 (13 bit)
FRACLE : FRACLE
bits : 16 - 16 (1 bit)
This register is used to configure the PLL3.It is not recommended to change the content of this register when the PLL3 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode.
address_offset : 0x890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD_PER : MOD_PER
bits : 0 - 12 (13 bit)
TPDFN_DIS : TPDFN_DIS
bits : 13 - 13 (1 bit)
RPDFN_DIS : RPDFN_DIS
bits : 14 - 14 (1 bit)
SSCG_MODE : SSCG_MODE
bits : 15 - 15 (1 bit)
INC_STEP : INC_STEP
bits : 16 - 30 (15 bit)
This register is used to control the PLL4.
address_offset : 0x894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLON : PLLON
bits : 0 - 0 (1 bit)
access : read-write
PLL4RDY : PLL4RDY
bits : 1 - 1 (1 bit)
access : read-only
SSCG_CTRL : SSCG_CTRL
bits : 2 - 2 (1 bit)
access : read-write
DIVPEN : DIVPEN
bits : 4 - 4 (1 bit)
access : read-write
DIVQEN : DIVQEN
bits : 5 - 5 (1 bit)
access : read-write
DIVREN : DIVREN
bits : 6 - 6 (1 bit)
access : read-write
This register is used to configure the PLL4.
address_offset : 0x898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVN : DIVN
bits : 0 - 8 (9 bit)
DIVM4 : DIVM4
bits : 16 - 21 (6 bit)
IFRGE : IFRGE
bits : 24 - 25 (2 bit)
This register is used to configure the PLL4.
address_offset : 0x89C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVP : DIVP
bits : 0 - 6 (7 bit)
DIVQ : DIVQ
bits : 8 - 14 (7 bit)
DIVR : DIVR
bits : 16 - 22 (7 bit)
This register is used to fine-tune the frequency of the PLL4 VCO.
address_offset : 0x8A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACV : FRACV
bits : 3 - 15 (13 bit)
FRACLE : FRACLE
bits : 16 - 16 (1 bit)
This register is used to configure the PLL4.It is not recommended to change the content of this register when the PLL4 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode.
address_offset : 0x8A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD_PER : MOD_PER
bits : 0 - 12 (13 bit)
TPDFN_DIS : TPDFN_DIS
bits : 13 - 13 (1 bit)
RPDFN_DIS : RPDFN_DIS
bits : 14 - 14 (1 bit)
SSCG_MODE : SSCG_MODE
bits : 15 - 15 (1 bit)
INC_STEP : INC_STEP
bits : 16 - 30 (15 bit)
This register is used to fine-tune the frequency of the PLL1 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACV : FRACV
bits : 3 - 15 (13 bit)
FRACLE : FRACLE
bits : 16 - 16 (1 bit)
This register is used to control the selection of the kernel clock for the I2C1 and I2C2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C12SRC : I2C12SRC
bits : 0 - 2 (3 bit)
This register is used to control the selection of the kernel clock for the I2C3 and I2C5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
address_offset : 0x8C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C35SRC : I2C35SRC
bits : 0 - 2 (3 bit)
This register is used to control the selection of the kernel clock for the SAI1 and DFSDM audio clock. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
address_offset : 0x8C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAI1SRC : SAI1SRC
bits : 0 - 2 (3 bit)
This register is used to control the selection of the kernel clock for the SAI2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
address_offset : 0x8CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAI2SRC : SAI2SRC
bits : 0 - 2 (3 bit)
This register is used to control the selection of the kernel clock for the SAI3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
address_offset : 0x8D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAI3SRC : SAI3SRC
bits : 0 - 2 (3 bit)
This register is used to control the selection of the kernel clock for the SAI4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
address_offset : 0x8D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAI4SRC : SAI4SRC
bits : 0 - 2 (3 bit)
This register is used to control the selection of the kernel clock for the SPI/I2S1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
address_offset : 0x8D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI1SRC : SPI1SRC
bits : 0 - 2 (3 bit)
This register is used to control the selection of the kernel clock for the SPI/I2S2,3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
address_offset : 0x8DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI23SRC : SPI23SRC
bits : 0 - 2 (3 bit)
This register is used to control the selection of the kernel clock for the SPI4,5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
address_offset : 0x8E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI45SRC : SPI45SRC
bits : 0 - 2 (3 bit)
This register is used to control the selection of the kernel clock for the USART6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
address_offset : 0x8E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART6SRC : UART6SRC
bits : 0 - 2 (3 bit)
This register is used to control the selection of the kernel clock for the USART2 and UART4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
address_offset : 0x8E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART24SRC : UART24SRC
bits : 0 - 2 (3 bit)
This register is used to control the selection of the kernel clock for the USART3 and UART5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
address_offset : 0x8EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART35SRC : UART35SRC
bits : 0 - 2 (3 bit)
This register is used to control the selection of the kernel clock for the UART7 and UART8. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
address_offset : 0x8F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART78SRC : UART78SRC
bits : 0 - 2 (3 bit)
This register is used to control the selection of the kernel clock for the SDMMC1 and SDMMC2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
address_offset : 0x8F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDMMC12SRC : SDMMC12SRC
bits : 0 - 2 (3 bit)
This register is used to control the selection of the kernel clock for the SDMMC3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
address_offset : 0x8F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDMMC3SRC : SDMMC3SRC
bits : 0 - 2 (3 bit)
This register is used to control the selection of the kernel clock for the ETH block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
address_offset : 0x8FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETHSRC : ETHSRC
bits : 0 - 1 (2 bit)
ETHPTPDIV : ETHPTPDIV
bits : 4 - 7 (4 bit)
This register is used to configure the PLL1.It is not recommended to change the content of this register when the PLL1 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD_PER : MOD_PER
bits : 0 - 12 (13 bit)
TPDFN_DIS : TPDFN_DIS
bits : 13 - 13 (1 bit)
RPDFN_DIS : RPDFN_DIS
bits : 14 - 14 (1 bit)
SSCG_MODE : SSCG_MODE
bits : 15 - 15 (1 bit)
INC_STEP : INC_STEP
bits : 16 - 30 (15 bit)
This register is used to control the selection of the kernel clock for the QUADSPI. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QSPISRC : QSPISRC
bits : 0 - 1 (2 bit)
This register is used to control the selection of the kernel clock for the FMC block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FMCSRC : FMCSRC
bits : 0 - 1 (2 bit)
This register is used to control the selection of the kernel clock for the FDCAN block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
address_offset : 0x90C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FDCANSRC : FDCANSRC
bits : 0 - 1 (2 bit)
This register is used to control the selection of the kernel clock for the SPDIFRX. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
address_offset : 0x914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPDIFSRC : SPDIFSRC
bits : 0 - 1 (2 bit)
This register is used to control the selection of the kernel clock for the CEC-HDMI.
address_offset : 0x918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CECSRC : CECSRC
bits : 0 - 1 (2 bit)
This register is used to control the selection of the kernel clock for the USBPHY PLL of the USB HOST and USB OTG
address_offset : 0x91C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBPHYSRC : USBPHYSRC
bits : 0 - 1 (2 bit)
USBOSRC : USBOSRC
bits : 4 - 4 (1 bit)
This register is used to control the selection of the kernel clock for the RNG2.
address_offset : 0x920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RNG2SRC : RNG2SRC
bits : 0 - 1 (2 bit)
This register is used to control the selection of the kernel clock for the DSI block.
address_offset : 0x924 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSISRC : DSISRC
bits : 0 - 0 (1 bit)
This register is used to control the selection of the kernel clock for the ADC block.
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCSRC : ADCSRC
bits : 0 - 1 (2 bit)
This register is used to control the selection of the kernel clock for the LPTIM4 and LPTIM5 blocks.
address_offset : 0x92C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM45SRC : LPTIM45SRC
bits : 0 - 2 (3 bit)
This register is used to control the selection of the kernel clock for the LPTIM2 and LPTIM3 blocks.
address_offset : 0x930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM23SRC : LPTIM23SRC
bits : 0 - 2 (3 bit)
This register is used to control the selection of the kernel clock for the LPTIM1 block.
address_offset : 0x934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM1SRC : LPTIM1SRC
bits : 0 - 2 (3 bit)
This register is used to control the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLON : PLLON
bits : 0 - 0 (1 bit)
access : read-write
PLL2RDY : PLL2RDY
bits : 1 - 1 (1 bit)
access : read-only
SSCG_CTRL : SSCG_CTRL
bits : 2 - 2 (1 bit)
access : read-write
DIVPEN : DIVPEN
bits : 4 - 4 (1 bit)
access : read-write
DIVQEN : DIVQEN
bits : 5 - 5 (1 bit)
access : read-write
DIVREN : DIVREN
bits : 6 - 6 (1 bit)
access : read-write
This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVN : DIVN
bits : 0 - 8 (9 bit)
DIVM2 : DIVM2
bits : 16 - 21 (6 bit)
This register is used to activate the reset of the corresponding peripheral.
address_offset : 0x980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2RST : TIM2RST
bits : 0 - 0 (1 bit)
TIM3RST : TIM3RST
bits : 1 - 1 (1 bit)
TIM4RST : TIM4RST
bits : 2 - 2 (1 bit)
TIM5RST : TIM5RST
bits : 3 - 3 (1 bit)
TIM6RST : TIM6RST
bits : 4 - 4 (1 bit)
TIM7RST : TIM7RST
bits : 5 - 5 (1 bit)
TIM12RST : TIM12RST
bits : 6 - 6 (1 bit)
TIM13RST : TIM13RST
bits : 7 - 7 (1 bit)
TIM14RST : TIM14RST
bits : 8 - 8 (1 bit)
LPTIM1RST : LPTIM1RST
bits : 9 - 9 (1 bit)
SPI2RST : SPI2RST
bits : 11 - 11 (1 bit)
SPI3RST : SPI3RST
bits : 12 - 12 (1 bit)
USART2RST : USART2RST
bits : 14 - 14 (1 bit)
USART3RST : USART3RST
bits : 15 - 15 (1 bit)
UART4RST : UART4RST
bits : 16 - 16 (1 bit)
UART5RST : UART5RST
bits : 17 - 17 (1 bit)
UART7RST : UART7RST
bits : 18 - 18 (1 bit)
UART8RST : UART8RST
bits : 19 - 19 (1 bit)
I2C1RST : I2C1RST
bits : 21 - 21 (1 bit)
I2C2RST : I2C2RST
bits : 22 - 22 (1 bit)
I2C3RST : I2C3RST
bits : 23 - 23 (1 bit)
I2C5RST : I2C5RST
bits : 24 - 24 (1 bit)
SPDIFRST : SPDIFRST
bits : 26 - 26 (1 bit)
CECRST : CECRST
bits : 27 - 27 (1 bit)
DAC12RST : DAC12RST
bits : 29 - 29 (1 bit)
MDIOSRST : MDIOSRST
bits : 31 - 31 (1 bit)
This register is used to release the reset of the corresponding peripheral.
address_offset : 0x984 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2RST : TIM2RST
bits : 0 - 0 (1 bit)
TIM3RST : TIM3RST
bits : 1 - 1 (1 bit)
TIM4RST : TIM4RST
bits : 2 - 2 (1 bit)
TIM5RST : TIM5RST
bits : 3 - 3 (1 bit)
TIM6RST : TIM6RST
bits : 4 - 4 (1 bit)
TIM7RST : TIM7RST
bits : 5 - 5 (1 bit)
TIM12RST : TIM12RST
bits : 6 - 6 (1 bit)
TIM13RST : TIM13RST
bits : 7 - 7 (1 bit)
TIM14RST : TIM14RST
bits : 8 - 8 (1 bit)
LPTIM1RST : LPTIM1RST
bits : 9 - 9 (1 bit)
SPI2RST : SPI2RST
bits : 11 - 11 (1 bit)
SPI3RST : SPI3RST
bits : 12 - 12 (1 bit)
USART2RST : USART2RST
bits : 14 - 14 (1 bit)
USART3RST : USART3RST
bits : 15 - 15 (1 bit)
UART4RST : UART4RST
bits : 16 - 16 (1 bit)
UART5RST : UART5RST
bits : 17 - 17 (1 bit)
UART7RST : UART7RST
bits : 18 - 18 (1 bit)
UART8RST : UART8RST
bits : 19 - 19 (1 bit)
I2C1RST : I2C1RST
bits : 21 - 21 (1 bit)
I2C2RST : I2C2RST
bits : 22 - 22 (1 bit)
I2C3RST : I2C3RST
bits : 23 - 23 (1 bit)
I2C5RST : I2C5RST
bits : 24 - 24 (1 bit)
SPDIFRST : SPDIFRST
bits : 26 - 26 (1 bit)
CECRST : CECRST
bits : 27 - 27 (1 bit)
DAC12RST : DAC12RST
bits : 29 - 29 (1 bit)
MDIOSRST : MDIOSRST
bits : 31 - 31 (1 bit)
This register is used to activate the reset of the corresponding peripheral.
address_offset : 0x988 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1RST : TIM1RST
bits : 0 - 0 (1 bit)
TIM8RST : TIM8RST
bits : 1 - 1 (1 bit)
TIM15RST : TIM15RST
bits : 2 - 2 (1 bit)
TIM16RST : TIM16RST
bits : 3 - 3 (1 bit)
TIM17RST : TIM17RST
bits : 4 - 4 (1 bit)
SPI1RST : SPI1RST
bits : 8 - 8 (1 bit)
SPI4RST : SPI4RST
bits : 9 - 9 (1 bit)
SPI5RST : SPI5RST
bits : 10 - 10 (1 bit)
USART6RST : USART6RST
bits : 13 - 13 (1 bit)
SAI1RST : SAI1RST
bits : 16 - 16 (1 bit)
SAI2RST : SAI2RST
bits : 17 - 17 (1 bit)
SAI3RST : SAI3RST
bits : 18 - 18 (1 bit)
DFSDMRST : DFSDMRST
bits : 20 - 20 (1 bit)
FDCANRST : FDCANRST
bits : 24 - 24 (1 bit)
This register is used to release the reset of the corresponding peripheral.
address_offset : 0x98C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1RST : TIM1RST
bits : 0 - 0 (1 bit)
TIM8RST : TIM8RST
bits : 1 - 1 (1 bit)
TIM15RST : TIM15RST
bits : 2 - 2 (1 bit)
TIM16RST : TIM16RST
bits : 3 - 3 (1 bit)
TIM17RST : TIM17RST
bits : 4 - 4 (1 bit)
SPI1RST : SPI1RST
bits : 8 - 8 (1 bit)
SPI4RST : SPI4RST
bits : 9 - 9 (1 bit)
SPI5RST : SPI5RST
bits : 10 - 10 (1 bit)
USART6RST : USART6RST
bits : 13 - 13 (1 bit)
SAI1RST : SAI1RST
bits : 16 - 16 (1 bit)
SAI2RST : SAI2RST
bits : 17 - 17 (1 bit)
SAI3RST : SAI3RST
bits : 18 - 18 (1 bit)
DFSDMRST : DFSDMRST
bits : 20 - 20 (1 bit)
FDCANRST : FDCANRST
bits : 24 - 24 (1 bit)
This register is used to activate the reset of the corresponding peripheral.
address_offset : 0x990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM2RST : LPTIM2RST
bits : 0 - 0 (1 bit)
LPTIM3RST : LPTIM3RST
bits : 1 - 1 (1 bit)
LPTIM4RST : LPTIM4RST
bits : 2 - 2 (1 bit)
LPTIM5RST : LPTIM5RST
bits : 3 - 3 (1 bit)
SAI4RST : SAI4RST
bits : 8 - 8 (1 bit)
SYSCFGRST : SYSCFGRST
bits : 11 - 11 (1 bit)
VREFRST : VREFRST
bits : 13 - 13 (1 bit)
DTSRST : DTSRST
bits : 16 - 16 (1 bit)
This register is used to release the reset of the corresponding peripheral.
address_offset : 0x994 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM2RST : LPTIM2RST
bits : 0 - 0 (1 bit)
LPTIM3RST : LPTIM3RST
bits : 1 - 1 (1 bit)
LPTIM4RST : LPTIM4RST
bits : 2 - 2 (1 bit)
LPTIM5RST : LPTIM5RST
bits : 3 - 3 (1 bit)
SAI4RST : SAI4RST
bits : 8 - 8 (1 bit)
SYSCFGRST : SYSCFGRST
bits : 11 - 11 (1 bit)
VREFRST : VREFRST
bits : 13 - 13 (1 bit)
DTSRST : DTSRST
bits : 16 - 16 (1 bit)
This register is used to activate the reset of the corresponding peripheral.
address_offset : 0x998 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1RST : DMA1RST
bits : 0 - 0 (1 bit)
DMA2RST : DMA2RST
bits : 1 - 1 (1 bit)
DMAMUXRST : DMAMUXRST
bits : 2 - 2 (1 bit)
ADC12RST : ADC12RST
bits : 5 - 5 (1 bit)
USBORST : USBORST
bits : 8 - 8 (1 bit)
SDMMC3RST : SDMMC3RST
bits : 16 - 16 (1 bit)
This register is used to release the reset of the corresponding peripheral.
address_offset : 0x99C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1RST : DMA1RST
bits : 0 - 0 (1 bit)
DMA2RST : DMA2RST
bits : 1 - 1 (1 bit)
DMAMUXRST : DMAMUXRST
bits : 2 - 2 (1 bit)
ADC12RST : ADC12RST
bits : 5 - 5 (1 bit)
USBORST : USBORST
bits : 8 - 8 (1 bit)
SDMMC3RST : SDMMC3RST
bits : 16 - 16 (1 bit)
This register is used to activate the reset of the corresponding peripheral.
address_offset : 0x9A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMIRST : DCMIRST
bits : 0 - 0 (1 bit)
CRYP2RST : CRYP2RST
bits : 4 - 4 (1 bit)
HASH2RST : HASH2RST
bits : 5 - 5 (1 bit)
RNG2RST : RNG2RST
bits : 6 - 6 (1 bit)
CRC2RST : CRC2RST
bits : 7 - 7 (1 bit)
HSEMRST : HSEMRST
bits : 11 - 11 (1 bit)
IPCCRST : IPCCRST
bits : 12 - 12 (1 bit)
This register is used to release the reset of the corresponding peripheral.
address_offset : 0x9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMIRST : DCMIRST
bits : 0 - 0 (1 bit)
CRYP2RST : CRYP2RST
bits : 4 - 4 (1 bit)
HASH2RST : HASH2RST
bits : 5 - 5 (1 bit)
RNG2RST : RNG2RST
bits : 6 - 6 (1 bit)
CRC2RST : CRC2RST
bits : 7 - 7 (1 bit)
HSEMRST : HSEMRST
bits : 11 - 11 (1 bit)
IPCCRST : IPCCRST
bits : 12 - 12 (1 bit)
This register is used to activate the reset of the corresponding peripheral
address_offset : 0x9A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOARST : GPIOARST
bits : 0 - 0 (1 bit)
GPIOBRST : GPIOBRST
bits : 1 - 1 (1 bit)
GPIOCRST : GPIOCRST
bits : 2 - 2 (1 bit)
GPIODRST : GPIODRST
bits : 3 - 3 (1 bit)
GPIOERST : GPIOERST
bits : 4 - 4 (1 bit)
GPIOFRST : GPIOFRST
bits : 5 - 5 (1 bit)
GPIOGRST : GPIOGRST
bits : 6 - 6 (1 bit)
GPIOHRST : GPIOHRST
bits : 7 - 7 (1 bit)
GPIOIRST : GPIOIRST
bits : 8 - 8 (1 bit)
GPIOJRST : GPIOJRST
bits : 9 - 9 (1 bit)
GPIOKRST : GPIOKRST
bits : 10 - 10 (1 bit)
This register is used to release the reset of the corresponding peripheral.
address_offset : 0x9AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOARST : GPIOARST
bits : 0 - 0 (1 bit)
GPIOBRST : GPIOBRST
bits : 1 - 1 (1 bit)
GPIOCRST : GPIOCRST
bits : 2 - 2 (1 bit)
GPIODRST : GPIODRST
bits : 3 - 3 (1 bit)
GPIOERST : GPIOERST
bits : 4 - 4 (1 bit)
GPIOFRST : GPIOFRST
bits : 5 - 5 (1 bit)
GPIOGRST : GPIOGRST
bits : 6 - 6 (1 bit)
GPIOHRST : GPIOHRST
bits : 7 - 7 (1 bit)
GPIOIRST : GPIOIRST
bits : 8 - 8 (1 bit)
GPIOJRST : GPIOJRST
bits : 9 - 9 (1 bit)
GPIOKRST : GPIOKRST
bits : 10 - 10 (1 bit)
This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVP : DIVP
bits : 0 - 6 (7 bit)
DIVQ : DIVQ
bits : 8 - 14 (7 bit)
DIVR : DIVR
bits : 16 - 22 (7 bit)
This register is used to fine-tune the frequency of the PLL2 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACV : FRACV
bits : 3 - 15 (13 bit)
FRACLE : FRACLE
bits : 16 - 16 (1 bit)
This register is used to set the peripheral clock enable bit
address_offset : 0xA00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2EN : TIM2EN
bits : 0 - 0 (1 bit)
TIM3EN : TIM3EN
bits : 1 - 1 (1 bit)
TIM4EN : TIM4EN
bits : 2 - 2 (1 bit)
TIM5EN : TIM5EN
bits : 3 - 3 (1 bit)
TIM6EN : TIM6EN
bits : 4 - 4 (1 bit)
TIM7EN : TIM7EN
bits : 5 - 5 (1 bit)
TIM12EN : TIM12EN
bits : 6 - 6 (1 bit)
TIM13EN : TIM13EN
bits : 7 - 7 (1 bit)
TIM14EN : TIM14EN
bits : 8 - 8 (1 bit)
LPTIM1EN : LPTIM1EN
bits : 9 - 9 (1 bit)
SPI2EN : SPI2EN
bits : 11 - 11 (1 bit)
SPI3EN : SPI3EN
bits : 12 - 12 (1 bit)
USART2EN : USART2EN
bits : 14 - 14 (1 bit)
USART3EN : USART3EN
bits : 15 - 15 (1 bit)
UART4EN : UART4EN
bits : 16 - 16 (1 bit)
UART5EN : UART5EN
bits : 17 - 17 (1 bit)
UART7EN : UART7EN
bits : 18 - 18 (1 bit)
UART8EN : UART8EN
bits : 19 - 19 (1 bit)
I2C1EN : I2C1EN
bits : 21 - 21 (1 bit)
I2C2EN : I2C2EN
bits : 22 - 22 (1 bit)
I2C3EN : I2C3EN
bits : 23 - 23 (1 bit)
I2C5EN : I2C5EN
bits : 24 - 24 (1 bit)
SPDIFEN : SPDIFEN
bits : 26 - 26 (1 bit)
CECEN : CECEN
bits : 27 - 27 (1 bit)
DAC12EN : DAC12EN
bits : 29 - 29 (1 bit)
MDIOSEN : MDIOSEN
bits : 31 - 31 (1 bit)
This register is used to clear the peripheral clock enable bit
address_offset : 0xA04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2EN : TIM2EN
bits : 0 - 0 (1 bit)
TIM3EN : TIM3EN
bits : 1 - 1 (1 bit)
TIM4EN : TIM4EN
bits : 2 - 2 (1 bit)
TIM5EN : TIM5EN
bits : 3 - 3 (1 bit)
TIM6EN : TIM6EN
bits : 4 - 4 (1 bit)
TIM7EN : TIM7EN
bits : 5 - 5 (1 bit)
TIM12EN : TIM12EN
bits : 6 - 6 (1 bit)
TIM13EN : TIM13EN
bits : 7 - 7 (1 bit)
TIM14EN : TIM14EN
bits : 8 - 8 (1 bit)
LPTIM1EN : LPTIM1EN
bits : 9 - 9 (1 bit)
SPI2EN : SPI2EN
bits : 11 - 11 (1 bit)
SPI3EN : SPI3EN
bits : 12 - 12 (1 bit)
USART2EN : USART2EN
bits : 14 - 14 (1 bit)
USART3EN : USART3EN
bits : 15 - 15 (1 bit)
UART4EN : UART4EN
bits : 16 - 16 (1 bit)
UART5EN : UART5EN
bits : 17 - 17 (1 bit)
UART7EN : UART7EN
bits : 18 - 18 (1 bit)
UART8EN : UART8EN
bits : 19 - 19 (1 bit)
I2C1EN : I2C1EN
bits : 21 - 21 (1 bit)
I2C2EN : I2C2EN
bits : 22 - 22 (1 bit)
I2C3EN : I2C3EN
bits : 23 - 23 (1 bit)
I2C5EN : I2C5EN
bits : 24 - 24 (1 bit)
SPDIFEN : SPDIFEN
bits : 26 - 26 (1 bit)
CECEN : CECEN
bits : 27 - 27 (1 bit)
DAC12EN : DAC12EN
bits : 29 - 29 (1 bit)
MDIOSEN : MDIOSEN
bits : 31 - 31 (1 bit)
This register is used to set the peripheral clock enable bit
address_offset : 0xA08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1EN : TIM1EN
bits : 0 - 0 (1 bit)
TIM8EN : TIM8EN
bits : 1 - 1 (1 bit)
TIM15EN : TIM15EN
bits : 2 - 2 (1 bit)
TIM16EN : TIM16EN
bits : 3 - 3 (1 bit)
TIM17EN : TIM17EN
bits : 4 - 4 (1 bit)
SPI1EN : SPI1EN
bits : 8 - 8 (1 bit)
SPI4EN : SPI4EN
bits : 9 - 9 (1 bit)
SPI5EN : SPI5EN
bits : 10 - 10 (1 bit)
USART6EN : USART6EN
bits : 13 - 13 (1 bit)
SAI1EN : SAI1EN
bits : 16 - 16 (1 bit)
SAI2EN : SAI2EN
bits : 17 - 17 (1 bit)
SAI3EN : SAI3EN
bits : 18 - 18 (1 bit)
DFSDMEN : DFSDMEN
bits : 20 - 20 (1 bit)
ADFSDMEN : ADFSDMEN
bits : 21 - 21 (1 bit)
FDCANEN : FDCANEN
bits : 24 - 24 (1 bit)
This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
address_offset : 0xA0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1EN : TIM1EN
bits : 0 - 0 (1 bit)
TIM8EN : TIM8EN
bits : 1 - 1 (1 bit)
TIM15EN : TIM15EN
bits : 2 - 2 (1 bit)
TIM16EN : TIM16EN
bits : 3 - 3 (1 bit)
TIM17EN : TIM17EN
bits : 4 - 4 (1 bit)
SPI1EN : SPI1EN
bits : 8 - 8 (1 bit)
SPI4EN : SPI4EN
bits : 9 - 9 (1 bit)
SPI5EN : SPI5EN
bits : 10 - 10 (1 bit)
USART6EN : USART6EN
bits : 13 - 13 (1 bit)
SAI1EN : SAI1EN
bits : 16 - 16 (1 bit)
SAI2EN : SAI2EN
bits : 17 - 17 (1 bit)
SAI3EN : SAI3EN
bits : 18 - 18 (1 bit)
DFSDMEN : DFSDMEN
bits : 20 - 20 (1 bit)
ADFSDMEN : ADFSDMEN
bits : 21 - 21 (1 bit)
FDCANEN : FDCANEN
bits : 24 - 24 (1 bit)
This register is used to set the peripheral clock enable bit
address_offset : 0xA10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM2EN : LPTIM2EN
bits : 0 - 0 (1 bit)
LPTIM3EN : LPTIM3EN
bits : 1 - 1 (1 bit)
LPTIM4EN : LPTIM4EN
bits : 2 - 2 (1 bit)
LPTIM5EN : LPTIM5EN
bits : 3 - 3 (1 bit)
SAI4EN : SAI4EN
bits : 8 - 8 (1 bit)
SYSCFGEN : SYSCFGEN
bits : 11 - 11 (1 bit)
VREFEN : VREFEN
bits : 13 - 13 (1 bit)
DTSEN : DTSEN
bits : 16 - 16 (1 bit)
HDPEN : HDPEN
bits : 20 - 20 (1 bit)
This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
address_offset : 0xA14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM2EN : LPTIM2EN
bits : 0 - 0 (1 bit)
LPTIM3EN : LPTIM3EN
bits : 1 - 1 (1 bit)
LPTIM4EN : LPTIM4EN
bits : 2 - 2 (1 bit)
LPTIM5EN : LPTIM5EN
bits : 3 - 3 (1 bit)
SAI4EN : SAI4EN
bits : 8 - 8 (1 bit)
SYSCFGEN : SYSCFGEN
bits : 11 - 11 (1 bit)
VREFEN : VREFEN
bits : 13 - 13 (1 bit)
DTSEN : DTSEN
bits : 16 - 16 (1 bit)
HDPEN : HDPEN
bits : 20 - 20 (1 bit)
This register is used to set the peripheral clock enable bit of the corresponding peripheral
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1EN : DMA1EN
bits : 0 - 0 (1 bit)
DMA2EN : DMA2EN
bits : 1 - 1 (1 bit)
DMAMUXEN : DMAMUXEN
bits : 2 - 2 (1 bit)
ADC12EN : ADC12EN
bits : 5 - 5 (1 bit)
USBOEN : USBOEN
bits : 8 - 8 (1 bit)
SDMMC3EN : SDMMC3EN
bits : 16 - 16 (1 bit)
This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
address_offset : 0xA1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1EN : DMA1EN
bits : 0 - 0 (1 bit)
DMA2EN : DMA2EN
bits : 1 - 1 (1 bit)
DMAMUXEN : DMAMUXEN
bits : 2 - 2 (1 bit)
ADC12EN : ADC12EN
bits : 5 - 5 (1 bit)
USBOEN : USBOEN
bits : 8 - 8 (1 bit)
SDMMC3EN : SDMMC3EN
bits : 16 - 16 (1 bit)
This register is used to set the peripheral clock enable bit of the corresponding peripheral
address_offset : 0xA20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMIEN : DCMIEN
bits : 0 - 0 (1 bit)
CRYP2EN : CRYP2EN
bits : 4 - 4 (1 bit)
HASH2EN : HASH2EN
bits : 5 - 5 (1 bit)
RNG2EN : RNG2EN
bits : 6 - 6 (1 bit)
CRC2EN : CRC2EN
bits : 7 - 7 (1 bit)
HSEMEN : HSEMEN
bits : 11 - 11 (1 bit)
IPCCEN : IPCCEN
bits : 12 - 12 (1 bit)
This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
address_offset : 0xA24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMIEN : DCMIEN
bits : 0 - 0 (1 bit)
CRYP2EN : CRYP2EN
bits : 4 - 4 (1 bit)
HASH2EN : HASH2EN
bits : 5 - 5 (1 bit)
RNG2EN : RNG2EN
bits : 6 - 6 (1 bit)
CRC2EN : CRC2EN
bits : 7 - 7 (1 bit)
HSEMEN : HSEMEN
bits : 11 - 11 (1 bit)
IPCCEN : IPCCEN
bits : 12 - 12 (1 bit)
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU.
address_offset : 0xA28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOAEN : GPIOAEN
bits : 0 - 0 (1 bit)
GPIOBEN : GPIOBEN
bits : 1 - 1 (1 bit)
GPIOCEN : GPIOCEN
bits : 2 - 2 (1 bit)
GPIODEN : GPIODEN
bits : 3 - 3 (1 bit)
GPIOEEN : GPIOEEN
bits : 4 - 4 (1 bit)
GPIOFEN : GPIOFEN
bits : 5 - 5 (1 bit)
GPIOGEN : GPIOGEN
bits : 6 - 6 (1 bit)
GPIOHEN : GPIOHEN
bits : 7 - 7 (1 bit)
GPIOIEN : GPIOIEN
bits : 8 - 8 (1 bit)
GPIOJEN : GPIOJEN
bits : 9 - 9 (1 bit)
GPIOKEN : GPIOKEN
bits : 10 - 10 (1 bit)
This register is used to clear the peripheral clock enable bit
address_offset : 0xA2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOAEN : GPIOAEN
bits : 0 - 0 (1 bit)
GPIOBEN : GPIOBEN
bits : 1 - 1 (1 bit)
GPIOCEN : GPIOCEN
bits : 2 - 2 (1 bit)
GPIODEN : GPIODEN
bits : 3 - 3 (1 bit)
GPIOEEN : GPIOEEN
bits : 4 - 4 (1 bit)
GPIOFEN : GPIOFEN
bits : 5 - 5 (1 bit)
GPIOGEN : GPIOGEN
bits : 6 - 6 (1 bit)
GPIOHEN : GPIOHEN
bits : 7 - 7 (1 bit)
GPIOIEN : GPIOIEN
bits : 8 - 8 (1 bit)
GPIOJEN : GPIOJEN
bits : 9 - 9 (1 bit)
GPIOKEN : GPIOKEN
bits : 10 - 10 (1 bit)
This register is used to set the peripheral clock enable bit
address_offset : 0xA38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RETRAMEN : RETRAMEN
bits : 4 - 4 (1 bit)
This register is used to clear the peripheral clock enable bit.
address_offset : 0xA3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RETRAMEN : RETRAMEN
bits : 4 - 4 (1 bit)
This register is used to configure the PLL2. It is not recommended to change the content of this register when the PLL2 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD_PER : MOD_PER
bits : 0 - 12 (13 bit)
TPDFN_DIS : TPDFN_DIS
bits : 13 - 13 (1 bit)
RPDFN_DIS : RPDFN_DIS
bits : 14 - 14 (1 bit)
SSCG_MODE : SSCG_MODE
bits : 15 - 15 (1 bit)
INC_STEP : INC_STEP
bits : 16 - 30 (15 bit)
This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return . Writing a sets the corresponding bit to .
address_offset : 0xA80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2EN : TIM2EN
bits : 0 - 0 (1 bit)
TIM3EN : TIM3EN
bits : 1 - 1 (1 bit)
TIM4EN : TIM4EN
bits : 2 - 2 (1 bit)
TIM5EN : TIM5EN
bits : 3 - 3 (1 bit)
TIM6EN : TIM6EN
bits : 4 - 4 (1 bit)
TIM7EN : TIM7EN
bits : 5 - 5 (1 bit)
TIM12EN : TIM12EN
bits : 6 - 6 (1 bit)
TIM13EN : TIM13EN
bits : 7 - 7 (1 bit)
TIM14EN : TIM14EN
bits : 8 - 8 (1 bit)
LPTIM1EN : LPTIM1EN
bits : 9 - 9 (1 bit)
SPI2EN : SPI2EN
bits : 11 - 11 (1 bit)
SPI3EN : SPI3EN
bits : 12 - 12 (1 bit)
USART2EN : USART2EN
bits : 14 - 14 (1 bit)
USART3EN : USART3EN
bits : 15 - 15 (1 bit)
UART4EN : UART4EN
bits : 16 - 16 (1 bit)
UART5EN : UART5EN
bits : 17 - 17 (1 bit)
UART7EN : UART7EN
bits : 18 - 18 (1 bit)
UART8EN : UART8EN
bits : 19 - 19 (1 bit)
I2C1EN : I2C1EN
bits : 21 - 21 (1 bit)
I2C2EN : I2C2EN
bits : 22 - 22 (1 bit)
I2C3EN : I2C3EN
bits : 23 - 23 (1 bit)
I2C5EN : I2C5EN
bits : 24 - 24 (1 bit)
SPDIFEN : SPDIFEN
bits : 26 - 26 (1 bit)
CECEN : CECEN
bits : 27 - 27 (1 bit)
WWDG1EN : WWDG1EN
bits : 28 - 28 (1 bit)
DAC12EN : DAC12EN
bits : 29 - 29 (1 bit)
MDIOSEN : MDIOSEN
bits : 31 - 31 (1 bit)
This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
address_offset : 0xA84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2EN : TIM2EN
bits : 0 - 0 (1 bit)
TIM3EN : TIM3EN
bits : 1 - 1 (1 bit)
TIM4EN : TIM4EN
bits : 2 - 2 (1 bit)
TIM5EN : TIM5EN
bits : 3 - 3 (1 bit)
TIM6EN : TIM6EN
bits : 4 - 4 (1 bit)
TIM7EN : TIM7EN
bits : 5 - 5 (1 bit)
TIM12EN : TIM12EN
bits : 6 - 6 (1 bit)
TIM13EN : TIM13EN
bits : 7 - 7 (1 bit)
TIM14EN : TIM14EN
bits : 8 - 8 (1 bit)
LPTIM1EN : LPTIM1EN
bits : 9 - 9 (1 bit)
SPI2EN : SPI2EN
bits : 11 - 11 (1 bit)
SPI3EN : SPI3EN
bits : 12 - 12 (1 bit)
USART2EN : USART2EN
bits : 14 - 14 (1 bit)
USART3EN : USART3EN
bits : 15 - 15 (1 bit)
UART4EN : UART4EN
bits : 16 - 16 (1 bit)
UART5EN : UART5EN
bits : 17 - 17 (1 bit)
UART7EN : UART7EN
bits : 18 - 18 (1 bit)
UART8EN : UART8EN
bits : 19 - 19 (1 bit)
I2C1EN : I2C1EN
bits : 21 - 21 (1 bit)
I2C2EN : I2C2EN
bits : 22 - 22 (1 bit)
I2C3EN : I2C3EN
bits : 23 - 23 (1 bit)
I2C5EN : I2C5EN
bits : 24 - 24 (1 bit)
SPDIFEN : SPDIFEN
bits : 26 - 26 (1 bit)
CECEN : CECEN
bits : 27 - 27 (1 bit)
DAC12EN : DAC12EN
bits : 29 - 29 (1 bit)
MDIOSEN : MDIOSEN
bits : 31 - 31 (1 bit)
This register is used to set the peripheral clock enable bit
address_offset : 0xA88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1EN : TIM1EN
bits : 0 - 0 (1 bit)
TIM8EN : TIM8EN
bits : 1 - 1 (1 bit)
TIM15EN : TIM15EN
bits : 2 - 2 (1 bit)
TIM16EN : TIM16EN
bits : 3 - 3 (1 bit)
TIM17EN : TIM17EN
bits : 4 - 4 (1 bit)
SPI1EN : SPI1EN
bits : 8 - 8 (1 bit)
SPI4EN : SPI4EN
bits : 9 - 9 (1 bit)
SPI5EN : SPI5EN
bits : 10 - 10 (1 bit)
USART6EN : USART6EN
bits : 13 - 13 (1 bit)
SAI1EN : SAI1EN
bits : 16 - 16 (1 bit)
SAI2EN : SAI2EN
bits : 17 - 17 (1 bit)
SAI3EN : SAI3EN
bits : 18 - 18 (1 bit)
DFSDMEN : DFSDMEN
bits : 20 - 20 (1 bit)
ADFSDMEN : ADFSDMEN
bits : 21 - 21 (1 bit)
FDCANEN : FDCANEN
bits : 24 - 24 (1 bit)
This register is used to clear the peripheral clock enable bit
address_offset : 0xA8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1EN : TIM1EN
bits : 0 - 0 (1 bit)
TIM8EN : TIM8EN
bits : 1 - 1 (1 bit)
TIM15EN : TIM15EN
bits : 2 - 2 (1 bit)
TIM16EN : TIM16EN
bits : 3 - 3 (1 bit)
TIM17EN : TIM17EN
bits : 4 - 4 (1 bit)
SPI1EN : SPI1EN
bits : 8 - 8 (1 bit)
SPI4EN : SPI4EN
bits : 9 - 9 (1 bit)
SPI5EN : SPI5EN
bits : 10 - 10 (1 bit)
USART6EN : USART6EN
bits : 13 - 13 (1 bit)
SAI1EN : SAI1EN
bits : 16 - 16 (1 bit)
SAI2EN : SAI2EN
bits : 17 - 17 (1 bit)
SAI3EN : SAI3EN
bits : 18 - 18 (1 bit)
DFSDMEN : DFSDMEN
bits : 20 - 20 (1 bit)
ADFSDMEN : ADFSDMEN
bits : 21 - 21 (1 bit)
FDCANEN : FDCANEN
bits : 24 - 24 (1 bit)
This register is used to set the peripheral clock enable bit
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM2EN : LPTIM2EN
bits : 0 - 0 (1 bit)
LPTIM3EN : LPTIM3EN
bits : 1 - 1 (1 bit)
LPTIM4EN : LPTIM4EN
bits : 2 - 2 (1 bit)
LPTIM5EN : LPTIM5EN
bits : 3 - 3 (1 bit)
SAI4EN : SAI4EN
bits : 8 - 8 (1 bit)
SYSCFGEN : SYSCFGEN
bits : 11 - 11 (1 bit)
VREFEN : VREFEN
bits : 13 - 13 (1 bit)
DTSEN : DTSEN
bits : 16 - 16 (1 bit)
HDPEN : HDPEN
bits : 20 - 20 (1 bit)
This register is used to clear the peripheral clock enable bit
address_offset : 0xA94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM2EN : LPTIM2EN
bits : 0 - 0 (1 bit)
LPTIM3EN : LPTIM3EN
bits : 1 - 1 (1 bit)
LPTIM4EN : LPTIM4EN
bits : 2 - 2 (1 bit)
LPTIM5EN : LPTIM5EN
bits : 3 - 3 (1 bit)
SAI4EN : SAI4EN
bits : 8 - 8 (1 bit)
SYSCFGEN : SYSCFGEN
bits : 11 - 11 (1 bit)
VREFEN : VREFEN
bits : 13 - 13 (1 bit)
DTSEN : DTSEN
bits : 16 - 16 (1 bit)
HDPEN : HDPEN
bits : 20 - 20 (1 bit)
This register is used to set the peripheral clock enable bit
address_offset : 0xA98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1EN : DMA1EN
bits : 0 - 0 (1 bit)
DMA2EN : DMA2EN
bits : 1 - 1 (1 bit)
DMAMUXEN : DMAMUXEN
bits : 2 - 2 (1 bit)
ADC12EN : ADC12EN
bits : 5 - 5 (1 bit)
USBOEN : USBOEN
bits : 8 - 8 (1 bit)
SDMMC3EN : SDMMC3EN
bits : 16 - 16 (1 bit)
This register is used to clear the peripheral clock enable bit
address_offset : 0xA9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1EN : DMA1EN
bits : 0 - 0 (1 bit)
DMA2EN : DMA2EN
bits : 1 - 1 (1 bit)
DMAMUXEN : DMAMUXEN
bits : 2 - 2 (1 bit)
ADC12EN : ADC12EN
bits : 5 - 5 (1 bit)
USBOEN : USBOEN
bits : 8 - 8 (1 bit)
SDMMC3EN : SDMMC3EN
bits : 16 - 16 (1 bit)
This register is used to set the peripheral clock enable bit
address_offset : 0xAA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMIEN : DCMIEN
bits : 0 - 0 (1 bit)
CRYP2EN : CRYP2EN
bits : 4 - 4 (1 bit)
HASH2EN : HASH2EN
bits : 5 - 5 (1 bit)
RNG2EN : RNG2EN
bits : 6 - 6 (1 bit)
CRC2EN : CRC2EN
bits : 7 - 7 (1 bit)
HSEMEN : HSEMEN
bits : 11 - 11 (1 bit)
IPCCEN : IPCCEN
bits : 12 - 12 (1 bit)
This register is used to clear the peripheral clock enable bit
address_offset : 0xAA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMIEN : DCMIEN
bits : 0 - 0 (1 bit)
CRYP2EN : CRYP2EN
bits : 4 - 4 (1 bit)
HASH2EN : HASH2EN
bits : 5 - 5 (1 bit)
RNG2EN : RNG2EN
bits : 6 - 6 (1 bit)
CRC2EN : CRC2EN
bits : 7 - 7 (1 bit)
HSEMEN : HSEMEN
bits : 11 - 11 (1 bit)
IPCCEN : IPCCEN
bits : 12 - 12 (1 bit)
This register is used to set the peripheral clock enable bit
address_offset : 0xAA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOAEN : GPIOAEN
bits : 0 - 0 (1 bit)
GPIOBEN : GPIOBEN
bits : 1 - 1 (1 bit)
GPIOCEN : GPIOCEN
bits : 2 - 2 (1 bit)
GPIODEN : GPIODEN
bits : 3 - 3 (1 bit)
GPIOEEN : GPIOEEN
bits : 4 - 4 (1 bit)
GPIOFEN : GPIOFEN
bits : 5 - 5 (1 bit)
GPIOGEN : GPIOGEN
bits : 6 - 6 (1 bit)
GPIOHEN : GPIOHEN
bits : 7 - 7 (1 bit)
GPIOIEN : GPIOIEN
bits : 8 - 8 (1 bit)
GPIOJEN : GPIOJEN
bits : 9 - 9 (1 bit)
GPIOKEN : GPIOKEN
bits : 10 - 10 (1 bit)
This register is used to clear the peripheral clock enable bit
address_offset : 0xAAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOAEN : GPIOAEN
bits : 0 - 0 (1 bit)
GPIOBEN : GPIOBEN
bits : 1 - 1 (1 bit)
GPIOCEN : GPIOCEN
bits : 2 - 2 (1 bit)
GPIODEN : GPIODEN
bits : 3 - 3 (1 bit)
GPIOEEN : GPIOEEN
bits : 4 - 4 (1 bit)
GPIOFEN : GPIOFEN
bits : 5 - 5 (1 bit)
GPIOGEN : GPIOGEN
bits : 6 - 6 (1 bit)
GPIOHEN : GPIOHEN
bits : 7 - 7 (1 bit)
GPIOIEN : GPIOIEN
bits : 8 - 8 (1 bit)
GPIOJEN : GPIOJEN
bits : 9 - 9 (1 bit)
GPIOKEN : GPIOKEN
bits : 10 - 10 (1 bit)
This register is used to set the peripheral clock enable bit
address_offset : 0xAB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSRAMEN : SYSRAMEN
bits : 0 - 0 (1 bit)
This register is used to clear the peripheral clock enable bit
address_offset : 0xAB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSRAMEN : SYSRAMEN
bits : 0 - 0 (1 bit)
This register is used to set the peripheral clock enable bit
address_offset : 0xAB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RETRAMEN : RETRAMEN
bits : 4 - 4 (1 bit)
This register is used to clear the peripheral clock enable bit
address_offset : 0xABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RETRAMEN : RETRAMEN
bits : 4 - 4 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bits
address_offset : 0xB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2LPEN : TIM2LPEN
bits : 0 - 0 (1 bit)
TIM3LPEN : TIM3LPEN
bits : 1 - 1 (1 bit)
TIM4LPEN : TIM4LPEN
bits : 2 - 2 (1 bit)
TIM5LPEN : TIM5LPEN
bits : 3 - 3 (1 bit)
TIM6LPEN : TIM6LPEN
bits : 4 - 4 (1 bit)
TIM7LPEN : TIM7LPEN
bits : 5 - 5 (1 bit)
TIM12LPEN : TIM12LPEN
bits : 6 - 6 (1 bit)
TIM13LPEN : TIM13LPEN
bits : 7 - 7 (1 bit)
TIM14LPEN : TIM14LPEN
bits : 8 - 8 (1 bit)
LPTIM1LPEN : LPTIM1LPEN
bits : 9 - 9 (1 bit)
SPI2LPEN : SPI2LPEN
bits : 11 - 11 (1 bit)
SPI3LPEN : SPI3LPEN
bits : 12 - 12 (1 bit)
USART2LPEN : USART2LPEN
bits : 14 - 14 (1 bit)
USART3LPEN : USART3LPEN
bits : 15 - 15 (1 bit)
UART4LPEN : UART4LPEN
bits : 16 - 16 (1 bit)
UART5LPEN : UART5LPEN
bits : 17 - 17 (1 bit)
UART7LPEN : UART7LPEN
bits : 18 - 18 (1 bit)
UART8LPEN : UART8LPEN
bits : 19 - 19 (1 bit)
I2C1LPEN : I2C1LPEN
bits : 21 - 21 (1 bit)
I2C2LPEN : I2C2LPEN
bits : 22 - 22 (1 bit)
I2C3LPEN : I2C3LPEN
bits : 23 - 23 (1 bit)
I2C5LPEN : I2C5LPEN
bits : 24 - 24 (1 bit)
SPDIFLPEN : SPDIFLPEN
bits : 26 - 26 (1 bit)
CECLPEN : CECLPEN
bits : 27 - 27 (1 bit)
DAC12LPEN : DAC12LPEN
bits : 29 - 29 (1 bit)
MDIOSLPEN : MDIOSLPEN
bits : 31 - 31 (1 bit)
This register is used by the MPU in order to clear the PERxLPEN bits .
address_offset : 0xB04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2LPEN : TIM2LPEN
bits : 0 - 0 (1 bit)
TIM3LPEN : TIM3LPEN
bits : 1 - 1 (1 bit)
TIM4LPEN : TIM4LPEN
bits : 2 - 2 (1 bit)
TIM5LPEN : TIM5LPEN
bits : 3 - 3 (1 bit)
TIM6LPEN : TIM6LPEN
bits : 4 - 4 (1 bit)
TIM7LPEN : TIM7LPEN
bits : 5 - 5 (1 bit)
TIM12LPEN : TIM12LPEN
bits : 6 - 6 (1 bit)
TIM13LPEN : TIM13LPEN
bits : 7 - 7 (1 bit)
TIM14LPEN : TIM14LPEN
bits : 8 - 8 (1 bit)
LPTIM1LPEN : LPTIM1LPEN
bits : 9 - 9 (1 bit)
SPI2LPEN : SPI2LPEN
bits : 11 - 11 (1 bit)
SPI3LPEN : SPI3LPEN
bits : 12 - 12 (1 bit)
USART2LPEN : USART2LPEN
bits : 14 - 14 (1 bit)
USART3LPEN : USART3LPEN
bits : 15 - 15 (1 bit)
UART4LPEN : UART4LPEN
bits : 16 - 16 (1 bit)
UART5LPEN : UART5LPEN
bits : 17 - 17 (1 bit)
UART7LPEN : UART7LPEN
bits : 18 - 18 (1 bit)
UART8LPEN : UART8LPEN
bits : 19 - 19 (1 bit)
I2C1LPEN : I2C1LPEN
bits : 21 - 21 (1 bit)
I2C2LPEN : I2C2LPEN
bits : 22 - 22 (1 bit)
I2C3LPEN : I2C3LPEN
bits : 23 - 23 (1 bit)
I2C5LPEN : I2C5LPEN
bits : 24 - 24 (1 bit)
SPDIFLPEN : SPDIFLPEN
bits : 26 - 26 (1 bit)
CECLPEN : CECLPEN
bits : 27 - 27 (1 bit)
DAC12LPEN : DAC12LPEN
bits : 29 - 29 (1 bit)
MDIOSLPEN : MDIOSLPEN
bits : 31 - 31 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bits
address_offset : 0xB08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1LPEN : TIM1LPEN
bits : 0 - 0 (1 bit)
TIM8LPEN : TIM8LPEN
bits : 1 - 1 (1 bit)
TIM15LPEN : TIM15LPEN
bits : 2 - 2 (1 bit)
TIM16LPEN : TIM16LPEN
bits : 3 - 3 (1 bit)
TIM17LPEN : TIM17LPEN
bits : 4 - 4 (1 bit)
SPI1LPEN : SPI1LPEN
bits : 8 - 8 (1 bit)
SPI4LPEN : SPI4LPEN
bits : 9 - 9 (1 bit)
SPI5LPEN : SPI5LPEN
bits : 10 - 10 (1 bit)
USART6LPEN : USART6LPEN
bits : 13 - 13 (1 bit)
SAI1LPEN : SAI1LPEN
bits : 16 - 16 (1 bit)
SAI2LPEN : SAI2LPEN
bits : 17 - 17 (1 bit)
SAI3LPEN : SAI3LPEN
bits : 18 - 18 (1 bit)
DFSDMLPEN : DFSDMLPEN
bits : 20 - 20 (1 bit)
ADFSDMLPEN : ADFSDMLPEN
bits : 21 - 21 (1 bit)
FDCANLPEN : FDCANLPEN
bits : 24 - 24 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bits
address_offset : 0xB0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1LPEN : TIM1LPEN
bits : 0 - 0 (1 bit)
TIM8LPEN : TIM8LPEN
bits : 1 - 1 (1 bit)
TIM15LPEN : TIM15LPEN
bits : 2 - 2 (1 bit)
TIM16LPEN : TIM16LPEN
bits : 3 - 3 (1 bit)
TIM17LPEN : TIM17LPEN
bits : 4 - 4 (1 bit)
SPI1LPEN : SPI1LPEN
bits : 8 - 8 (1 bit)
SPI4LPEN : SPI4LPEN
bits : 9 - 9 (1 bit)
SPI5LPEN : SPI5LPEN
bits : 10 - 10 (1 bit)
USART6LPEN : USART6LPEN
bits : 13 - 13 (1 bit)
SAI1LPEN : SAI1LPEN
bits : 16 - 16 (1 bit)
SAI2LPEN : SAI2LPEN
bits : 17 - 17 (1 bit)
SAI3LPEN : SAI3LPEN
bits : 18 - 18 (1 bit)
DFSDMLPEN : DFSDMLPEN
bits : 20 - 20 (1 bit)
ADFSDMLPEN : ADFSDMLPEN
bits : 21 - 21 (1 bit)
FDCANLPEN : FDCANLPEN
bits : 24 - 24 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bits
address_offset : 0xB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM2LPEN : LPTIM2LPEN
bits : 0 - 0 (1 bit)
LPTIM3LPEN : LPTIM3LPEN
bits : 1 - 1 (1 bit)
LPTIM4LPEN : LPTIM4LPEN
bits : 2 - 2 (1 bit)
LPTIM5LPEN : LPTIM5LPEN
bits : 3 - 3 (1 bit)
SAI4LPEN : SAI4LPEN
bits : 8 - 8 (1 bit)
SYSCFGLPEN : SYSCFGLPEN
bits : 11 - 11 (1 bit)
VREFLPEN : VREFLPEN
bits : 13 - 13 (1 bit)
DTSLPEN : DTSLPEN
bits : 16 - 16 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bits
address_offset : 0xB14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM2LPEN : LPTIM2LPEN
bits : 0 - 0 (1 bit)
LPTIM3LPEN : LPTIM3LPEN
bits : 1 - 1 (1 bit)
LPTIM4LPEN : LPTIM4LPEN
bits : 2 - 2 (1 bit)
LPTIM5LPEN : LPTIM5LPEN
bits : 3 - 3 (1 bit)
SAI4LPEN : SAI4LPEN
bits : 8 - 8 (1 bit)
SYSCFGLPEN : SYSCFGLPEN
bits : 11 - 11 (1 bit)
VREFLPEN : VREFLPEN
bits : 13 - 13 (1 bit)
DTSLPEN : DTSLPEN
bits : 16 - 16 (1 bit)
This register is used by the MPU in order to set the PERxLPEN bit.
address_offset : 0xB18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1LPEN : DMA1LPEN
bits : 0 - 0 (1 bit)
DMA2LPEN : DMA2LPEN
bits : 1 - 1 (1 bit)
DMAMUXLPEN : DMAMUXLPEN
bits : 2 - 2 (1 bit)
ADC12LPEN : ADC12LPEN
bits : 5 - 5 (1 bit)
USBOLPEN : USBOLPEN
bits : 8 - 8 (1 bit)
SDMMC3LPEN : SDMMC3LPEN
bits : 16 - 16 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bits
address_offset : 0xB1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1LPEN : DMA1LPEN
bits : 0 - 0 (1 bit)
DMA2LPEN : DMA2LPEN
bits : 1 - 1 (1 bit)
DMAMUXLPEN : DMAMUXLPEN
bits : 2 - 2 (1 bit)
ADC12LPEN : ADC12LPEN
bits : 5 - 5 (1 bit)
USBOLPEN : USBOLPEN
bits : 8 - 8 (1 bit)
SDMMC3LPEN : SDMMC3LPEN
bits : 16 - 16 (1 bit)
This register is used by the MPU
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMILPEN : DCMILPEN
bits : 0 - 0 (1 bit)
CRYP2LPEN : CRYP2LPEN
bits : 4 - 4 (1 bit)
HASH2LPEN : HASH2LPEN
bits : 5 - 5 (1 bit)
RNG2LPEN : RNG2LPEN
bits : 6 - 6 (1 bit)
CRC2LPEN : CRC2LPEN
bits : 7 - 7 (1 bit)
HSEMLPEN : HSEMLPEN
bits : 11 - 11 (1 bit)
IPCCLPEN : IPCCLPEN
bits : 12 - 12 (1 bit)
This register is used by the MPU in order to clear the PERxLPEN bit
address_offset : 0xB24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMILPEN : DCMILPEN
bits : 0 - 0 (1 bit)
CRYP2LPEN : CRYP2LPEN
bits : 4 - 4 (1 bit)
HASH2LPEN : HASH2LPEN
bits : 5 - 5 (1 bit)
RNG2LPEN : RNG2LPEN
bits : 6 - 6 (1 bit)
CRC2LPEN : CRC2LPEN
bits : 7 - 7 (1 bit)
HSEMLPEN : HSEMLPEN
bits : 11 - 11 (1 bit)
IPCCLPEN : IPCCLPEN
bits : 12 - 12 (1 bit)
This register is used by the MPU
address_offset : 0xB28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOALPEN : GPIOALPEN
bits : 0 - 0 (1 bit)
GPIOBLPEN : GPIOBLPEN
bits : 1 - 1 (1 bit)
GPIOCLPEN : GPIOCLPEN
bits : 2 - 2 (1 bit)
GPIODLPEN : GPIODLPEN
bits : 3 - 3 (1 bit)
GPIOELPEN : GPIOELPEN
bits : 4 - 4 (1 bit)
GPIOFLPEN : GPIOFLPEN
bits : 5 - 5 (1 bit)
GPIOGLPEN : GPIOGLPEN
bits : 6 - 6 (1 bit)
GPIOHLPEN : GPIOHLPEN
bits : 7 - 7 (1 bit)
GPIOILPEN : GPIOILPEN
bits : 8 - 8 (1 bit)
GPIOJLPEN : GPIOJLPEN
bits : 9 - 9 (1 bit)
GPIOKLPEN : GPIOKLPEN
bits : 10 - 10 (1 bit)
This register is used by the MPU
address_offset : 0xB2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOALPEN : GPIOALPEN
bits : 0 - 0 (1 bit)
GPIOBLPEN : GPIOBLPEN
bits : 1 - 1 (1 bit)
GPIOCLPEN : GPIOCLPEN
bits : 2 - 2 (1 bit)
GPIODLPEN : GPIODLPEN
bits : 3 - 3 (1 bit)
GPIOELPEN : GPIOELPEN
bits : 4 - 4 (1 bit)
GPIOFLPEN : GPIOFLPEN
bits : 5 - 5 (1 bit)
GPIOGLPEN : GPIOGLPEN
bits : 6 - 6 (1 bit)
GPIOHLPEN : GPIOHLPEN
bits : 7 - 7 (1 bit)
GPIOILPEN : GPIOILPEN
bits : 8 - 8 (1 bit)
GPIOJLPEN : GPIOJLPEN
bits : 9 - 9 (1 bit)
GPIOKLPEN : GPIOKLPEN
bits : 10 - 10 (1 bit)
This register is used by the MPU
address_offset : 0xB30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSRAMLPEN : SYSRAMLPEN
bits : 0 - 0 (1 bit)
This register is used by the MPU
address_offset : 0xB34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSRAMLPEN : SYSRAMLPEN
bits : 0 - 0 (1 bit)
This register is used by the MPU in order to set the PERxLPEN bit
address_offset : 0xB38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM1LPEN : SRAM1LPEN
bits : 0 - 0 (1 bit)
SRAM2LPEN : SRAM2LPEN
bits : 1 - 1 (1 bit)
SRAM34LPEN : SRAM34LPEN
bits : 2 - 2 (1 bit)
RETRAMLPEN : RETRAMLPEN
bits : 4 - 4 (1 bit)
This register is used by the MPU in order to clear the PERxLPEN bit
address_offset : 0xB3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM1LPEN : SRAM1LPEN
bits : 0 - 0 (1 bit)
SRAM2LPEN : SRAM2LPEN
bits : 1 - 1 (1 bit)
SRAM34LPEN : SRAM34LPEN
bits : 2 - 2 (1 bit)
RETRAMLPEN : RETRAMLPEN
bits : 4 - 4 (1 bit)
This register is used by the MCU in order to set the PERxLPEN bit.
address_offset : 0xB80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2LPEN : TIM2LPEN
bits : 0 - 0 (1 bit)
TIM3LPEN : TIM3LPEN
bits : 1 - 1 (1 bit)
TIM4LPEN : TIM4LPEN
bits : 2 - 2 (1 bit)
TIM5LPEN : TIM5LPEN
bits : 3 - 3 (1 bit)
TIM6LPEN : TIM6LPEN
bits : 4 - 4 (1 bit)
TIM7LPEN : TIM7LPEN
bits : 5 - 5 (1 bit)
TIM12LPEN : TIM12LPEN
bits : 6 - 6 (1 bit)
TIM13LPEN : TIM13LPEN
bits : 7 - 7 (1 bit)
TIM14LPEN : TIM14LPEN
bits : 8 - 8 (1 bit)
LPTIM1LPEN : LPTIM1LPEN
bits : 9 - 9 (1 bit)
SPI2LPEN : SPI2LPEN
bits : 11 - 11 (1 bit)
SPI3LPEN : SPI3LPEN
bits : 12 - 12 (1 bit)
USART2LPEN : USART2LPEN
bits : 14 - 14 (1 bit)
USART3LPEN : USART3LPEN
bits : 15 - 15 (1 bit)
UART4LPEN : UART4LPEN
bits : 16 - 16 (1 bit)
UART5LPEN : UART5LPEN
bits : 17 - 17 (1 bit)
UART7LPEN : UART7LPEN
bits : 18 - 18 (1 bit)
UART8LPEN : UART8LPEN
bits : 19 - 19 (1 bit)
I2C1LPEN : I2C1LPEN
bits : 21 - 21 (1 bit)
I2C2LPEN : I2C2LPEN
bits : 22 - 22 (1 bit)
I2C3LPEN : I2C3LPEN
bits : 23 - 23 (1 bit)
I2C5LPEN : I2C5LPEN
bits : 24 - 24 (1 bit)
SPDIFLPEN : SPDIFLPEN
bits : 26 - 26 (1 bit)
CECLPEN : CECLPEN
bits : 27 - 27 (1 bit)
WWDG1LPEN : WWDG1LPEN
bits : 28 - 28 (1 bit)
DAC12LPEN : DAC12LPEN
bits : 29 - 29 (1 bit)
MDIOSLPEN : MDIOSLPEN
bits : 31 - 31 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bits
address_offset : 0xB84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2LPEN : TIM2LPEN
bits : 0 - 0 (1 bit)
TIM3LPEN : TIM3LPEN
bits : 1 - 1 (1 bit)
TIM4LPEN : TIM4LPEN
bits : 2 - 2 (1 bit)
TIM5LPEN : TIM5LPEN
bits : 3 - 3 (1 bit)
TIM6LPEN : TIM6LPEN
bits : 4 - 4 (1 bit)
TIM7LPEN : TIM7LPEN
bits : 5 - 5 (1 bit)
TIM12LPEN : TIM12LPEN
bits : 6 - 6 (1 bit)
TIM13LPEN : TIM13LPEN
bits : 7 - 7 (1 bit)
TIM14LPEN : TIM14LPEN
bits : 8 - 8 (1 bit)
LPTIM1LPEN : LPTIM1LPEN
bits : 9 - 9 (1 bit)
SPI2LPEN : SPI2LPEN
bits : 11 - 11 (1 bit)
SPI3LPEN : SPI3LPEN
bits : 12 - 12 (1 bit)
USART2LPEN : USART2LPEN
bits : 14 - 14 (1 bit)
USART3LPEN : USART3LPEN
bits : 15 - 15 (1 bit)
UART4LPEN : UART4LPEN
bits : 16 - 16 (1 bit)
UART5LPEN : UART5LPEN
bits : 17 - 17 (1 bit)
UART7LPEN : UART7LPEN
bits : 18 - 18 (1 bit)
UART8LPEN : UART8LPEN
bits : 19 - 19 (1 bit)
I2C1LPEN : I2C1LPEN
bits : 21 - 21 (1 bit)
I2C2LPEN : I2C2LPEN
bits : 22 - 22 (1 bit)
I2C3LPEN : I2C3LPEN
bits : 23 - 23 (1 bit)
I2C5LPEN : I2C5LPEN
bits : 24 - 24 (1 bit)
SPDIFLPEN : SPDIFLPEN
bits : 26 - 26 (1 bit)
CECLPEN : CECLPEN
bits : 27 - 27 (1 bit)
WWDG1LPEN : WWDG1LPEN
bits : 28 - 28 (1 bit)
DAC12LPEN : DAC12LPEN
bits : 29 - 29 (1 bit)
MDIOSLPEN : MDIOSLPEN
bits : 31 - 31 (1 bit)
This register is used by the MCU in order to set the PERxLPEN bit.
address_offset : 0xB88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1LPEN : TIM1LPEN
bits : 0 - 0 (1 bit)
TIM8LPEN : TIM8LPEN
bits : 1 - 1 (1 bit)
TIM15LPEN : TIM15LPEN
bits : 2 - 2 (1 bit)
TIM16LPEN : TIM16LPEN
bits : 3 - 3 (1 bit)
TIM17LPEN : TIM17LPEN
bits : 4 - 4 (1 bit)
SPI1LPEN : SPI1LPEN
bits : 8 - 8 (1 bit)
SPI4LPEN : SPI4LPEN
bits : 9 - 9 (1 bit)
SPI5LPEN : SPI5LPEN
bits : 10 - 10 (1 bit)
USART6LPEN : USART6LPEN
bits : 13 - 13 (1 bit)
SAI1LPEN : SAI1LPEN
bits : 16 - 16 (1 bit)
SAI2LPEN : SAI2LPEN
bits : 17 - 17 (1 bit)
SAI3LPEN : SAI3LPEN
bits : 18 - 18 (1 bit)
DFSDMLPEN : DFSDMLPEN
bits : 20 - 20 (1 bit)
ADFSDMLPEN : ADFSDMLPEN
bits : 21 - 21 (1 bit)
FDCANLPEN : FDCANLPEN
bits : 24 - 24 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bit
address_offset : 0xB8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1LPEN : TIM1LPEN
bits : 0 - 0 (1 bit)
TIM8LPEN : TIM8LPEN
bits : 1 - 1 (1 bit)
TIM15LPEN : TIM15LPEN
bits : 2 - 2 (1 bit)
TIM16LPEN : TIM16LPEN
bits : 3 - 3 (1 bit)
TIM17LPEN : TIM17LPEN
bits : 4 - 4 (1 bit)
SPI1LPEN : SPI1LPEN
bits : 8 - 8 (1 bit)
SPI4LPEN : SPI4LPEN
bits : 9 - 9 (1 bit)
SPI5LPEN : SPI5LPEN
bits : 10 - 10 (1 bit)
USART6LPEN : USART6LPEN
bits : 13 - 13 (1 bit)
SAI1LPEN : SAI1LPEN
bits : 16 - 16 (1 bit)
SAI2LPEN : SAI2LPEN
bits : 17 - 17 (1 bit)
SAI3LPEN : SAI3LPEN
bits : 18 - 18 (1 bit)
DFSDMLPEN : DFSDMLPEN
bits : 20 - 20 (1 bit)
ADFSDMLPEN : ADFSDMLPEN
bits : 21 - 21 (1 bit)
FDCANLPEN : FDCANLPEN
bits : 24 - 24 (1 bit)
This register is used by the MCU in order to set the PERxLPEN bit.
address_offset : 0xB90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM2LPEN : LPTIM2LPEN
bits : 0 - 0 (1 bit)
LPTIM3LPEN : LPTIM3LPEN
bits : 1 - 1 (1 bit)
LPTIM4LPEN : LPTIM4LPEN
bits : 2 - 2 (1 bit)
LPTIM5LPEN : LPTIM5LPEN
bits : 3 - 3 (1 bit)
SAI4LPEN : SAI4LPEN
bits : 8 - 8 (1 bit)
SYSCFGLPEN : SYSCFGLPEN
bits : 11 - 11 (1 bit)
VREFLPEN : VREFLPEN
bits : 13 - 13 (1 bit)
DTSLPEN : DTSLPEN
bits : 16 - 16 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bit
address_offset : 0xB94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIM2LPEN : LPTIM2LPEN
bits : 0 - 0 (1 bit)
LPTIM3LPEN : LPTIM3LPEN
bits : 1 - 1 (1 bit)
LPTIM4LPEN : LPTIM4LPEN
bits : 2 - 2 (1 bit)
LPTIM5LPEN : LPTIM5LPEN
bits : 3 - 3 (1 bit)
SAI4LPEN : SAI4LPEN
bits : 8 - 8 (1 bit)
SYSCFGLPEN : SYSCFGLPEN
bits : 11 - 11 (1 bit)
VREFLPEN : VREFLPEN
bits : 13 - 13 (1 bit)
DTSLPEN : DTSLPEN
bits : 16 - 16 (1 bit)
This register is used by the MCU in order to set the PERxLPEN bit.
address_offset : 0xB98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1LPEN : DMA1LPEN
bits : 0 - 0 (1 bit)
DMA2LPEN : DMA2LPEN
bits : 1 - 1 (1 bit)
DMAMUXLPEN : DMAMUXLPEN
bits : 2 - 2 (1 bit)
ADC12LPEN : ADC12LPEN
bits : 5 - 5 (1 bit)
USBOLPEN : USBOLPEN
bits : 8 - 8 (1 bit)
SDMMC3LPEN : SDMMC3LPEN
bits : 16 - 16 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bit
address_offset : 0xB9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1LPEN : DMA1LPEN
bits : 0 - 0 (1 bit)
DMA2LPEN : DMA2LPEN
bits : 1 - 1 (1 bit)
DMAMUXLPEN : DMAMUXLPEN
bits : 2 - 2 (1 bit)
ADC12LPEN : ADC12LPEN
bits : 5 - 5 (1 bit)
USBOLPEN : USBOLPEN
bits : 8 - 8 (1 bit)
SDMMC3LPEN : SDMMC3LPEN
bits : 16 - 16 (1 bit)
This register is used by the MCU in order to set the PERxLPEN bit.
address_offset : 0xBA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMILPEN : DCMILPEN
bits : 0 - 0 (1 bit)
CRYP2LPEN : CRYP2LPEN
bits : 4 - 4 (1 bit)
HASH2LPEN : HASH2LPEN
bits : 5 - 5 (1 bit)
RNG2LPEN : RNG2LPEN
bits : 6 - 6 (1 bit)
CRC2LPEN : CRC2LPEN
bits : 7 - 7 (1 bit)
HSEMLPEN : HSEMLPEN
bits : 11 - 11 (1 bit)
IPCCLPEN : IPCCLPEN
bits : 12 - 12 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bit
address_offset : 0xBA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCMILPEN : DCMILPEN
bits : 0 - 0 (1 bit)
CRYP2LPEN : CRYP2LPEN
bits : 4 - 4 (1 bit)
HASH2LPEN : HASH2LPEN
bits : 5 - 5 (1 bit)
RNG2LPEN : RNG2LPEN
bits : 6 - 6 (1 bit)
CRC2LPEN : CRC2LPEN
bits : 7 - 7 (1 bit)
HSEMLPEN : HSEMLPEN
bits : 11 - 11 (1 bit)
IPCCLPEN : IPCCLPEN
bits : 12 - 12 (1 bit)
This register is used by the MCU in order to set the PERxLPEN bit.
address_offset : 0xBA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOALPEN : GPIOALPEN
bits : 0 - 0 (1 bit)
GPIOBLPEN : GPIOBLPEN
bits : 1 - 1 (1 bit)
GPIOCLPEN : GPIOCLPEN
bits : 2 - 2 (1 bit)
GPIODLPEN : GPIODLPEN
bits : 3 - 3 (1 bit)
GPIOELPEN : GPIOELPEN
bits : 4 - 4 (1 bit)
GPIOFLPEN : GPIOFLPEN
bits : 5 - 5 (1 bit)
GPIOGLPEN : GPIOGLPEN
bits : 6 - 6 (1 bit)
GPIOHLPEN : GPIOHLPEN
bits : 7 - 7 (1 bit)
GPIOILPEN : GPIOILPEN
bits : 8 - 8 (1 bit)
GPIOJLPEN : GPIOJLPEN
bits : 9 - 9 (1 bit)
GPIOKLPEN : GPIOKLPEN
bits : 10 - 10 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral.
address_offset : 0xBAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOALPEN : GPIOALPEN
bits : 0 - 0 (1 bit)
GPIOBLPEN : GPIOBLPEN
bits : 1 - 1 (1 bit)
GPIOCLPEN : GPIOCLPEN
bits : 2 - 2 (1 bit)
GPIODLPEN : GPIODLPEN
bits : 3 - 3 (1 bit)
GPIOELPEN : GPIOELPEN
bits : 4 - 4 (1 bit)
GPIOFLPEN : GPIOFLPEN
bits : 5 - 5 (1 bit)
GPIOGLPEN : GPIOGLPEN
bits : 6 - 6 (1 bit)
GPIOHLPEN : GPIOHLPEN
bits : 7 - 7 (1 bit)
GPIOILPEN : GPIOILPEN
bits : 8 - 8 (1 bit)
GPIOJLPEN : GPIOJLPEN
bits : 9 - 9 (1 bit)
GPIOKLPEN : GPIOKLPEN
bits : 10 - 10 (1 bit)
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral.
address_offset : 0xBB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSRAMLPEN : SYSRAMLPEN
bits : 0 - 0 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral.
address_offset : 0xBB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSRAMLPEN : SYSRAMLPEN
bits : 0 - 0 (1 bit)
This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral.
address_offset : 0xBB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM1LPEN : SRAM1LPEN
bits : 0 - 0 (1 bit)
SRAM2LPEN : SRAM2LPEN
bits : 1 - 1 (1 bit)
SRAM34LPEN : SRAM34LPEN
bits : 2 - 2 (1 bit)
RETRAMLPEN : RETRAMLPEN
bits : 4 - 4 (1 bit)
This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral.
address_offset : 0xBBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM1LPEN : SRAM1LPEN
bits : 0 - 0 (1 bit)
SRAM2LPEN : SRAM2LPEN
bits : 1 - 1 (1 bit)
SRAM34LPEN : SRAM34LPEN
bits : 2 - 2 (1 bit)
RETRAMLPEN : RETRAMLPEN
bits : 4 - 4 (1 bit)
This register is used to control the oscillators.Writing to this register has no effect, writing will set the corresponding bits. Reading will give the effective values of each bit.If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSION : HSION
bits : 0 - 0 (1 bit)
HSIKERON : HSIKERON
bits : 1 - 1 (1 bit)
CSION : CSION
bits : 4 - 4 (1 bit)
CSIKERON : CSIKERON
bits : 5 - 5 (1 bit)
DIGBYP : DIGBYP
bits : 7 - 7 (1 bit)
HSEON : HSEON
bits : 8 - 8 (1 bit)
HSEKERON : HSEKERON
bits : 9 - 9 (1 bit)
HSEBYP : HSEBYP
bits : 10 - 10 (1 bit)
HSECSSON : HSECSSON
bits : 11 - 11 (1 bit)
This register is used to control the selection of the kernel clock for the I2C4 and I2C6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C46SRC : I2C46SRC
bits : 0 - 2 (3 bit)
This register is used by the MCU to check the reset source.
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORRSTF : PORRSTF
bits : 0 - 0 (1 bit)
BORRSTF : BORRSTF
bits : 1 - 1 (1 bit)
PADRSTF : PADRSTF
bits : 2 - 2 (1 bit)
HCSSRSTF : HCSSRSTF
bits : 3 - 3 (1 bit)
VCORERSTF : VCORERSTF
bits : 4 - 4 (1 bit)
MCURSTF : MCURSTF
bits : 5 - 5 (1 bit)
MPSYSRSTF : MPSYSRSTF
bits : 6 - 6 (1 bit)
MCSYSRSTF : MCSYSRSTF
bits : 7 - 7 (1 bit)
IWDG1RSTF : IWDG1RSTF
bits : 8 - 8 (1 bit)
IWDG2RSTF : IWDG2RSTF
bits : 9 - 9 (1 bit)
WWDG1RSTF : WWDG1RSTF
bits : 10 - 10 (1 bit)
This register shall be used by the MCU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details.
address_offset : 0xC14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSIRDYIE : LSIRDYIE
bits : 0 - 0 (1 bit)
LSERDYIE : LSERDYIE
bits : 1 - 1 (1 bit)
HSIRDYIE : HSIRDYIE
bits : 2 - 2 (1 bit)
HSERDYIE : HSERDYIE
bits : 3 - 3 (1 bit)
CSIRDYIE : CSIRDYIE
bits : 4 - 4 (1 bit)
PLL1DYIE : PLL1DYIE
bits : 8 - 8 (1 bit)
PLL2DYIE : PLL2DYIE
bits : 9 - 9 (1 bit)
PLL3DYIE : PLL3DYIE
bits : 10 - 10 (1 bit)
PLL4DYIE : PLL4DYIE
bits : 11 - 11 (1 bit)
LSECSSIE : LSECSSIE
bits : 16 - 16 (1 bit)
WKUPIE : WKUPIE
bits : 20 - 20 (1 bit)
This register shall be used by the MCU in order to read and clear the interrupt flags.
address_offset : 0xC18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSIRDYF : LSIRDYF
bits : 0 - 0 (1 bit)
LSERDYF : LSERDYF
bits : 1 - 1 (1 bit)
HSIRDYF : HSIRDYF
bits : 2 - 2 (1 bit)
HSERDYF : HSERDYF
bits : 3 - 3 (1 bit)
CSIRDYF : CSIRDYF
bits : 4 - 4 (1 bit)
PLL1DYF : PLL1DYF
bits : 8 - 8 (1 bit)
PLL2DYF : PLL2DYF
bits : 9 - 9 (1 bit)
PLL3DYF : PLL3DYF
bits : 10 - 10 (1 bit)
PLL4DYF : PLL4DYF
bits : 11 - 11 (1 bit)
LSECSSF : LSECSSF
bits : 16 - 16 (1 bit)
WKUPF : WKUPF
bits : 20 - 20 (1 bit)
This register is used to control the selection of the kernel clock for the SPI6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI6SRC : SPI6SRC
bits : 0 - 2 (3 bit)
This register is used to control the selection of the kernel clock for the USART1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART1SRC : UART1SRC
bits : 0 - 2 (3 bit)
This register is used to control the selection of the kernel clock for the RNG1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RNG1SRC : RNG1SRC
bits : 0 - 1 (2 bit)
This register is used to select an oscillator source as kernel clock for the per_ck clock. The per_ck clock is distributed to several peripherals. Refer to Section: Clock enabling delays.
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKPERSRC : CKPERSRC
bits : 0 - 1 (2 bit)
This register is used to select the peripheral clock for the STGEN block. Note that this clock is used to provide a time reference for the application. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STGENSRC : STGENSRC
bits : 0 - 1 (2 bit)
This register is used to control the DDR interface, including the DDRC and DDRPHYC. If TZEN = , this register can only be modified in secure mode.
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DDRC1EN : DDRC1EN
bits : 0 - 0 (1 bit)
DDRC1LPEN : DDRC1LPEN
bits : 1 - 1 (1 bit)
DDRC2EN : DDRC2EN
bits : 2 - 2 (1 bit)
DDRC2LPEN : DDRC2LPEN
bits : 3 - 3 (1 bit)
DDRPHYCEN : DDRPHYCEN
bits : 4 - 4 (1 bit)
DDRPHYCLPEN : DDRPHYCLPEN
bits : 5 - 5 (1 bit)
DDRCAPBEN : DDRCAPBEN
bits : 6 - 6 (1 bit)
DDRCAPBLPEN : DDRCAPBLPEN
bits : 7 - 7 (1 bit)
AXIDCGEN : AXIDCGEN
bits : 8 - 8 (1 bit)
DDRPHYCAPBEN : DDRPHYCAPBEN
bits : 9 - 9 (1 bit)
DDRPHYCAPBLPEN : DDRPHYCAPBLPEN
bits : 10 - 10 (1 bit)
KERDCG_DLY : KERDCG_DLY
bits : 11 - 13 (3 bit)
DDRCAPBRST : DDRCAPBRST
bits : 14 - 14 (1 bit)
DDRCAXIRST : DDRCAXIRST
bits : 15 - 15 (1 bit)
DDRCORERST : DDRCORERST
bits : 16 - 16 (1 bit)
DPHYAPBRST : DPHYAPBRST
bits : 17 - 17 (1 bit)
DPHYRST : DPHYRST
bits : 18 - 18 (1 bit)
DPHYCTLRST : DPHYCTLRST
bits : 19 - 19 (1 bit)
DDRCKMOD : DDRCKMOD
bits : 20 - 22 (3 bit)
GSKPMOD : GSKPMOD
bits : 23 - 23 (1 bit)
GSKPCTRL : GSKPCTRL
bits : 24 - 24 (1 bit)
DFILP_WIDTH : DFILP_WIDTH
bits : 25 - 27 (3 bit)
GSKP_DUR : GSKP_DUR
bits : 28 - 31 (4 bit)
This register gives the IP version
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINREV : MINREV
bits : 0 - 3 (4 bit)
MAJREV : MAJREV
bits : 4 - 7 (4 bit)
This register gives the unique identifier of the RCC
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : ID
bits : 0 - 31 (32 bit)
This register gives the decoding space, which is for the RCC of 4 kB.
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SID : SID
bits : 0 - 31 (32 bit)
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