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EXTI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

RTSR1

FPR1

SECCFGR1

PRIVCFGR1

FTSR1

EXTICR1

EXTICR2

EXTICR3

EXTICR4

LOCKR

SWIER1

IMR1

EMR1

RPR1


RTSR1

EXTI rising trigger selection register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTSR1 RTSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RT0 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT17 RT18 RT19 RT20 RT21 RT22

RT0 : Rising trigger event configuration bit of configurable event input x
bits : 0 - 0 (1 bit)

RT1 : Rising trigger event configuration bit of configurable event input x
bits : 1 - 1 (1 bit)

RT2 : Rising trigger event configuration bit of configurable event input x
bits : 2 - 2 (1 bit)

RT3 : Rising trigger event configuration bit of configurable event input x
bits : 3 - 3 (1 bit)

RT4 : Rising trigger event configuration bit of configurable event input x
bits : 4 - 4 (1 bit)

RT5 : Rising trigger event configuration bit of configurable event input x
bits : 5 - 5 (1 bit)

RT6 : Rising trigger event configuration bit of configurable event input x
bits : 6 - 6 (1 bit)

RT7 : Rising trigger event configuration bit of configurable event input x
bits : 7 - 7 (1 bit)

RT8 : Rising trigger event configuration bit of configurable event input x
bits : 8 - 8 (1 bit)

RT9 : Rising trigger event configuration bit of configurable event input x
bits : 9 - 9 (1 bit)

RT10 : Rising trigger event configuration bit of configurable event input x
bits : 10 - 10 (1 bit)

RT11 : Rising trigger event configuration bit of configurable event input x
bits : 11 - 11 (1 bit)

RT12 : Rising trigger event configuration bit of configurable event input x
bits : 12 - 12 (1 bit)

RT13 : Rising trigger event configuration bit of configurable event input x
bits : 13 - 13 (1 bit)

RT14 : Rising trigger event configuration bit of configurable event input x
bits : 14 - 14 (1 bit)

RT15 : Rising trigger event configuration bit of configurable event input x
bits : 15 - 15 (1 bit)

RT16 : Rising trigger event configuration bit of configurable event input x
bits : 16 - 16 (1 bit)

RT17 : Rising trigger event configuration bit of configurable event input x
bits : 17 - 17 (1 bit)

RT18 : Rising trigger event configuration bit of configurable event input x
bits : 18 - 18 (1 bit)

RT19 : Rising trigger event configuration bit of configurable event input x
bits : 19 - 19 (1 bit)

RT20 : Rising trigger event configuration bit of configurable event input x
bits : 20 - 20 (1 bit)

RT21 : Rising trigger event configuration bit of configurable event input x
bits : 21 - 21 (1 bit)

RT22 : Rising trigger event configuration bit of configurable event input x
bits : 22 - 22 (1 bit)


FPR1

EXTI falling edge pending register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPR1 FPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPIF0 FPIF1 FPIF2 FPIF3 FPIF4 FPIF5 FPIF6 FPIF7 FPIF8 FPIF9 FPIF10 FPIF11 FPIF12 FPIF13 FPIF14 FPIF15 FPIF16 FPIF17 FPIF18 FPIF19 FPIF20 FPIF21 FPIF22

FPIF0 : configurable event inputs x falling edge pending bit.
bits : 0 - 0 (1 bit)

FPIF1 : configurable event inputs x falling edge pending bit.
bits : 1 - 1 (1 bit)

FPIF2 : configurable event inputs x falling edge pending bit.
bits : 2 - 2 (1 bit)

FPIF3 : configurable event inputs x falling edge pending bit.
bits : 3 - 3 (1 bit)

FPIF4 : configurable event inputs x falling edge pending bit.
bits : 4 - 4 (1 bit)

FPIF5 : configurable event inputs x falling edge pending bit.
bits : 5 - 5 (1 bit)

FPIF6 : configurable event inputs x falling edge pending bit.
bits : 6 - 6 (1 bit)

FPIF7 : configurable event inputs x falling edge pending bit.
bits : 7 - 7 (1 bit)

FPIF8 : configurable event inputs x falling edge pending bit.
bits : 8 - 8 (1 bit)

FPIF9 : configurable event inputs x falling edge pending bit.
bits : 9 - 9 (1 bit)

FPIF10 : configurable event inputs x falling edge pending bit.
bits : 10 - 10 (1 bit)

FPIF11 : configurable event inputs x falling edge pending bit.
bits : 11 - 11 (1 bit)

FPIF12 : configurable event inputs x falling edge pending bit.
bits : 12 - 12 (1 bit)

FPIF13 : configurable event inputs x falling edge pending bit.
bits : 13 - 13 (1 bit)

FPIF14 : configurable event inputs x falling edge pending bit.
bits : 14 - 14 (1 bit)

FPIF15 : configurable event inputs x falling edge pending bit.
bits : 15 - 15 (1 bit)

FPIF16 : configurable event inputs x falling edge pending bit.
bits : 16 - 16 (1 bit)

FPIF17 : configurable event inputs x falling edge pending bit.
bits : 17 - 17 (1 bit)

FPIF18 : configurable event inputs x falling edge pending bit.
bits : 18 - 18 (1 bit)

FPIF19 : configurable event inputs x falling edge pending bit.
bits : 19 - 19 (1 bit)

FPIF20 : configurable event inputs x falling edge pending bit.
bits : 20 - 20 (1 bit)

FPIF21 : configurable event inputs x falling edge pending bit.
bits : 21 - 21 (1 bit)

FPIF22 : configurable event inputs x falling edge pending bit.
bits : 22 - 22 (1 bit)


SECCFGR1

EXTI security configuration register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECCFGR1 SECCFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEC0 SEC1 SEC2 SEC3 SEC4 SEC5 SEC6 SEC7 SEC8 SEC9 SEC10 SEC11 SEC12 SEC13 SEC14 SEC15 SEC16 SEC17 SEC18 SEC19 SEC20 SEC21 SEC22

SEC0 : Security enable on event input x
bits : 0 - 0 (1 bit)

SEC1 : Security enable on event input x
bits : 1 - 1 (1 bit)

SEC2 : Security enable on event input x
bits : 2 - 2 (1 bit)

SEC3 : Security enable on event input x
bits : 3 - 3 (1 bit)

SEC4 : Security enable on event input x
bits : 4 - 4 (1 bit)

SEC5 : Security enable on event input x
bits : 5 - 5 (1 bit)

SEC6 : Security enable on event input x
bits : 6 - 6 (1 bit)

SEC7 : Security enable on event input x
bits : 7 - 7 (1 bit)

SEC8 : Security enable on event input x
bits : 8 - 8 (1 bit)

SEC9 : Security enable on event input x
bits : 9 - 9 (1 bit)

SEC10 : Security enable on event input x
bits : 10 - 10 (1 bit)

SEC11 : Security enable on event input x
bits : 11 - 11 (1 bit)

SEC12 : Security enable on event input x
bits : 12 - 12 (1 bit)

SEC13 : Security enable on event input x
bits : 13 - 13 (1 bit)

SEC14 : Security enable on event input x
bits : 14 - 14 (1 bit)

SEC15 : Security enable on event input x
bits : 15 - 15 (1 bit)

SEC16 : Security enable on event input x
bits : 16 - 16 (1 bit)

SEC17 : Security enable on event input x
bits : 17 - 17 (1 bit)

SEC18 : Security enable on event input x
bits : 18 - 18 (1 bit)

SEC19 : Security enable on event input x
bits : 19 - 19 (1 bit)

SEC20 : Security enable on event input x
bits : 20 - 20 (1 bit)

SEC21 : Security enable on event input x
bits : 21 - 21 (1 bit)

SEC22 : Security enable on event input x
bits : 22 - 22 (1 bit)


PRIVCFGR1

EXTI privilege configuration register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRIVCFGR1 PRIVCFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIV0 PRIV1 PRIV2 PRIV3 PRIV4 PRIV5 PRIV6 PRIV7 PRIV8 PRIV9 PRIV10 PRIV11 PRIV12 PRIV13 PRIV14 PRIV15 PRIV16 PRIV17 PRIV18 PRIV19 PRIV20 PRIV21 PRIV22

PRIV0 : Security enable on event input x
bits : 0 - 0 (1 bit)

PRIV1 : Security enable on event input x
bits : 1 - 1 (1 bit)

PRIV2 : Security enable on event input x
bits : 2 - 2 (1 bit)

PRIV3 : Security enable on event input x
bits : 3 - 3 (1 bit)

PRIV4 : Security enable on event input x
bits : 4 - 4 (1 bit)

PRIV5 : Security enable on event input x
bits : 5 - 5 (1 bit)

PRIV6 : Security enable on event input x
bits : 6 - 6 (1 bit)

PRIV7 : Security enable on event input x
bits : 7 - 7 (1 bit)

PRIV8 : Security enable on event input x
bits : 8 - 8 (1 bit)

PRIV9 : Security enable on event input x
bits : 9 - 9 (1 bit)

PRIV10 : Security enable on event input x
bits : 10 - 10 (1 bit)

PRIV11 : Security enable on event input x
bits : 11 - 11 (1 bit)

PRIV12 : Security enable on event input x
bits : 12 - 12 (1 bit)

PRIV13 : Security enable on event input x
bits : 13 - 13 (1 bit)

PRIV14 : Security enable on event input x
bits : 14 - 14 (1 bit)

PRIV15 : Security enable on event input x
bits : 15 - 15 (1 bit)

PRIV16 : Security enable on event input x
bits : 16 - 16 (1 bit)

PRIV17 : Security enable on event input x
bits : 17 - 17 (1 bit)

PRIV18 : Security enable on event input x
bits : 18 - 18 (1 bit)

PRIV19 : Security enable on event input x
bits : 19 - 19 (1 bit)

PRIV20 : Security enable on event input x
bits : 20 - 20 (1 bit)

PRIV21 : Security enable on event input x
bits : 21 - 21 (1 bit)

PRIV22 : Security enable on event input x
bits : 22 - 22 (1 bit)


FTSR1

EXTI falling trigger selection register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FTSR1 FTSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FT8 FT9 FT10 FT11 FT12 FT13 FT14 FT15 FT16 FT17 FT18 FT19 FT20 FT21 FT22

FT0 : Falling trigger event configuration bit of configurable event input x
bits : 0 - 0 (1 bit)

FT1 : Falling trigger event configuration bit of configurable event input x
bits : 1 - 1 (1 bit)

FT2 : Falling trigger event configuration bit of configurable event input x
bits : 2 - 2 (1 bit)

FT3 : Falling trigger event configuration bit of configurable event input x
bits : 3 - 3 (1 bit)

FT4 : Falling trigger event configuration bit of configurable event input x
bits : 4 - 4 (1 bit)

FT5 : Falling trigger event configuration bit of configurable event input x
bits : 5 - 5 (1 bit)

FT6 : Falling trigger event configuration bit of configurable event input x
bits : 6 - 6 (1 bit)

FT7 : Falling trigger event configuration bit of configurable event input x
bits : 7 - 7 (1 bit)

FT8 : Falling trigger event configuration bit of configurable event input x
bits : 8 - 8 (1 bit)

FT9 : Falling trigger event configuration bit of configurable event input x
bits : 9 - 9 (1 bit)

FT10 : Falling trigger event configuration bit of configurable event input x
bits : 10 - 10 (1 bit)

FT11 : Falling trigger event configuration bit of configurable event input x
bits : 11 - 11 (1 bit)

FT12 : Falling trigger event configuration bit of configurable event input x
bits : 12 - 12 (1 bit)

FT13 : Falling trigger event configuration bit of configurable event input x
bits : 13 - 13 (1 bit)

FT14 : Falling trigger event configuration bit of configurable event input x
bits : 14 - 14 (1 bit)

FT15 : Falling trigger event configuration bit of configurable event input x
bits : 15 - 15 (1 bit)

FT16 : Falling trigger event configuration bit of configurable event input x
bits : 16 - 16 (1 bit)

FT17 : Falling trigger event configuration bit of configurable event input x
bits : 17 - 17 (1 bit)

FT18 : Falling trigger event configuration bit of configurable event input x
bits : 18 - 18 (1 bit)

FT19 : Falling trigger event configuration bit of configurable event input x
bits : 19 - 19 (1 bit)

FT20 : Falling trigger event configuration bit of configurable event input x
bits : 20 - 20 (1 bit)

FT21 : Falling trigger event configuration bit of configurable event input x
bits : 21 - 21 (1 bit)

FT22 : Falling trigger event configuration bit of configurable event input x
bits : 22 - 22 (1 bit)


EXTICR1

EXTI external interrupt selection register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR1 EXTICR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0_7 EXTI8_15 EXTI16_23 EXTI24_31

EXTI0_7 : EXTIm GPIO port selection
bits : 0 - 7 (8 bit)

EXTI8_15 : EXTIm+1 GPIO port selection
bits : 8 - 15 (8 bit)

EXTI16_23 : EXTIm+2 GPIO port selection
bits : 16 - 23 (8 bit)

EXTI24_31 : EXTIm+3 GPIO port selection
bits : 24 - 31 (8 bit)


EXTICR2

EXTI external interrupt selection register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR2 EXTICR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0_7 EXTI8_15 EXTI16_23 EXTI24_31

EXTI0_7 : EXTIm GPIO port selection
bits : 0 - 7 (8 bit)

EXTI8_15 : EXTIm+1 GPIO port selection
bits : 8 - 15 (8 bit)

EXTI16_23 : EXTIm+2 GPIO port selection
bits : 16 - 23 (8 bit)

EXTI24_31 : EXTIm+3 GPIO port selection
bits : 24 - 31 (8 bit)


EXTICR3

EXTI external interrupt selection register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR3 EXTICR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0_7 EXTI8_15 EXTI16_23 EXTI24_31

EXTI0_7 : EXTIm GPIO port selection
bits : 0 - 7 (8 bit)

EXTI8_15 : EXTIm+1 GPIO port selection
bits : 8 - 15 (8 bit)

EXTI16_23 : EXTIm+2 GPIO port selection
bits : 16 - 23 (8 bit)

EXTI24_31 : EXTIm+3 GPIO port selection
bits : 24 - 31 (8 bit)


EXTICR4

EXTI external interrupt selection register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR4 EXTICR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0_7 EXTI8_15 EXTI16_23 EXTI24_31

EXTI0_7 : EXTIm GPIO port selection
bits : 0 - 7 (8 bit)

EXTI8_15 : EXTIm+1 GPIO port selection
bits : 8 - 15 (8 bit)

EXTI16_23 : EXTIm+2 GPIO port selection
bits : 16 - 23 (8 bit)

EXTI24_31 : EXTIm+3 GPIO port selection
bits : 24 - 31 (8 bit)


LOCKR

EXTI lock register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCKR LOCKR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK

LOCK : LOCK
bits : 0 - 0 (1 bit)


SWIER1

EXTI software interrupt event register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWIER1 SWIER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWI0 SWI1 SWI2 SWI3 SWI4 SWI5 SWI6 SWI7 SWI8 SWI9 SWI10 SWI11 SWI12 SWI13 SWI14 SWI15 SWI16 SWI17 SWI18 SWI19 SWI20 SWI21 SWI22

SWI0 : Software interrupt on event x
bits : 0 - 0 (1 bit)

SWI1 : Software interrupt on event x
bits : 1 - 1 (1 bit)

SWI2 : Software interrupt on event x
bits : 2 - 2 (1 bit)

SWI3 : Software interrupt on event x
bits : 3 - 3 (1 bit)

SWI4 : Software interrupt on event x
bits : 4 - 4 (1 bit)

SWI5 : Software interrupt on event x
bits : 5 - 5 (1 bit)

SWI6 : Software interrupt on event x
bits : 6 - 6 (1 bit)

SWI7 : Software interrupt on event x
bits : 7 - 7 (1 bit)

SWI8 : Software interrupt on event x
bits : 8 - 8 (1 bit)

SWI9 : Software interrupt on event x
bits : 9 - 9 (1 bit)

SWI10 : Software interrupt on event x
bits : 10 - 10 (1 bit)

SWI11 : Software interrupt on event x
bits : 11 - 11 (1 bit)

SWI12 : Software interrupt on event x
bits : 12 - 12 (1 bit)

SWI13 : Software interrupt on event x
bits : 13 - 13 (1 bit)

SWI14 : Software interrupt on event x
bits : 14 - 14 (1 bit)

SWI15 : Software interrupt on event x
bits : 15 - 15 (1 bit)

SWI16 : Software interrupt on event x
bits : 16 - 16 (1 bit)

SWI17 : Software interrupt on event x
bits : 17 - 17 (1 bit)

SWI18 : Software interrupt on event x
bits : 18 - 18 (1 bit)

SWI19 : Software interrupt on event x
bits : 19 - 19 (1 bit)

SWI20 : Software interrupt on event x
bits : 20 - 20 (1 bit)

SWI21 : Software interrupt on event x
bits : 21 - 21 (1 bit)

SWI22 : Software interrupt on event x
bits : 22 - 22 (1 bit)


IMR1

EXTI CPU wakeup with interrupt mask register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMR1 IMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IM0 IM1 IM2 IM3 IM4 IM5 IM6 IM7 IM8 IM9 IM10 IM11 IM12 IM13 IM14 IM15 IM16 IM17 IM18 IM19 IM20 IM21 IM22

IM0 : CPU wakeup with interrupt mask on event input
bits : 0 - 0 (1 bit)

IM1 : CPU wakeup with interrupt mask on event input
bits : 1 - 1 (1 bit)

IM2 : CPU wakeup with interrupt mask on event input
bits : 2 - 2 (1 bit)

IM3 : CPU wakeup with interrupt mask on event input
bits : 3 - 3 (1 bit)

IM4 : CPU wakeup with interrupt mask on event input
bits : 4 - 4 (1 bit)

IM5 : CPU wakeup with interrupt mask on event input
bits : 5 - 5 (1 bit)

IM6 : CPU wakeup with interrupt mask on event input
bits : 6 - 6 (1 bit)

IM7 : CPU wakeup with interrupt mask on event input
bits : 7 - 7 (1 bit)

IM8 : CPU wakeup with interrupt mask on event input
bits : 8 - 8 (1 bit)

IM9 : CPU wakeup with interrupt mask on event input
bits : 9 - 9 (1 bit)

IM10 : CPU wakeup with interrupt mask on event input
bits : 10 - 10 (1 bit)

IM11 : CPU wakeup with interrupt mask on event input
bits : 11 - 11 (1 bit)

IM12 : CPU wakeup with interrupt mask on event input
bits : 12 - 12 (1 bit)

IM13 : CPU wakeup with interrupt mask on event input
bits : 13 - 13 (1 bit)

IM14 : CPU wakeup with interrupt mask on event input
bits : 14 - 14 (1 bit)

IM15 : CPU wakeup with interrupt mask on event input
bits : 15 - 15 (1 bit)

IM16 : CPU wakeup with interrupt mask on event input
bits : 16 - 16 (1 bit)

IM17 : CPU wakeup with interrupt mask on event input
bits : 17 - 17 (1 bit)

IM18 : CPU wakeup with interrupt mask on event input
bits : 18 - 18 (1 bit)

IM19 : CPU wakeup with interrupt mask on event input
bits : 19 - 19 (1 bit)

IM20 : CPU wakeup with interrupt mask on event input
bits : 20 - 20 (1 bit)

IM21 : CPU wakeup with interrupt mask on event input
bits : 21 - 21 (1 bit)

IM22 : CPU wakeup with interrupt mask on event input
bits : 22 - 22 (1 bit)


EMR1

EXTI CPU wakeup with event mask register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EMR1 EMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM0 EM1 EM2 EM3 EM4 EM5 EM6 EM7 EM8 EM9 EM10 EM11 EM12 EM13 EM14 EM15 EM16 EM17 EM18 EM19 EM20 EM21 EM22

EM0 : CPU wakeup with event generation mask on event input
bits : 0 - 0 (1 bit)

EM1 : CPU wakeup with event generation mask on event input
bits : 1 - 1 (1 bit)

EM2 : CPU wakeup with event generation mask on event input
bits : 2 - 2 (1 bit)

EM3 : CPU wakeup with event generation mask on event input
bits : 3 - 3 (1 bit)

EM4 : CPU wakeup with event generation mask on event input
bits : 4 - 4 (1 bit)

EM5 : CPU wakeup with event generation mask on event input
bits : 5 - 5 (1 bit)

EM6 : CPU wakeup with event generation mask on event input
bits : 6 - 6 (1 bit)

EM7 : CPU wakeup with event generation mask on event input
bits : 7 - 7 (1 bit)

EM8 : CPU wakeup with event generation mask on event input
bits : 8 - 8 (1 bit)

EM9 : CPU wakeup with event generation mask on event input
bits : 9 - 9 (1 bit)

EM10 : CPU wakeup with event generation mask on event input
bits : 10 - 10 (1 bit)

EM11 : CPU wakeup with event generation mask on event input
bits : 11 - 11 (1 bit)

EM12 : CPU wakeup with event generation mask on event input
bits : 12 - 12 (1 bit)

EM13 : CPU wakeup with event generation mask on event input
bits : 13 - 13 (1 bit)

EM14 : CPU wakeup with event generation mask on event input
bits : 14 - 14 (1 bit)

EM15 : CPU wakeup with event generation mask on event input
bits : 15 - 15 (1 bit)

EM16 : CPU wakeup with event generation mask on event input
bits : 16 - 16 (1 bit)

EM17 : CPU wakeup with event generation mask on event input
bits : 17 - 17 (1 bit)

EM18 : CPU wakeup with event generation mask on event input
bits : 18 - 18 (1 bit)

EM19 : CPU wakeup with event generation mask on event input
bits : 19 - 19 (1 bit)

EM20 : CPU wakeup with event generation mask on event input
bits : 20 - 20 (1 bit)

EM21 : CPU wakeup with event generation mask on event input
bits : 21 - 21 (1 bit)

EM22 : CPU wakeup with event generation mask on event input
bits : 22 - 22 (1 bit)


RPR1

EXTI rising edge pending register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPR1 RPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPIF0 RPIF1 RPIF2 RPIF3 RPIF4 RPIF5 RPIF6 RPIF7 RPIF8 RPIF9 RPIF10 RPIF11 RPIF12 RPIF13 RPIF14 RPIF15 RPIF16 RPIF17 RPIF18 RPIF19 RPIF20 RPIF21 RPIF22

RPIF0 : configurable event inputs x rising edge pending bit
bits : 0 - 0 (1 bit)

RPIF1 : configurable event inputs x rising edge pending bit
bits : 1 - 1 (1 bit)

RPIF2 : configurable event inputs x rising edge pending bit
bits : 2 - 2 (1 bit)

RPIF3 : configurable event inputs x rising edge pending bit
bits : 3 - 3 (1 bit)

RPIF4 : configurable event inputs x rising edge pending bit
bits : 4 - 4 (1 bit)

RPIF5 : configurable event inputs x rising edge pending bit
bits : 5 - 5 (1 bit)

RPIF6 : configurable event inputs x rising edge pending bit
bits : 6 - 6 (1 bit)

RPIF7 : configurable event inputs x rising edge pending bit
bits : 7 - 7 (1 bit)

RPIF8 : configurable event inputs x rising edge pending bit
bits : 8 - 8 (1 bit)

RPIF9 : configurable event inputs x rising edge pending bit
bits : 9 - 9 (1 bit)

RPIF10 : configurable event inputs x rising edge pending bit
bits : 10 - 10 (1 bit)

RPIF11 : configurable event inputs x rising edge pending bit
bits : 11 - 11 (1 bit)

RPIF12 : configurable event inputs x rising edge pending bit
bits : 12 - 12 (1 bit)

RPIF13 : configurable event inputs x rising edge pending bit
bits : 13 - 13 (1 bit)

RPIF14 : configurable event inputs x rising edge pending bit
bits : 14 - 14 (1 bit)

RPIF15 : configurable event inputs x rising edge pending bit
bits : 15 - 15 (1 bit)

RPIF16 : configurable event inputs x rising edge pending bit
bits : 16 - 16 (1 bit)

RPIF17 : configurable event inputs x rising edge pending bit
bits : 17 - 17 (1 bit)

RPIF18 : configurable event inputs x rising edge pending bit
bits : 18 - 18 (1 bit)

RPIF19 : configurable event inputs x rising edge pending bit
bits : 19 - 19 (1 bit)

RPIF20 : configurable event inputs x rising edge pending bit
bits : 20 - 20 (1 bit)

RPIF21 : configurable event inputs x rising edge pending bit
bits : 21 - 21 (1 bit)

RPIF22 : configurable event inputs x rising edge pending bit
bits : 22 - 22 (1 bit)



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