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DCACHE

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

DCACHE_CR (CR)

DCACHE_RHMONR (RHMONR)

DCACHE_RMMONR (RMMONR)

DCACHE_WHMONR (WHMONR)

DCACHE_WMMONR (WMMONR)

DCACHE_CMDRSADDRR (CMDRSADDRR)

DCACHE_CMDREADDRR (CMDREADDRR)

DCACHE_SR (SR)

DCACHE_IER (IER)

DCACHE_FCR (FCR)


DCACHE_CR (CR)

DCACHE control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCACHE_CR DCACHE_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN CACHEINV CACHECMD STARTCMD RHITMEN RMISSMEN RHITMRST RMISSMRST WHITMEN WMISSMEN WHITMRST WMISSMRST HBURST

EN : EN
bits : 0 - 0 (1 bit)
access : read-write

CACHEINV : CACHEINV
bits : 1 - 1 (1 bit)
access : write-only

CACHECMD : CACHECMD
bits : 8 - 10 (3 bit)
access : read-write

STARTCMD : STARTCMD
bits : 11 - 11 (1 bit)
access : write-only

RHITMEN : RHITMEN
bits : 16 - 16 (1 bit)
access : read-write

RMISSMEN : RMISSMEN
bits : 17 - 17 (1 bit)
access : read-write

RHITMRST : RHITMRST
bits : 18 - 18 (1 bit)
access : read-write

RMISSMRST : RMISSMRST
bits : 19 - 19 (1 bit)
access : read-write

WHITMEN : WHITMEN
bits : 20 - 20 (1 bit)
access : read-write

WMISSMEN : WMISSMEN
bits : 21 - 21 (1 bit)
access : read-write

WHITMRST : WHITMRST
bits : 22 - 22 (1 bit)
access : read-write

WMISSMRST : WMISSMRST
bits : 23 - 23 (1 bit)
access : read-write

HBURST : HBURST
bits : 31 - 31 (1 bit)
access : read-write


DCACHE_RHMONR (RHMONR)

DCACHE read-hit monitor register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCACHE_RHMONR DCACHE_RHMONR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RHITMON

RHITMON : RHITMON
bits : 0 - 31 (32 bit)


DCACHE_RMMONR (RMMONR)

DCACHE read-miss monitor register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCACHE_RMMONR DCACHE_RMMONR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MRISSMON

MRISSMON : RMISSMON
bits : 0 - 15 (16 bit)


DCACHE_WHMONR (WHMONR)

write-hit monitor register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCACHE_WHMONR DCACHE_WHMONR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WHITMON

WHITMON : WHITMON
bits : 0 - 31 (32 bit)


DCACHE_WMMONR (WMMONR)

write-miss monitor register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCACHE_WMMONR DCACHE_WMMONR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WMISSMON

WMISSMON : WMISSMON
bits : 0 - 15 (16 bit)


DCACHE_CMDRSADDRR (CMDRSADDRR)

command range start address register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCACHE_CMDRSADDRR DCACHE_CMDRSADDRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDSTARTADDR

CMDSTARTADDR : CMDSTARTADDR
bits : 0 - 31 (32 bit)


DCACHE_CMDREADDRR (CMDREADDRR)

command range start address register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCACHE_CMDREADDRR DCACHE_CMDREADDRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDENDADDR

CMDENDADDR : CMDENDADDR
bits : 0 - 31 (32 bit)


DCACHE_SR (SR)

DCACHE status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCACHE_SR DCACHE_SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSYF BSYENDF ERRF BUSYCMDF CMDENDF

BUSYF : BUSYF
bits : 0 - 0 (1 bit)

BSYENDF : BSYENDF
bits : 1 - 1 (1 bit)

ERRF : ERRF
bits : 2 - 2 (1 bit)

BUSYCMDF : BUSYCMDF
bits : 3 - 3 (1 bit)

CMDENDF : CMDENDF
bits : 4 - 4 (1 bit)


DCACHE_IER (IER)

DCACHE interrupt enable register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCACHE_IER DCACHE_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BSYENDIE ERRIE CMDENDIE

BSYENDIE : BSYENDIE
bits : 1 - 1 (1 bit)

ERRIE : ERRIE
bits : 2 - 2 (1 bit)

CMDENDIE : CMDENDIE
bits : 4 - 4 (1 bit)


DCACHE_FCR (FCR)

DCACHE flag clear register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DCACHE_FCR DCACHE_FCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CBSYENDF CERRF CCMDENDF

CBSYENDF : CBSYENDF
bits : 1 - 1 (1 bit)

CERRF : CERRF
bits : 2 - 2 (1 bit)

CCMDENDF : CCMDENDF
bits : 4 - 4 (1 bit)



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