\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
DCACHE control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
CACHEINV : CACHEINV
bits : 1 - 1 (1 bit)
access : write-only
CACHECMD : CACHECMD
bits : 8 - 10 (3 bit)
access : read-write
STARTCMD : STARTCMD
bits : 11 - 11 (1 bit)
access : write-only
RHITMEN : RHITMEN
bits : 16 - 16 (1 bit)
access : read-write
RMISSMEN : RMISSMEN
bits : 17 - 17 (1 bit)
access : read-write
RHITMRST : RHITMRST
bits : 18 - 18 (1 bit)
access : read-write
RMISSMRST : RMISSMRST
bits : 19 - 19 (1 bit)
access : read-write
WHITMEN : WHITMEN
bits : 20 - 20 (1 bit)
access : read-write
WMISSMEN : WMISSMEN
bits : 21 - 21 (1 bit)
access : read-write
WHITMRST : WHITMRST
bits : 22 - 22 (1 bit)
access : read-write
WMISSMRST : WMISSMRST
bits : 23 - 23 (1 bit)
access : read-write
HBURST : HBURST
bits : 31 - 31 (1 bit)
access : read-write
DCACHE read-hit monitor register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RHITMON : RHITMON
bits : 0 - 31 (32 bit)
DCACHE read-miss monitor register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MRISSMON : RMISSMON
bits : 0 - 15 (16 bit)
write-hit monitor register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WHITMON : WHITMON
bits : 0 - 31 (32 bit)
write-miss monitor register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WMISSMON : WMISSMON
bits : 0 - 15 (16 bit)
command range start address register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDSTARTADDR : CMDSTARTADDR
bits : 0 - 31 (32 bit)
command range start address register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDENDADDR : CMDENDADDR
bits : 0 - 31 (32 bit)
DCACHE status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSYF : BUSYF
bits : 0 - 0 (1 bit)
BSYENDF : BSYENDF
bits : 1 - 1 (1 bit)
ERRF : ERRF
bits : 2 - 2 (1 bit)
BUSYCMDF : BUSYCMDF
bits : 3 - 3 (1 bit)
CMDENDF : CMDENDF
bits : 4 - 4 (1 bit)
DCACHE interrupt enable register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSYENDIE : BSYENDIE
bits : 1 - 1 (1 bit)
ERRIE : ERRIE
bits : 2 - 2 (1 bit)
CMDENDIE : CMDENDIE
bits : 4 - 4 (1 bit)
DCACHE flag clear register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CBSYENDF : CBSYENDF
bits : 1 - 1 (1 bit)
CERRF : CERRF
bits : 2 - 2 (1 bit)
CCMDENDF : CCMDENDF
bits : 4 - 4 (1 bit)
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