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LPTIM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

ISR_output

ISR_intput

CR

CCR1

ARR

CNT

CFGR2

RCR

CCMR1

CCR2

HWCFGR2

HWCFGR1

ICR_output

ICR_intput

DIER_output

DIER_intput

CFGR


ISR_output

Interrupt and Status Register (output mode)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR_output ISR_output read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1IF ARRM EXTTRIG CMP1OK ARROK UP DOWN UE REPOK CC2IF CMP2OK DIEROK

CC1IF : Compare 1 interrupt flag
bits : 0 - 0 (1 bit)

ARRM : Autoreload match
bits : 1 - 1 (1 bit)

EXTTRIG : External trigger edge event
bits : 2 - 2 (1 bit)

CMP1OK : Compare register 1 update OK
bits : 3 - 3 (1 bit)

ARROK : Autoreload register update OK
bits : 4 - 4 (1 bit)

UP : Counter direction change down to up
bits : 5 - 5 (1 bit)

DOWN : Counter direction change up to down
bits : 6 - 6 (1 bit)

UE : LPTIM update event occurred
bits : 7 - 7 (1 bit)

REPOK : Repetition register update Ok
bits : 8 - 8 (1 bit)

CC2IF : Compare 2 interrupt flag
bits : 9 - 9 (1 bit)

CMP2OK : Compare register 2 update OK
bits : 19 - 19 (1 bit)

DIEROK : Interrupt enable register update OK
bits : 24 - 24 (1 bit)


ISR_intput

Interrupt and Status Register (intput mode)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISR_output
reset_Mask : 0x0

ISR_intput ISR_intput read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1IF ARRM EXTTRIG ARROK UP DOWN UE REPOK CC2IF CC1OF CC2OF DIEROK

CC1IF : Compare 1 interrupt flag
bits : 0 - 0 (1 bit)

ARRM : Autoreload match
bits : 1 - 1 (1 bit)

EXTTRIG : External trigger edge event
bits : 2 - 2 (1 bit)

ARROK : Autoreload register update OK
bits : 4 - 4 (1 bit)

UP : Counter direction change down to up
bits : 5 - 5 (1 bit)

DOWN : Counter direction change up to down
bits : 6 - 6 (1 bit)

UE : LPTIM update event occurred
bits : 7 - 7 (1 bit)

REPOK : Repetition register update Ok
bits : 8 - 8 (1 bit)

CC2IF : Capture 2 interrupt flag
bits : 9 - 9 (1 bit)

CC1OF : Capture 1 over-capture flag
bits : 12 - 12 (1 bit)

CC2OF : Capture 2 over-capture flag
bits : 13 - 13 (1 bit)

DIEROK : Interrupt enable register update OK
bits : 24 - 24 (1 bit)


CR

Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE SNGSTRT CNTSTRT COUNTRST RSTARE

ENABLE : LPTIM Enable
bits : 0 - 0 (1 bit)

SNGSTRT : LPTIM start in single mode
bits : 1 - 1 (1 bit)

CNTSTRT : Timer start in continuous mode
bits : 2 - 2 (1 bit)

COUNTRST : Counter reset
bits : 3 - 3 (1 bit)

RSTARE : Reset after read enable
bits : 4 - 4 (1 bit)


CCR1

Compare Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR1 CCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR1

CCR1 : Capture/compare 1 value
bits : 0 - 15 (16 bit)


ARR

Autoreload Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARR ARR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR

ARR : Auto reload value
bits : 0 - 15 (16 bit)


CNT

Counter Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Counter value
bits : 0 - 15 (16 bit)


CFGR2

LPTIM configuration register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR2 CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IN1SEL IN2SEL IC1SEL IC2SEL

IN1SEL : LPTIM input 1 selection
bits : 0 - 1 (2 bit)

IN2SEL : LPTIM input 2 selection
bits : 4 - 5 (2 bit)

IC1SEL : LPTIM input capture 1 selection
bits : 16 - 17 (2 bit)

IC2SEL : LPTIM input capture 2 selection
bits : 20 - 21 (2 bit)


RCR

LPTIM repetition register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR RCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REP

REP : Repetition register value
bits : 0 - 7 (8 bit)


CCMR1

LPTIM capture/compare mode register 1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCMR1 CCMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1SEL CC1E CC1P IC1PSC IC1F CC2SEL CC2E CC2P IC2PSC IC2F

CC1SEL : Capture/compare 1 selection
bits : 0 - 0 (1 bit)

CC1E : Capture/compare 1 output enable
bits : 1 - 1 (1 bit)

CC1P : Capture/compare 1 output polarity
bits : 2 - 3 (2 bit)

IC1PSC : Input capture 1 prescaler
bits : 8 - 9 (2 bit)

IC1F : Input capture 1 filter
bits : 12 - 13 (2 bit)

CC2SEL : Capture/compare 2 selection
bits : 16 - 16 (1 bit)

CC2E : Capture/compare 2 output enable
bits : 17 - 17 (1 bit)

CC2P : Capture/compare 2 output polarity
bits : 18 - 19 (2 bit)

IC2PSC : Input capture 2 prescaler
bits : 24 - 25 (2 bit)

IC2F : Input capture 2 filter
bits : 28 - 29 (2 bit)


CCR2

LPTIM Compare Register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR2 CCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR2

CCR2 : Capture/compare 2 value
bits : 0 - 15 (16 bit)


HWCFGR2

LPTIM peripheral hardware configuration register 2
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWCFGR2 HWCFGR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG1 CFG2 CFG3

CFG1 : peripheral hardware configuration 1
bits : 0 - 3 (4 bit)

CFG2 : peripheral hardware configuration 2
bits : 8 - 15 (8 bit)

CFG3 : peripheral hardware configuration 3
bits : 16 - 16 (1 bit)


HWCFGR1

LPTIM peripheral hardware configuration register 1
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWCFGR1 HWCFGR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG1 CFG2 CFG3 CFG4

CFG1 : peripheral hardware configuration 1
bits : 0 - 7 (8 bit)

CFG2 : peripheral hardware configuration 2
bits : 8 - 15 (8 bit)

CFG3 : peripheral hardware configuration 3
bits : 16 - 19 (4 bit)

CFG4 : peripheral hardware configuration 4
bits : 24 - 31 (8 bit)


ICR_output

Interrupt Clear Register (output mode)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICR_output ICR_output write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1IF ARRMCF EXTTRIGCF CMP1OKCF ARROKCF UPCF DOWNCF UECF REPOKCF CC2CF CMP2OKCF DIEROKCF

CC1IF : Capture/compare 1 clear flag
bits : 0 - 0 (1 bit)

ARRMCF : Autoreload match Clear Flag
bits : 1 - 1 (1 bit)

EXTTRIGCF : External trigger valid edge Clear Flag
bits : 2 - 2 (1 bit)

CMP1OKCF : Compare register 1 update OK Clear Flag
bits : 3 - 3 (1 bit)

ARROKCF : Autoreload register update OK Clear Flag
bits : 4 - 4 (1 bit)

UPCF : Direction change to UP Clear Flag
bits : 5 - 5 (1 bit)

DOWNCF : Direction change to down Clear Flag
bits : 6 - 6 (1 bit)

UECF : Update event clear flag
bits : 7 - 7 (1 bit)

REPOKCF : Repetition register update OK clear flag
bits : 8 - 8 (1 bit)

CC2CF : Capture/compare 2 clear flag
bits : 9 - 9 (1 bit)

CMP2OKCF : Compare register 2 update OK clear flag
bits : 19 - 19 (1 bit)

DIEROKCF : Interrupt enable register update OK clear flag
bits : 24 - 24 (1 bit)


ICR_intput

Interrupt Clear Register (intput mode)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ICR_output
reset_Mask : 0x0

ICR_intput ICR_intput write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1IF ARRMCF EXTTRIGCF ARROKCF UPCF DOWNCF UECF REPOKCF CC2CF CC1OCF CC2OCF DIEROKCF

CC1IF : Capture/compare 1 clear flag
bits : 0 - 0 (1 bit)

ARRMCF : Autoreload match Clear Flag
bits : 1 - 1 (1 bit)

EXTTRIGCF : External trigger valid edge Clear Flag
bits : 2 - 2 (1 bit)

ARROKCF : Autoreload register update OK Clear Flag
bits : 4 - 4 (1 bit)

UPCF : Direction change to UP Clear Flag
bits : 5 - 5 (1 bit)

DOWNCF : Direction change to down Clear Flag
bits : 6 - 6 (1 bit)

UECF : Update event clear flag
bits : 7 - 7 (1 bit)

REPOKCF : Repetition register update OK clear flag
bits : 8 - 8 (1 bit)

CC2CF : Capture/compare 2 clear flag
bits : 9 - 9 (1 bit)

CC1OCF : Capture/compare 1 over-capture clear flag
bits : 12 - 12 (1 bit)

CC2OCF : Capture/compare 2 over-capture clear flag
bits : 13 - 13 (1 bit)

DIEROKCF : Interrupt enable register update OK clear flag
bits : 24 - 24 (1 bit)


DIER_output

LPTIM interrupt Enable Register (output mode)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIER_output DIER_output read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1IF ARRMIE EXTTRIGIE CMP1OKIE ARROKIE UPIE DOWNIE UEIE REPOKIE CC2IE CMP2OKIE UEDE

CC1IF : Capture/compare 1 clear flag
bits : 0 - 0 (1 bit)

ARRMIE : Autoreload match Interrupt Enable
bits : 1 - 1 (1 bit)

EXTTRIGIE : External trigger valid edge Interrupt Enable
bits : 2 - 2 (1 bit)

CMP1OKIE : Compare register 1 update OK Interrupt Enable
bits : 3 - 3 (1 bit)

ARROKIE : Autoreload register update OK Interrupt Enable
bits : 4 - 4 (1 bit)

UPIE : Direction change to UP Interrupt Enable
bits : 5 - 5 (1 bit)

DOWNIE : Direction change to down Interrupt Enable
bits : 6 - 6 (1 bit)

UEIE : Update event interrupt enable
bits : 7 - 7 (1 bit)

REPOKIE : REPOKIE
bits : 8 - 8 (1 bit)

CC2IE : Capture/compare 2 interrupt enable
bits : 9 - 9 (1 bit)

CMP2OKIE : Compare register 2 update OK interrupt enable
bits : 19 - 19 (1 bit)

UEDE : Update event DMA request enable
bits : 23 - 23 (1 bit)


DIER_intput

LPTIM interrupt Enable Register (intput mode)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DIER_output
reset_Mask : 0x0

DIER_intput DIER_intput read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1IF ARRMIE EXTTRIGIE ARROKIE UPIE DOWNIE UEIE REPOKIE CC2IE CC1OIE CC2OIE CC1DE CC2DE

CC1IF : Capture/compare 1 clear flag
bits : 0 - 0 (1 bit)

ARRMIE : Autoreload match Interrupt Enable
bits : 1 - 1 (1 bit)

EXTTRIGIE : External trigger valid edge Interrupt Enable
bits : 2 - 2 (1 bit)

ARROKIE : Autoreload register update OK Interrupt Enable
bits : 4 - 4 (1 bit)

UPIE : Direction change to UP Interrupt Enable
bits : 5 - 5 (1 bit)

DOWNIE : Direction change to down Interrupt Enable
bits : 6 - 6 (1 bit)

UEIE : Update event interrupt enable
bits : 7 - 7 (1 bit)

REPOKIE : REPOKIE
bits : 8 - 8 (1 bit)

CC2IE : Capture/compare 2 interrupt enable
bits : 9 - 9 (1 bit)

CC1OIE : Capture/compare 1 over-capture interrupt enable
bits : 12 - 12 (1 bit)

CC2OIE : Capture/compare 2 over-capture interrupt enable
bits : 13 - 13 (1 bit)

CC1DE : Capture/compare 1 DMA request enable
bits : 16 - 16 (1 bit)

CC2DE : Capture/compare 2 DMA request enable
bits : 25 - 25 (1 bit)


CFGR

Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKSEL CKPOL CKFLT TRGFLT PRESC TRIGSEL TRIGEN TIMOUT WAVE WAVPOL PRELOAD COUNTMODE ENC

CKSEL : Clock selector
bits : 0 - 0 (1 bit)

CKPOL : Clock Polarity
bits : 1 - 2 (2 bit)

CKFLT : Configurable digital filter for external clock
bits : 3 - 4 (2 bit)

TRGFLT : Configurable digital filter for trigger
bits : 6 - 7 (2 bit)

PRESC : Clock prescaler
bits : 9 - 11 (3 bit)

TRIGSEL : Trigger selector
bits : 13 - 15 (3 bit)

TRIGEN : Trigger enable and polarity
bits : 17 - 18 (2 bit)

TIMOUT : Timeout enable
bits : 19 - 19 (1 bit)

WAVE : Waveform shape
bits : 20 - 20 (1 bit)

WAVPOL : Waveform shape polarity
bits : 21 - 21 (1 bit)

PRELOAD : Registers update mode
bits : 22 - 22 (1 bit)

COUNTMODE : counter mode enabled
bits : 23 - 23 (1 bit)

ENC : Encoder mode enable
bits : 24 - 24 (1 bit)



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