\n

GTZC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

TZSC_CR

TZSC_SECCFGR1

TZSC_SECCFGR2

TZSC_SECCFGR3

TZSC_PRIVCFGR1

TZSC_PRIVCFGR2

TZSC_PRIVCFGR3

TZSC_MPCWM1ACFGR

TZSC_MPCWM1AR

TZSC_MPCWM1BCFGR

TZSC_MPCWM1BR

TZSC_MPCWM2ACFGR

TZSC_MPCWM2AR

TZSC_MPCWM2BCFGR

TZSC_MPCWM2BR

TZSC_MPCWM3ACFGR

TZSC_MPCWM3AR

TZSC_MPCWM4ACFGR

TZSC_MPCWM4AR

TZSC_MPCWM5ACFGR

TZSC_MPCWM5AR

TZSC_MPCWM5BCFGR

TZSC_MPCWM5BR


TZSC_CR

TZSC control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_CR TZSC_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCK

LCK : lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx registers until next reset
bits : 0 - 0 (1 bit)


TZSC_SECCFGR1

TZSC secure configuration register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_SECCFGR1 TZSC_SECCFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2SEC TIM3SEC TIM4SEC TIM5SEC TIM6SEC TIM7SEC WWDGSEC IWDGSEC SPI2SEC USART2SEC USART3SEC UART4SEC UART5SEC I2C1SEC I2C2SEC CRSSEC I2C4SEC LPTIM2SEC FDCAN1SEC UCPD1SEC

TIM2SEC : secure access mode for TIM2
bits : 0 - 0 (1 bit)

TIM3SEC : secure access mode for TIM3
bits : 1 - 1 (1 bit)

TIM4SEC : secure access mode for TIM4
bits : 2 - 2 (1 bit)

TIM5SEC : secure access mode for TIM5
bits : 3 - 3 (1 bit)

TIM6SEC : secure access mode for TIM6
bits : 4 - 4 (1 bit)

TIM7SEC : secure access mode for TIM7
bits : 5 - 5 (1 bit)

WWDGSEC : secure access mode for WWDG
bits : 6 - 6 (1 bit)

IWDGSEC : secure access mode for IWDG
bits : 7 - 7 (1 bit)

SPI2SEC : secure access mode for SPI2
bits : 8 - 8 (1 bit)

USART2SEC : secure access mode for USART2
bits : 9 - 9 (1 bit)

USART3SEC : secure access mode for USART3
bits : 10 - 10 (1 bit)

UART4SEC : secure access mode for UART4
bits : 11 - 11 (1 bit)

UART5SEC : secure access mode for UART5
bits : 12 - 12 (1 bit)

I2C1SEC : secure access mode for I2C1
bits : 13 - 13 (1 bit)

I2C2SEC : secure access mode for I2C2
bits : 14 - 14 (1 bit)

CRSSEC : secure access mode for CRS
bits : 15 - 15 (1 bit)

I2C4SEC : secure access mode for I2C4
bits : 16 - 16 (1 bit)

LPTIM2SEC : secure access mode for LPTIM2
bits : 17 - 17 (1 bit)

FDCAN1SEC : secure access mode for FDCAN1
bits : 18 - 18 (1 bit)

UCPD1SEC : secure access mode for UCPD1
bits : 19 - 19 (1 bit)


TZSC_SECCFGR2

TZSC secure configuration register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_SECCFGR2 TZSC_SECCFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1SEC SPI1SEC TIM8SEC USART1SEC TIM15SEC TIM16SEC TIM17SEC SAI1SEC SAI2SEC

TIM1SEC : secure access mode for TIM1
bits : 0 - 0 (1 bit)

SPI1SEC : secure access mode for SPI1
bits : 1 - 1 (1 bit)

TIM8SEC : secure access mode for TIM8
bits : 2 - 2 (1 bit)

USART1SEC : secure access mode for USART1
bits : 3 - 3 (1 bit)

TIM15SEC : secure access mode for TIM5
bits : 4 - 4 (1 bit)

TIM16SEC : secure access mode for TIM6
bits : 5 - 5 (1 bit)

TIM17SEC : secure access mode for TIM7
bits : 6 - 6 (1 bit)

SAI1SEC : secure access mode for SAI1
bits : 7 - 7 (1 bit)

SAI2SEC : secure access mode for SAI2
bits : 8 - 8 (1 bit)


TZSC_SECCFGR3

TZSC secure configuration register 3
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_SECCFGR3 TZSC_SECCFGR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDF1SEC CORDICSEC FMACSEC CRCSEC TSCSEC DMA2DSEC ICACHE_REGSEC DCACHE_REGSEC ADC1SEC DCMISEC OTGFSSEC AESSEC HASHSEC RNGSEC PKASEC SAESSEC OCTOSPIMSEC SDMMC1SEC SDMMC2SEC FSMC_REGSEC OCTOSPI1_REGSEC OCTOSPI2_REGSEC RAMCFGSEC

MDF1SEC : secure access mode for MDF1
bits : 0 - 0 (1 bit)

CORDICSEC : secure access mode for CORDIC
bits : 1 - 1 (1 bit)

FMACSEC : secure access mode for FMAC
bits : 2 - 2 (1 bit)

CRCSEC : secure access mode for CRC
bits : 3 - 3 (1 bit)

TSCSEC : secure access mode for TSC
bits : 4 - 4 (1 bit)

DMA2DSEC : secure access mode for register of DMA2D
bits : 5 - 5 (1 bit)

ICACHE_REGSEC : secure access mode for ICACHE registers
bits : 6 - 6 (1 bit)

DCACHE_REGSEC : secure access mode for DCACHE registers
bits : 7 - 7 (1 bit)

ADC1SEC : secure access mode for ADC1
bits : 8 - 8 (1 bit)

DCMISEC : secure access mode for DCMI
bits : 9 - 9 (1 bit)

OTGFSSEC : secure access mode for OTG_FS
bits : 10 - 10 (1 bit)

AESSEC : secure access mode for AES
bits : 11 - 11 (1 bit)

HASHSEC : secure access mode for HASH
bits : 12 - 12 (1 bit)

RNGSEC : secure access mode for RNG
bits : 13 - 13 (1 bit)

PKASEC : secure access mode for PKA
bits : 14 - 14 (1 bit)

SAESSEC : secure access mode for SAES
bits : 15 - 15 (1 bit)

OCTOSPIMSEC : secure access mode for OCTOSPIM
bits : 16 - 16 (1 bit)

SDMMC1SEC : secure access mode for SDMMC2
bits : 17 - 17 (1 bit)

SDMMC2SEC : secure access mode for SDMMC1
bits : 18 - 18 (1 bit)

FSMC_REGSEC : secure access mode for FSMC registers
bits : 19 - 19 (1 bit)

OCTOSPI1_REGSEC : secure access mode for OCTOSPI1 registers
bits : 20 - 20 (1 bit)

OCTOSPI2_REGSEC : secure access mode for OCTOSPI2 registers
bits : 21 - 21 (1 bit)

RAMCFGSEC : secure access mode for RAMCFG
bits : 22 - 22 (1 bit)


TZSC_PRIVCFGR1

TZSC privilege configuration register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_PRIVCFGR1 TZSC_PRIVCFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2PRIV TIM3PRIV TIM4PRIV TIM5PRIV TIM6PRIV TIM7PRIV WWDGPRIV IWDGPRIV SPI2PRIV USART2PRIV USART3PRIV UART4PRIV UART5PRIV I2C1PRIV I2C2PRIV CRSPRIV I2C4PRIV LPTIM2PRIV FDCAN1PRIV UCPD1PRIV

TIM2PRIV : privileged access mode for TIM2
bits : 0 - 0 (1 bit)

TIM3PRIV : privileged access mode for TIM3
bits : 1 - 1 (1 bit)

TIM4PRIV : privileged access mode for TIM4
bits : 2 - 2 (1 bit)

TIM5PRIV : privileged access mode for TIM5
bits : 3 - 3 (1 bit)

TIM6PRIV : privileged access mode for TIM6
bits : 4 - 4 (1 bit)

TIM7PRIV : privileged access mode for TIM7
bits : 5 - 5 (1 bit)

WWDGPRIV : privileged access mode for WWDG
bits : 6 - 6 (1 bit)

IWDGPRIV : privileged access mode for IWDG
bits : 7 - 7 (1 bit)

SPI2PRIV : privileged access mode for SPI2
bits : 8 - 8 (1 bit)

USART2PRIV : privileged access mode for USART2
bits : 9 - 9 (1 bit)

USART3PRIV : privileged access mode for USART3
bits : 10 - 10 (1 bit)

UART4PRIV : privileged access mode for UART4
bits : 11 - 11 (1 bit)

UART5PRIV : privileged access mode for UART5
bits : 12 - 12 (1 bit)

I2C1PRIV : privileged access mode for I2C1
bits : 13 - 13 (1 bit)

I2C2PRIV : privileged access mode for I2C2
bits : 14 - 14 (1 bit)

CRSPRIV : privileged access mode for CRS
bits : 15 - 15 (1 bit)

I2C4PRIV : privileged access mode for I2C4
bits : 16 - 16 (1 bit)

LPTIM2PRIV : privileged access mode for LPTIM2
bits : 17 - 17 (1 bit)

FDCAN1PRIV : privileged access mode for FDCAN1
bits : 18 - 18 (1 bit)

UCPD1PRIV : privileged access mode for UCPD1
bits : 19 - 19 (1 bit)


TZSC_PRIVCFGR2

TZSC privilege configuration register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_PRIVCFGR2 TZSC_PRIVCFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1PRIV SPI1PRIV TIM8PRIV USART1PRIV TIM15PRIV TIM16PRIV TIM17PRIV SAI1PRIV SAI2PRIV

TIM1PRIV : privileged access mode for TIM1
bits : 0 - 0 (1 bit)

SPI1PRIV : privileged access mode for SPI1PRIV
bits : 1 - 1 (1 bit)

TIM8PRIV : privileged access mode for TIM8
bits : 2 - 2 (1 bit)

USART1PRIV : privileged access mode for USART1
bits : 3 - 3 (1 bit)

TIM15PRIV : privileged access mode for TIM15
bits : 4 - 4 (1 bit)

TIM16PRIV : privileged access mode for TIM16
bits : 5 - 5 (1 bit)

TIM17PRIV : privileged access mode for TIM17
bits : 6 - 6 (1 bit)

SAI1PRIV : privileged access mode for SAI1
bits : 7 - 7 (1 bit)

SAI2PRIV : privileged access mode for SAI2
bits : 8 - 8 (1 bit)


TZSC_PRIVCFGR3

TZSC privilege configuration register 3
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_PRIVCFGR3 TZSC_PRIVCFGR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDF1PRIV CORDICPRIV FMACPRIV CRCPRIV TSCPRIV DMA2DPRIV ICACHE_REGPRIV DCACHE_REGPRIV ADC1PRIV DCMIPRIV OTGFSPRIV AESPRIV HASHPRIV RNGPRIV PKAPRIV SAESPRIV OCTOSPIMPRIV SDMMC1PRIV SDMMC2PRIV FSMC_REGPRIV OCTOSPI1_REGPRIV OCTOSPI2_REGPRIV RAMCFGPRIV

MDF1PRIV : privileged access mode for MDF1
bits : 0 - 0 (1 bit)

CORDICPRIV : privileged access mode for CORDIC
bits : 1 - 1 (1 bit)

FMACPRIV : privileged access mode for FMAC
bits : 2 - 2 (1 bit)

CRCPRIV : privileged access mode for CRC
bits : 3 - 3 (1 bit)

TSCPRIV : privileged access mode for TSC
bits : 4 - 4 (1 bit)

DMA2DPRIV : privileged access mode for register of DMA2D
bits : 5 - 5 (1 bit)

ICACHE_REGPRIV : privileged access mode for ICACHE registers
bits : 6 - 6 (1 bit)

DCACHE_REGPRIV : privileged access mode for DCACHE registers
bits : 7 - 7 (1 bit)

ADC1PRIV : privileged access mode for ADC1
bits : 8 - 8 (1 bit)

DCMIPRIV : privileged access mode for DCMI
bits : 9 - 9 (1 bit)

OTGFSPRIV : privileged access mode for OTG_FS
bits : 10 - 10 (1 bit)

AESPRIV : privileged access mode for AES
bits : 11 - 11 (1 bit)

HASHPRIV : privileged access mode for HASH
bits : 12 - 12 (1 bit)

RNGPRIV : privileged access mode for RNG
bits : 13 - 13 (1 bit)

PKAPRIV : privileged access mode for PKA
bits : 14 - 14 (1 bit)

SAESPRIV : privileged access mode for SAES
bits : 15 - 15 (1 bit)

OCTOSPIMPRIV : privileged access mode for OCTOSPIM
bits : 16 - 16 (1 bit)

SDMMC1PRIV : privileged access mode for SDMMC2
bits : 17 - 17 (1 bit)

SDMMC2PRIV : privileged access mode for SDMMC1
bits : 18 - 18 (1 bit)

FSMC_REGPRIV : privileged access mode for FSMC registers
bits : 19 - 19 (1 bit)

OCTOSPI1_REGPRIV : privileged access mode for OCTOSPI1
bits : 20 - 20 (1 bit)

OCTOSPI2_REGPRIV : privileged access mode for OCTOSPI2
bits : 21 - 21 (1 bit)

RAMCFGPRIV : privileged access mode for RAMCFG
bits : 22 - 22 (1 bit)


TZSC_MPCWM1ACFGR

TZSC memory 1 sub-region A watermark configuration register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM1ACFGR TZSC_MPCWM1ACFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SREN SRLOCK SEC PRIV

SREN : Sub-region enable
bits : 0 - 0 (1 bit)

SRLOCK : Sub-region lock
bits : 1 - 1 (1 bit)

SEC : Secure sub-region
bits : 8 - 8 (1 bit)

PRIV : Privileged sub-region
bits : 9 - 9 (1 bit)


TZSC_MPCWM1AR

TZSC memory 1 sub-region A watermark register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM1AR TZSC_MPCWM1AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBA_START SUBA_LENGTH

SUBA_START : Start of sub-region A
bits : 0 - 10 (11 bit)

SUBA_LENGTH : Length of sub-region A
bits : 16 - 27 (12 bit)


TZSC_MPCWM1BCFGR

TZSC memory 1 sub-region B watermark configuration register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM1BCFGR TZSC_MPCWM1BCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SREN SRLOCK SEC PRIV

SREN : Sub-region enable
bits : 0 - 0 (1 bit)

SRLOCK : Sub-region lock
bits : 1 - 1 (1 bit)

SEC : Secure sub-region
bits : 8 - 8 (1 bit)

PRIV : Privileged sub-region
bits : 9 - 9 (1 bit)


TZSC_MPCWM1BR

TZSC memory 1 sub-region B watermark register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM1BR TZSC_MPCWM1BR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBB_START SUBB_LENGTH

SUBB_START : Start of sub-region A
bits : 0 - 10 (11 bit)

SUBB_LENGTH : Length of sub-region A
bits : 16 - 27 (12 bit)


TZSC_MPCWM2ACFGR

TZSC memory 2 sub-region A watermark configuration register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM2ACFGR TZSC_MPCWM2ACFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SREN SRLOCK SEC PRIV

SREN : Sub-region enable
bits : 0 - 0 (1 bit)

SRLOCK : Sub-region lock
bits : 1 - 1 (1 bit)

SEC : Secure sub-region
bits : 8 - 8 (1 bit)

PRIV : Privileged sub-region
bits : 9 - 9 (1 bit)


TZSC_MPCWM2AR

TZSC memory 2 sub-region A watermark register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM2AR TZSC_MPCWM2AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBA_START SUBA_LENGTH

SUBA_START : Start of sub-region A
bits : 0 - 10 (11 bit)

SUBA_LENGTH : Length of sub-region A
bits : 16 - 27 (12 bit)


TZSC_MPCWM2BCFGR

TZSC memory 2 sub-region B watermark configuration register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM2BCFGR TZSC_MPCWM2BCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SREN SRLOCK SEC PRIV

SREN : Sub-region enable
bits : 0 - 0 (1 bit)

SRLOCK : Sub-region lock
bits : 1 - 1 (1 bit)

SEC : Secure sub-region
bits : 8 - 8 (1 bit)

PRIV : Privileged sub-region
bits : 9 - 9 (1 bit)


TZSC_MPCWM2BR

TZSC memory 2 sub-region B watermark register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM2BR TZSC_MPCWM2BR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBB_START SUBB_LENGTH

SUBB_START : Start of sub-region A
bits : 0 - 10 (11 bit)

SUBB_LENGTH : Length of sub-region A
bits : 16 - 27 (12 bit)


TZSC_MPCWM3ACFGR

TZSC memory 3 sub-region A watermark configuration register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM3ACFGR TZSC_MPCWM3ACFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SREN SRLOCK SEC PRIV

SREN : Sub-region enable
bits : 0 - 0 (1 bit)

SRLOCK : Sub-region lock
bits : 1 - 1 (1 bit)

SEC : Secure sub-region
bits : 8 - 8 (1 bit)

PRIV : Privileged sub-region
bits : 9 - 9 (1 bit)


TZSC_MPCWM3AR

TZSC memory 3 sub-region A watermark register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM3AR TZSC_MPCWM3AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBA_START SUBA_LENGTH

SUBA_START : Start of sub-region A
bits : 0 - 10 (11 bit)

SUBA_LENGTH : Length of sub-region A
bits : 16 - 27 (12 bit)


TZSC_MPCWM4ACFGR

TZSC memory 4 sub-region A watermark configuration register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM4ACFGR TZSC_MPCWM4ACFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SREN SRLOCK SEC PRIV

SREN : Sub-region enable
bits : 0 - 0 (1 bit)

SRLOCK : Sub-region lock
bits : 1 - 1 (1 bit)

SEC : Secure sub-region
bits : 8 - 8 (1 bit)

PRIV : Privileged sub-region
bits : 9 - 9 (1 bit)


TZSC_MPCWM4AR

TZSC memory 4 sub-region A watermark register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM4AR TZSC_MPCWM4AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBA_START SUBA_LENGTH

SUBA_START : Start of sub-region A
bits : 0 - 10 (11 bit)

SUBA_LENGTH : Length of sub-region A
bits : 16 - 27 (12 bit)


TZSC_MPCWM5ACFGR

TZSC memory 5 sub-region A watermark configuration register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM5ACFGR TZSC_MPCWM5ACFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SREN SRLOCK SEC PRIV

SREN : Sub-region enable
bits : 0 - 0 (1 bit)

SRLOCK : Sub-region lock
bits : 1 - 1 (1 bit)

SEC : Secure sub-region
bits : 8 - 8 (1 bit)

PRIV : Privileged sub-region
bits : 9 - 9 (1 bit)


TZSC_MPCWM5AR

TZSC memory 5 sub-region A watermark register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM5AR TZSC_MPCWM5AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBA_START SUBA_LENGTH

SUBA_START : Start of sub-region A
bits : 0 - 10 (11 bit)

SUBA_LENGTH : Length of sub-region A
bits : 16 - 27 (12 bit)


TZSC_MPCWM5BCFGR

TZSC memory 5 sub-region B watermark configuration register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM5BCFGR TZSC_MPCWM5BCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SREN SRLOCK SEC PRIV

SREN : Sub-region enable
bits : 0 - 0 (1 bit)

SRLOCK : Sub-region lock
bits : 1 - 1 (1 bit)

SEC : Secure sub-region
bits : 8 - 8 (1 bit)

PRIV : Privileged sub-region
bits : 9 - 9 (1 bit)


TZSC_MPCWM5BR

TZSC memory 5 sub-region B watermark register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM5BR TZSC_MPCWM5BR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBB_START SUBB_LENGTH

SUBB_START : Start of sub-region A
bits : 0 - 10 (11 bit)

SUBB_LENGTH : Length of sub-region A
bits : 16 - 27 (12 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.