Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
PWR control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPMS : Low-power mode selection These bits select the low-power mode entered when the CPU enters the Deepsleep mode. 10x: Standby mode (Standby mode also entered if LPMS = 11X in PWR_CR1 with BREN = 1 in PWR_BDCR1) 11x: Shutdown mode if BREN = 0 in PWR_BDCR1
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Stop 0 mode
0x1 : B_0x1
Stop 1 mode
0x2 : B_0x2
Stop 2 mode
0x3 : B_0x3
Stop 3 mode
End of enumeration elements list.
RRSB1 : SRAM2 page 1 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 1 content in Stop 3 and Standby modes. The SRAM2 page 1 corresponds to the first 8 Kbytes of the SRAM2 (from SRAM2 base address to SRAM2 base address + 0x1FFF). Note: This bit has no effect in Shutdown mode.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM2 page1 content not retained in Stop 3 and Standby modes
0x1 : B_0x1
SRAM2 page1 content retained in Stop 3 and Standby modes
End of enumeration elements list.
RRSB2 : SRAM2 page 2 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 2 content in Stop 3 and Standby modes. The SRAM2 page 2 corresponds to the last 56 Kbytes of the SRAM2 (from SRAM2 base address + 0x2000 to SRAM2 base address + 0xFFFF). Note: This bit has no effect in Shutdown mode.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM2 page2 content not retained in Stop3 and Standby modes
0x1 : B_0x1
SRAM2 page2 content retained in Stop 3 and Standby modes
End of enumeration elements list.
ULPMEN : BOR ultra-low power mode This bit is used to reduce the consumption by configuring the BOR in discontinuous mode. This bit must be set to reach the lowest power consumption in the low-power modes.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BOR operating in continuous (normal) mode in Stop 1, Stop 2, Stop 3 and Standby modes and when the regulator is in range 4 (Run, Sleep or Stop 0 mode)
0x1 : B_0x1
BOR operating in discontinuous (ultra-low power) mode in Stop 1, Stop 2, Stop 3 and Standby modes, and when the regulator is in range 4 (Run, Sleep or Stop 0 mode)
End of enumeration elements list.
SRAM1PD : SRAM1 power down This bit is used to reduce the consumption by powering off the SRAM1.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM1 powered on
0x1 : B_0x1
SRAM1 powered off
End of enumeration elements list.
SRAM2PD : SRAM2 power down This bit is used to reduce the consumption by powering off the SRAM2.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM2 powered on
0x1 : B_0x1
SRAM2 powered off
End of enumeration elements list.
SRAM3PD : SRAM3 power down This bit is used to reduce the consumption by powering off the SRAM3.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM3 powered on
0x1 : B_0x1
SRAM3 powered off
End of enumeration elements list.
SRAM4PD : SRAM4 power down This bit is used to reduce the consumption by powering off the SRAM4.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM4 powered on
0x1 : B_0x1
SRAM4 powered off
End of enumeration elements list.
PWR supply voltage monitoring control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PVDE : Power voltage detector enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Power voltage detector disabled
0x1 : B_0x1
Power voltage detector enabled
End of enumeration elements list.
PVDLS : Power voltage detector level selection These bits select the voltage threshold detected by the power voltage detector:
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
VPVD0 around 2.0 V
0x1 : B_0x1
VPVD1 around 2.2 V
0x2 : B_0x2
VPVD2 around 2.4 V
0x3 : B_0x3
VPVD3 around 2.5 V
0x4 : B_0x4
VPVD4 around 2.6 V
0x5 : B_0x5
VPVD5 around 2.8 V
0x6 : B_0x6
VPVD6 around 2.9 V
0x7 : B_0x7
External input analog voltage PVD_IN (compared internally to VREFINT)
End of enumeration elements list.
UVMEN : VDDUSB independent USB voltage monitor enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
VDDUSB voltage monitor disabled
0x1 : B_0x1
VDDUSB voltage monitor enabled
End of enumeration elements list.
IO2VMEN : VDDIO2 independent I/Os voltage monitor enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
VDDIO2 voltage monitor disabled
0x1 : B_0x1
VDDIO2 voltage monitor enabled
End of enumeration elements list.
AVM1EN : VDDA independent analog supply voltage monitor 1 enable (1.6 V threshold)
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
VDDA voltage monitor 1 disabled
0x1 : B_0x1
VDDA voltage monitor 1 enabled
End of enumeration elements list.
AVM2EN : VDDA independent analog supply voltage monitor 2 enable (1.8 V threshold)
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
VDDA voltage monitor 2 disabled
0x1 : B_0x1
VDDA voltage monitor 2 enabled
End of enumeration elements list.
USV : VDDUSB independent USB supply valid
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
VDDUSB not present: logical and electrical isolation is applied to ignore this supply.
0x1 : B_0x1
VDDUSB valid
End of enumeration elements list.
IO2SV : VDDIO2 independent I/Os supply valid This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose. Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the application, the VDDIO2 voltage monitor can be used to determine whether this supply is ready or not.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
VDDIO2 not present: logical and electrical isolation is applied to ignore this supply.
0x1 : B_0x1
VDDIO2 valid
End of enumeration elements list.
ASV : VDDA independent analog supply valid
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
VDDA not present: logical and electrical isolation is applied to ignore this supply.
0x1 : B_0x1
VDDA valid
End of enumeration elements list.
PWR wakeup control register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUPEN1 : Wakeup pin WKUP1 enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Wakeup pin WKUP1 disabled
0x1 : B_0x1
Wakeup pin WKUP1 enabled
End of enumeration elements list.
WUPEN2 : Wakeup pin WKUP2 enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Wakeup pin WKUP2 disabled
0x1 : B_0x1
Wakeup pin WKUP2 enabled
End of enumeration elements list.
WUPEN3 : Wakeup pin WKUP3 enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Wakeup pin WKUP3 disabled
0x1 : B_0x1
Wakeup pin WKUP3 enabled
End of enumeration elements list.
WUPEN4 : Wakeup pin WKUP4 enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Wakeup pin WKUP4 disabled
0x1 : B_0x1
Wakeup pin WKUP4 enabled
End of enumeration elements list.
WUPEN5 : Wakeup pin WKUP5 enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Wakeup pin WKUP5 disabled
0x1 : B_0x1
Wakeup pin WKUP5 enabled
End of enumeration elements list.
WUPEN6 : Wakeup pin WKUP6 enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Wakeup pin WKUP6 disabled
0x1 : B_0x1
Wakeup pin WKUP6 enabled
End of enumeration elements list.
WUPEN7 : Wakeup pin WKUP7 enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Wakeup pin WKUP7 disabled
0x1 : B_0x1
Wakeup pin WKUP7 enabled
End of enumeration elements list.
WUPEN8 : Wakeup pin WKUP8 enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Wakeup pin WKUP8 disabled
0x1 : B_0x1
Wakeup pin WKUP8 enabled
End of enumeration elements list.
PWR wakeup control register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUPP1 : Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Detection on high level (rising edge)
0x1 : B_0x1
Detection on low level (falling edge)
End of enumeration elements list.
WUPP2 : Wakeup pin WKUP2 polarity This bit must be configured when WUPEN2 = 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Detection on high level (rising edge)
0x1 : B_0x1
Detection on low level (falling edge)
End of enumeration elements list.
WUPP3 : Wakeup pin WKUP3 polarity This bit must be configured when WUPEN3 = 0.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Detection on high level (rising edge)
0x1 : B_0x1
Detection on low level (falling edge)
End of enumeration elements list.
WUPP4 : Wakeup pin WKUP4 polarity This bit must be configured when WUPEN4 = 0.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Detection on high level (rising edge)
0x1 : B_0x1
Detection on low level (falling edge)
End of enumeration elements list.
WUPP5 : Wakeup pin WKUP5 polarity This bit must be configured when WUPEN5 = 0.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Detection on high level (rising edge)
0x1 : B_0x1
Detection on low level (falling edge)
End of enumeration elements list.
WUPP6 : Wakeup pin WKUP6 polarity This bit must be configured when WUPEN6 = 0.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Detection on high level (rising edge)
0x1 : B_0x1
Detection on low level (falling edge)
End of enumeration elements list.
WUPP7 : Wakeup pin WKUP7 polarity This bit must be configured when WUPEN7 = 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Detection on high level (rising edge)
0x1 : B_0x1
Detection on low level (falling edge)
End of enumeration elements list.
WUPP8 : Wakeup pin WKUP8 polarity This bit must be configured when WUPEN8 = 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Detection on high level (rising edge)
0x1 : B_0x1
Detection on low level (falling edge)
End of enumeration elements list.
PWR wakeup control register 3
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUSEL1 : Wakeup pin WKUP1 selection This field must be configured when WUPEN1 = 0.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
WKUP0_0
0x1 : B_0x1
WKUP0_1
0x2 : B_0x2
WKUP0_2
0x3 : B_0x3
WKUP0_3
End of enumeration elements list.
WUSEL2 : Wakeup pin WKUP2 selection This field must be configured when WUPEN2 = 0.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
WKUP2_0
0x1 : B_0x1
WKUP2_1
0x2 : B_0x2
WKUP2_2
0x3 : B_0x3
WKUP2_3
End of enumeration elements list.
WUSEL3 : Wakeup pin WKUP3 selection This field must be configured when WUPEN3 = 0.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
WKUP3_0
0x1 : B_0x1
WKUP3_1
0x2 : B_0x2
WKUP3_2
0x3 : B_0x3
WKUP3_3
End of enumeration elements list.
WUSEL4 : Wakeup pin WKUP4 selection This field must be configured when WUPEN4 = 0.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
WKUP4_0
0x1 : B_0x1
WKUP4_1
0x2 : B_0x2
WKUP4_2
0x3 : B_0x3
WKUP4_3
End of enumeration elements list.
WUSEL5 : Wakeup pin WKUP5 selection This field must be configured when WUPEN5 = 0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
WKUP5_0
0x1 : B_0x1
WKUP5_1
0x2 : B_0x2
WKUP5_2
0x3 : B_0x3
WKUP5_3
End of enumeration elements list.
WUSEL6 : Wakeup pin WKUP6 selection This field must be configured when WUPEN6 = 0.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
WKUP6_0
0x1 : B_0x1
WKUP6_1
0x2 : B_0x2
WKUP6_2
0x3 : B_0x3
WKUP6_3
End of enumeration elements list.
WUSEL7 : Wakeup pin WKUP7 selection This field must be configured when WUPEN7 = 0.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
WKUP7_0
0x1 : B_0x1
WKUP7_1
0x2 : B_0x2
WKUP7_2
0x3 : B_0x3
WKUP7_3
End of enumeration elements list.
WUSEL8 : Wakeup pin WKUP8 selection This field must be configured when WUPEN8 = 0.
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
WKUP8_0
0x1 : B_0x1
WKUP8_1
0x2 : B_0x2
WKUP8_2
0x3 : B_0x3
WKUP8_3
End of enumeration elements list.
PWR Backup domain control register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BREN : Backup RAM retention in Standby and VBAT modes When this bit is set, the backup RAM content is kept in Standby and VBAT modes. If BREN is reset, the backup RAM can still be used in Run, Sleep and Stop modes. However, its content is lost in Standby, Shutdown and VBAT modes. This bit can be written only when the regulator is LDO, which must be configured before switching to SMPS. Note: Backup RAM cannot be preserved in Shutdown mode.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Backup RAM content lost in Standby and VBAT modes
0x1 : B_0x1
Backup RAM content preserved in Standby and VBAT modes
End of enumeration elements list.
MONEN : Backup domain voltage and temperature monitoring enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Backup domain voltage and temperature monitoring disabled
0x1 : B_0x1
Backup domain voltage and temperature monitoring enabled
End of enumeration elements list.
PWR Backup domain control register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBE : VBAT charging enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
VBAT battery charging disabled
0x1 : B_0x1
VBAT battery charging enabled
End of enumeration elements list.
VBRS : VBAT charging resistor selection
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Charge VBAT through a 5 kΩ resistor
0x1 : B_0x1
Charge VBAT through a 1.5 kΩ resistor
End of enumeration elements list.
PWR disable Backup domain register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBP : Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Write access to Backup domain disabled
0x1 : B_0x1
Write access to Backup domain enabled
End of enumeration elements list.
PWR USB Type-C™ and Power Delivery register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UCPD_DBDIS : UCPD dead battery disable After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized before doing the disable).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
UCPD dead battery pull-down behavior enabled on UCPDx_CC1 and UCPDx_CC2 pins
0x1 : B_0x1
UCPD dead battery pull-down behavior disabled on UCPDx_CC1 and UCPDx_CC2 pins
End of enumeration elements list.
UCPD_STBY : UCPD Standby mode When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD. It must be written to 0 after exiting the Standby mode and before writing any UCPD registers.
bits : 1 - 1 (1 bit)
access : read-write
PWR security configuration register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUP1SEC : WUP1 secure protection
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Bits related to the WKUP1 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access.
0x1 : B_0x1
Bits related to the WKUP1 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access.
End of enumeration elements list.
WUP2SEC : WUP2 secure protection
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Bits related to the WKUP2 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access.
0x1 : B_0x1
Bits related to the WKUP2 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access.
End of enumeration elements list.
WUP3SEC : WUP3 secure protection
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Bits related to the WKUP3 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access.
0x1 : B_0x1
Bits related to the WKUP3 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access.
End of enumeration elements list.
WUP4SEC : WUP4 secure protection
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Bits related to the WKUP4 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access.
0x1 : B_0x1
Bits related to the WKUP4 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access.
End of enumeration elements list.
WUP5SEC : WUP5 secure protection
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Bits related to the WKUP5 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access.
0x1 : B_0x1
Bits related to the WKUP5 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access.
End of enumeration elements list.
WUP6SEC : WUP6 secure protection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Bits related to the WKUP6 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access.
0x1 : B_0x1
Bits related to the WKUP6 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access.
End of enumeration elements list.
WUP7SEC : WUP7 secure protection
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Bits related to the WKUP7 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access.
0x1 : B_0x1
Bits related to the WKUP7 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access.
End of enumeration elements list.
WUP8SEC : WUP8 secure protection
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Bits related to the WKUP8 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access.
0x1 : B_0x1
Bits related to the WKUP8 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access.
End of enumeration elements list.
LPMSEC : Low-power modes secure protection
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PWR_CR1, PWR_CR2 and CSSF in the PWR_SR can be read and written with secure or non-secure access.
0x1 : B_0x1
PWR_CR1, PWR_CR2, and CSSF in the PWR_SR can be read and written only with secure access.
End of enumeration elements list.
VDMSEC : Voltage detection and monitoring secure protection
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PWR_SVMCR and PWR_CR3 can be read and written with secure or non-secure access.
0x1 : B_0x1
PWR_SVMCR and PWR_CR3 can be read and written only with secure access.
End of enumeration elements list.
VBSEC : Backup domain secure protection
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PWR_BDCR1, PWR_BDCR2 and PWR_DBPR can be read and written with secure or non-secure access.
0x1 : B_0x1
PWR_BDCR1, PWR_BDCR2 and PWR_DBPR can be read and written only with secure access.
End of enumeration elements list.
APCSEC : Pull-up/pull-down secure protection
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PWR_APCR can be read and written with secure or non-secure access.
0x1 : B_0x1
PWR_APCR can be read and written only with secure access.
End of enumeration elements list.
PWR privilege control register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPRIV : PWR secure functions privilege configuration This bit is set and reset by software. It can be written only by a secure privileged access.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Read and write to PWR secure functions can be done by privileged or unprivileged access.
0x1 : B_0x1
Read and write to PWR secure functions can be done by privileged access only.
End of enumeration elements list.
NSPRIV : PWR non-secure functions privilege configuration This bit is set and reset by software. It can be written only by privileged access, secure or non-secure.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Read and write to PWR non-secure functions can be done by privileged or unprivileged access.
0x1 : B_0x1
Read and write to PWR non-secure functions can be done by privileged access only.
End of enumeration elements list.
PWR status register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSSF : Clear Stop and Standby flags This bit is protected against non-secure access when LPMSEC = 1 in PWR_SECCFGR. This bit is protected against unprivileged access when LPMSEC = 1 and SPRIV = 1 in PWR_PRIVCFGR, or when LPMSEC = 0 and NSPRIV = 1. Writing 1 to this bit clears the STOPF and SBF flags.
bits : 0 - 0 (1 bit)
access : write-only
STOPF : Stop flag This bit is set by hardware when the device enters a Stop mode, and is cleared by software by writing 1 to the CSSF bit.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The device did not enter any Stop mode.
0x1 : B_0x1
The device entered a Stop mode.
End of enumeration elements list.
SBF : Standby flag This bit is set by hardware when the device enters the Standby mode, and is cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
The device did not enter Standby mode.
0x1 : B_0x1
The device entered Standby mode.
End of enumeration elements list.
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGS : Regulator selection
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
LDO selected
0x1 : B_0x1
SMPS selected
End of enumeration elements list.
PVDO : VDD voltage detector output
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
VDD is equal or above the PVD threshold selected by PVDLS[2:0].
0x1 : B_0x1
VDD is below the PVD threshold selected by PVDLS[2:0].
End of enumeration elements list.
ACTVOSRDY : Voltage level ready for currently used VOS
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
VCORE is above or below the current voltage scaling provided by ACTVOS[1:0].
0x1 : B_0x1
VCORE is equal to the current voltage scaling provided by ACTVOS[1:0]
End of enumeration elements list.
ACTVOS : VOS currently applied to VCORE This field provides the last VOS value.
bits : 16 - 17 (2 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Range 4 (lowest power)
0x1 : B_0x1
Range 3
0x2 : B_0x2
Range 2
0x3 : B_0x3
Range 1 (highest frequency)
End of enumeration elements list.
VDDUSBRDY : VDDUSB ready
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
VDDUSB is below the threshold of the VDDUSB voltage monitor.
0x1 : B_0x1
VDDUSB is equal or above the threshold of the VDDUSB voltage monitor.
End of enumeration elements list.
VDDIO2RDY : VDDIO2 ready
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
VDDIO2 is below the threshold of the VDDIO2 voltage monitor.
0x1 : B_0x1
VDDIO2 is equal or above the threshold of the VDDIO2 voltage monitor.
End of enumeration elements list.
VDDA1RDY : VDDA ready versus 1.6V voltage monitor
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
VDDA is below the threshold of the VDDA voltage monitor 1 (around 1.6 V).
0x1 : B_0x1
VDDA is equal or above the threshold of the VDDA voltage monitor 1 (around 1.6 V).
End of enumeration elements list.
VDDA2RDY : VDDA ready versus 1.8 V voltage monitor
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
VDDA is below the threshold of the VDDA voltage monitor 2 (around 1.8 V).
0x1 : B_0x1
VDDA is equal or above the threshold of the VDDA voltage monitor 2 (around 1.8 V).
End of enumeration elements list.
PWR control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM1PDS1 : SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM1 page 1 content retained in Stop modes
0x1 : B_0x1
SRAM1 page 1 content lost in Stop modes
End of enumeration elements list.
SRAM1PDS2 : SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM1 page 2 content retained in Stop modes
0x1 : B_0x1
SRAM1 page 2 content lost in Stop modes
End of enumeration elements list.
SRAM1PDS3 : SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM1 page 3 content retained in Stop modes
0x1 : B_0x1
SRAM1 page 3 content lost in Stop modes
End of enumeration elements list.
SRAM2PDS1 : SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 1 retention in Stop 3 is controlled by RRSB1 bit in PWR_CR1.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM2 page 1 content retained in Stop modes
0x1 : B_0x1
SRAM2 page 1 content lost in Stop modes
End of enumeration elements list.
SRAM2PDS2 : SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 2 retention in Stop 3 is controlled by RRSB2 bit in PWR_CR1.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM2 page 2 content retained in Stop modes
0x1 : B_0x1
SRAM2 page 2 content lost in Stop modes
End of enumeration elements list.
SRAM4PDS : SRAM4 power-down in Stop modes (Stop 0, 1, 2, 3)
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM4 content retained in Stop modes
0x1 : B_0x1
SRAM4 content lost in Stop modes
End of enumeration elements list.
ICRAMPDS : ICACHE SRAM power-down in Stop modes (Stop 0, 1, 2, 3)
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ICACHE SRAM content retained in Stop modes
0x1 : B_0x1
ICACHE SRAM content lost in Stop modes
End of enumeration elements list.
DC1RAMPDS : DCACHE1 SRAM power-down in Stop modes (Stop 0, 1, 2, 3)
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DCACHE1 SRAM content retained in Stop modes
0x1 : B_0x1
DCACHE1 SRAM content lost in Stop modes
End of enumeration elements list.
DMA2DRAMPDS : DMA2D SRAM power-down in Stop modes (Stop 0, 1, 2, 3)
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA2D SRAM content retained in Stop modes
0x1 : B_0x1
DMA2D SRAM content lost in Stop modes
End of enumeration elements list.
PRAMPDS : FMAC, FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0, 1, 2, 3)
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FMAC, FDCAN and USB peripherals SRAM content retained in Stop modes
0x1 : B_0x1
FMAC, FDCAN and USB peripherals SRAM content lost in Stop modes
End of enumeration elements list.
PKARAMPDS : PKA SRAM power-down
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PKA SRAM content retained in Stop modes
0x1 : B_0x1
PKA SRAM content lost in Stop modes
End of enumeration elements list.
SRAM4FWU : SRAM4 fast wakeup from Stop 0, Stop 1 and Stop 2 modes This bit is used to obtain the best trade-off between low-power consumption and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting Stop 0, 1 and 2 modes, and also increases the LPDMA access time to SRAM4 during Stop modes.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM4 enters low-power mode in Stop 0, 1 and 2 modes (source biasing for lower-power consumption).
0x1 : B_0x1
SRAM4 remains in normal mode in Stop 0, 1 and 2 modes (higher consumption but no SRAM4 wakeup time).
End of enumeration elements list.
FLASHFWU : Flash memory fast wakeup from Stop 0 and Stop 1 modes This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes. When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Flash memory enters low-power mode in Stop 0 and Stop 1 modes (lower-power consumption).
0x1 : B_0x1
Flash memory remains in normal mode in Stop 0 and Stop 1 modes (faster wakeup time).
End of enumeration elements list.
SRAM3PDS1 : SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM3 page 1 content retained in Stop modes
0x1 : B_0x1
SRAM3 page 1 content lost in Stop modes
End of enumeration elements list.
SRAM3PDS2 : SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM3 page 2 content retained in Stop modes
0x1 : B_0x1
SRAM3 page 2 content lost in Stop modes
End of enumeration elements list.
SRAM3PDS3 : SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM3 page 3 content retained in Stop modes
0x1 : B_0x1
SRAM3 page 3 content lost in Stop modes
End of enumeration elements list.
SRAM3PDS4 : SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM3 page 4 content retained in Stop modes
0x1 : B_0x1
SRAM3 page 4 content lost in Stop modes
End of enumeration elements list.
SRAM3PDS5 : SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM3 page 5 content retained in Stop modes
0x1 : B_0x1
SRAM3 page 5 content lost in Stop modes
End of enumeration elements list.
SRAM3PDS6 : SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM3 page 6 content retained in Stop modes
0x1 : B_0x1
SRAM3 page 6 content lost in Stop modes
End of enumeration elements list.
SRAM3PDS7 : SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM3 page 7 content retained in Stop modes
0x1 : B_0x1
SRAM3 page 7 content lost in Stop modes
End of enumeration elements list.
SRAM3PDS8 : SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM3 page 8 content retained in Stop modes
0x1 : B_0x1
SRAM3 page 8 content lost in Stop modes
End of enumeration elements list.
SRDRUN : SmartRun domain in Run mode
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SmartRun domain AHB3 and APB3 clocks disabled by default in Stop 0,1, 2 modes
0x1 : B_0x1
SmartRun domain AHB3 and APB3 clocks kept enabled in Stop 0,1, 2 modes
End of enumeration elements list.
PWR Backup domain status register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATH : Backup domain voltage level monitoring versus high threshold
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Backup domain voltage level < high threshold
0x1 : B_0x1
Backup domain voltage level ≥ high threshold
End of enumeration elements list.
TEMPL : Temperature level monitoring versus low threshold
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Temperature > low threshold
0x1 : B_0x1
Temperature ≤ low threshold
End of enumeration elements list.
TEMPH : Temperature level monitoring versus high threshold
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Temperature < high threshold
0x1 : B_0x1
Temperature ≥ high threshold
End of enumeration elements list.
PWR wakeup status register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUF1 : Wakeup flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN1 = 0.
bits : 0 - 0 (1 bit)
access : read-only
WUF2 : Wakeup flag 2 This bit is set when a wakeup event is detected on WKUP2 pin. This bit is cleared by writing 1 in the CWUF2 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN2 = 0.
bits : 1 - 1 (1 bit)
access : read-only
WUF3 : Wakeup flag 3 This bit is set when a wakeup event is detected on WKUP3 pin. This bit is cleared by writing 1 in the CWUF3 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN3 = 0.
bits : 2 - 2 (1 bit)
access : read-only
WUF4 : Wakeup flag 4 This bit is set when a wakeup event is detected on WKUP4 pin. This bit is cleared by writing 1 in the CWUF4 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN4 = 0.
bits : 3 - 3 (1 bit)
access : read-only
WUF5 : Wakeup flag 5 This bit is set when a wakeup event is detected on WKUP5 pin. This bit is cleared by writing 1 in the CWUF5 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN5 = 0.
bits : 4 - 4 (1 bit)
access : read-only
WUF6 : Wakeup flag 6 This bit is set when a wakeup event is detected on WKUP6 pin. This bit is cleared by writing 1 in the CWUF6 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN6 = 0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared.
bits : 5 - 5 (1 bit)
access : read-only
WUF7 : Wakeup flag 7 This bit is set when a wakeup event is detected on WKUP7 pin. This bit is cleared by writing 1 in the CWUF7 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN7 = 0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared.
bits : 6 - 6 (1 bit)
access : read-only
WUF8 : Wakeup flag 8 This bit is set when a wakeup event is detected on WKUP8 pin. This bit is cleared by writing 1 in the CWUF8 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN8 = 0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared.
bits : 7 - 7 (1 bit)
access : read-only
PWR wakeup status clear register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CWUF1 : Wakeup flag 1 Writing 1 to this bit clears the WUF1 flag in PWR_WUSR.
bits : 0 - 0 (1 bit)
access : write-only
CWUF2 : Wakeup flag 2 Writing 1 to this bit clears the WUF2 flag in PWR_WUSR.
bits : 1 - 1 (1 bit)
access : write-only
CWUF3 : Wakeup flag 3 Writing 1 to this bit clears the WUF3 flag in PWR_WUSR.
bits : 2 - 2 (1 bit)
access : write-only
CWUF4 : Wakeup flag 4 Writing 1 to this bit clears the WUF4 flag in PWR_WUSR.
bits : 3 - 3 (1 bit)
access : write-only
CWUF5 : Wakeup flag 5 Writing 1 to this bit clears the WUF5 flag in PWR_WUSR.
bits : 4 - 4 (1 bit)
access : write-only
CWUF6 : Wakeup flag 6 Writing 1 to this bit clears the WUF6 flag in PWR_WUSR.
bits : 5 - 5 (1 bit)
access : write-only
CWUF7 : Wakeup flag 7 Writing 1 to this bit clears the WUF7 flag in PWR_WUSR.
bits : 6 - 6 (1 bit)
access : write-only
CWUF8 : Wakeup flag 8 Writing 1 to this bit clears the WUF8 flag in PWR_WUSR.
bits : 7 - 7 (1 bit)
access : write-only
PWR apply pull configuration register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APC : Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in PWR_PUCRx and PWR_PDCRx are applied. When this bit is cleared, PWR_PUCRx and PWR_PDCRx are not applied to the I/Os.
bits : 0 - 0 (1 bit)
access : read-write
PWR port A pull-up control register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PU0 : Port A pull-up bit
bits : 0 - 0 (1 bit)
access : read-write
PU1 : Port A pull-up bit
bits : 1 - 1 (1 bit)
access : read-write
PU2 : Port A pull-up bit
bits : 2 - 2 (1 bit)
access : read-write
PU3 : Port A pull-up bit
bits : 3 - 3 (1 bit)
access : read-write
PU4 : Port A pull-up bit
bits : 4 - 4 (1 bit)
access : read-write
PU5 : Port A pull-up bit
bits : 5 - 5 (1 bit)
access : read-write
PU6 : Port A pull-up bit
bits : 6 - 6 (1 bit)
access : read-write
PU7 : Port A pull-up bit
bits : 7 - 7 (1 bit)
access : read-write
PU8 : Port A pull-up bit
bits : 8 - 8 (1 bit)
access : read-write
PU9 : Port A pull-up bit
bits : 9 - 9 (1 bit)
access : read-write
PU10 : Port A pull-up bit
bits : 10 - 10 (1 bit)
access : read-write
PU11 : Port A pull-up bit
bits : 11 - 11 (1 bit)
access : read-write
PU12 : Port A pull-up bit
bits : 12 - 12 (1 bit)
access : read-write
PU13 : Port A pull-up bit
bits : 13 - 13 (1 bit)
access : read-write
PU15 : Port A pull-up bit 15 When set, this bit activates the pull-up on PA15 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD15 bit is also set.
bits : 15 - 15 (1 bit)
access : read-write
PWR port A pull-down control register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD0 : Port A pull-down bit
bits : 0 - 0 (1 bit)
access : read-write
PD1 : Port A pull-down bit
bits : 1 - 1 (1 bit)
access : read-write
PD2 : Port A pull-down bit
bits : 2 - 2 (1 bit)
access : read-write
PD3 : Port A pull-down bit
bits : 3 - 3 (1 bit)
access : read-write
PD4 : Port A pull-down bit
bits : 4 - 4 (1 bit)
access : read-write
PD5 : Port A pull-down bit
bits : 5 - 5 (1 bit)
access : read-write
PD6 : Port A pull-down bit
bits : 6 - 6 (1 bit)
access : read-write
PD7 : Port A pull-down bit
bits : 7 - 7 (1 bit)
access : read-write
PD8 : Port A pull-down bit
bits : 8 - 8 (1 bit)
access : read-write
PD9 : Port A pull-down bit
bits : 9 - 9 (1 bit)
access : read-write
PD10 : Port A pull-down bit
bits : 10 - 10 (1 bit)
access : read-write
PD11 : Port A pull-down bit
bits : 11 - 11 (1 bit)
access : read-write
PD12 : Port A pull-down bit
bits : 12 - 12 (1 bit)
access : read-write
PD14 : Port A pull-down bit
bits : 14 - 14 (1 bit)
access : read-write
PWR port B pull-up control register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PU0 : Port B pull-up bit
bits : 0 - 0 (1 bit)
access : read-write
PU1 : Port B pull-up bit
bits : 1 - 1 (1 bit)
access : read-write
PU2 : Port B pull-up bit
bits : 2 - 2 (1 bit)
access : read-write
PU3 : Port B pull-up bit
bits : 3 - 3 (1 bit)
access : read-write
PU4 : Port B pull-up bit
bits : 4 - 4 (1 bit)
access : read-write
PU5 : Port B pull-up bit
bits : 5 - 5 (1 bit)
access : read-write
PU6 : Port B pull-up bit
bits : 6 - 6 (1 bit)
access : read-write
PU7 : Port B pull-up bit
bits : 7 - 7 (1 bit)
access : read-write
PU8 : Port B pull-up bit
bits : 8 - 8 (1 bit)
access : read-write
PU9 : Port B pull-up bit
bits : 9 - 9 (1 bit)
access : read-write
PU10 : Port B pull-up bit
bits : 10 - 10 (1 bit)
access : read-write
PU11 : Port B pull-up bit
bits : 11 - 11 (1 bit)
access : read-write
PU12 : Port B pull-up bit
bits : 12 - 12 (1 bit)
access : read-write
PU13 : Port B pull-up bit
bits : 13 - 13 (1 bit)
access : read-write
PU14 : Port B pull-up bit
bits : 14 - 14 (1 bit)
access : read-write
PU15 : Port B pull-up bit
bits : 15 - 15 (1 bit)
access : read-write
PWR port B pull-down control register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD0 : Port B pull-down bit
bits : 0 - 0 (1 bit)
access : read-write
PD1 : Port B pull-down bit
bits : 1 - 1 (1 bit)
access : read-write
PD2 : Port B pull-down bit
bits : 2 - 2 (1 bit)
access : read-write
PD3 : Port B pull-down bit
bits : 3 - 3 (1 bit)
access : read-write
PD5 : Port B pull-down bit
bits : 5 - 5 (1 bit)
access : read-write
PD6 : Port B pull-down bit
bits : 6 - 6 (1 bit)
access : read-write
PD7 : Port B pull-down bit
bits : 7 - 7 (1 bit)
access : read-write
PD8 : Port B pull-down bit
bits : 8 - 8 (1 bit)
access : read-write
PD9 : Port B pull-down bit
bits : 9 - 9 (1 bit)
access : read-write
PD10 : Port B pull-down bit
bits : 10 - 10 (1 bit)
access : read-write
PD11 : Port B pull-down bit
bits : 11 - 11 (1 bit)
access : read-write
PD12 : Port B pull-down bit
bits : 12 - 12 (1 bit)
access : read-write
PD13 : Port B pull-down bit
bits : 13 - 13 (1 bit)
access : read-write
PD14 : Port B pull-down bit
bits : 14 - 14 (1 bit)
access : read-write
PD15 : Port B pull-down bit
bits : 15 - 15 (1 bit)
access : read-write
PWR port C pull-up control register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PU0 : Port C pull-up bit
bits : 0 - 0 (1 bit)
access : read-write
PU1 : Port C pull-up bit
bits : 1 - 1 (1 bit)
access : read-write
PU2 : Port C pull-up bit
bits : 2 - 2 (1 bit)
access : read-write
PU3 : Port C pull-up bit
bits : 3 - 3 (1 bit)
access : read-write
PU4 : Port C pull-up bit
bits : 4 - 4 (1 bit)
access : read-write
PU5 : Port C pull-up bit
bits : 5 - 5 (1 bit)
access : read-write
PU6 : Port C pull-up bit
bits : 6 - 6 (1 bit)
access : read-write
PU7 : Port C pull-up bit
bits : 7 - 7 (1 bit)
access : read-write
PU8 : Port C pull-up bit
bits : 8 - 8 (1 bit)
access : read-write
PU9 : Port C pull-up bit
bits : 9 - 9 (1 bit)
access : read-write
PU10 : Port C pull-up bit
bits : 10 - 10 (1 bit)
access : read-write
PU11 : Port C pull-up bit
bits : 11 - 11 (1 bit)
access : read-write
PU12 : Port C pull-up bit
bits : 12 - 12 (1 bit)
access : read-write
PU13 : Port C pull-up bit
bits : 13 - 13 (1 bit)
access : read-write
PU14 : Port C pull-up bit
bits : 14 - 14 (1 bit)
access : read-write
PU15 : Port C pull-up bit
bits : 15 - 15 (1 bit)
access : read-write
PWR port C pull-down control register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD0 : Port C pull-down bit
bits : 0 - 0 (1 bit)
access : read-write
PD1 : Port C pull-down bit
bits : 1 - 1 (1 bit)
access : read-write
PD2 : Port C pull-down bit
bits : 2 - 2 (1 bit)
access : read-write
PD3 : Port C pull-down bit
bits : 3 - 3 (1 bit)
access : read-write
PD4 : Port C pull-down bit
bits : 4 - 4 (1 bit)
access : read-write
PD5 : Port C pull-down bit
bits : 5 - 5 (1 bit)
access : read-write
PD6 : Port C pull-down bit
bits : 6 - 6 (1 bit)
access : read-write
PD7 : Port C pull-down bit
bits : 7 - 7 (1 bit)
access : read-write
PD8 : Port C pull-down bit
bits : 8 - 8 (1 bit)
access : read-write
PD9 : Port C pull-down bit
bits : 9 - 9 (1 bit)
access : read-write
PD10 : Port C pull-down bit
bits : 10 - 10 (1 bit)
access : read-write
PD11 : Port C pull-down bit
bits : 11 - 11 (1 bit)
access : read-write
PD12 : Port C pull-down bit
bits : 12 - 12 (1 bit)
access : read-write
PD13 : Port C pull-down bit
bits : 13 - 13 (1 bit)
access : read-write
PD14 : Port C pull-down bit
bits : 14 - 14 (1 bit)
access : read-write
PD15 : Port C pull-down bit
bits : 15 - 15 (1 bit)
access : read-write
PWR port D pull-up control register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PU0 : Port D pull-up bit
bits : 0 - 0 (1 bit)
access : read-write
PU1 : Port D pull-up bit
bits : 1 - 1 (1 bit)
access : read-write
PU2 : Port D pull-up bit
bits : 2 - 2 (1 bit)
access : read-write
PU3 : Port D pull-up bit
bits : 3 - 3 (1 bit)
access : read-write
PU4 : Port D pull-up bit
bits : 4 - 4 (1 bit)
access : read-write
PU5 : Port D pull-up bit
bits : 5 - 5 (1 bit)
access : read-write
PU6 : Port D pull-up bit
bits : 6 - 6 (1 bit)
access : read-write
PU7 : Port D pull-up bit
bits : 7 - 7 (1 bit)
access : read-write
PU8 : Port D pull-up bit
bits : 8 - 8 (1 bit)
access : read-write
PU9 : Port D pull-up bit
bits : 9 - 9 (1 bit)
access : read-write
PU10 : Port D pull-up bit
bits : 10 - 10 (1 bit)
access : read-write
PU11 : Port D pull-up bit
bits : 11 - 11 (1 bit)
access : read-write
PU12 : Port D pull-up bit
bits : 12 - 12 (1 bit)
access : read-write
PU13 : Port D pull-up bit
bits : 13 - 13 (1 bit)
access : read-write
PU14 : Port D pull-up bit
bits : 14 - 14 (1 bit)
access : read-write
PU15 : Port D pull-up bit
bits : 15 - 15 (1 bit)
access : read-write
PWR port D pull-down control register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD0 : Port D pull-down bit
bits : 0 - 0 (1 bit)
access : read-write
PD1 : Port D pull-down bit
bits : 1 - 1 (1 bit)
access : read-write
PD2 : Port D pull-down bit
bits : 2 - 2 (1 bit)
access : read-write
PD3 : Port D pull-down bit
bits : 3 - 3 (1 bit)
access : read-write
PD4 : Port D pull-down bit
bits : 4 - 4 (1 bit)
access : read-write
PD5 : Port D pull-down bit
bits : 5 - 5 (1 bit)
access : read-write
PD6 : Port D pull-down bit
bits : 6 - 6 (1 bit)
access : read-write
PD7 : Port D pull-down bit
bits : 7 - 7 (1 bit)
access : read-write
PD8 : Port D pull-down bit
bits : 8 - 8 (1 bit)
access : read-write
PD9 : Port D pull-down bit
bits : 9 - 9 (1 bit)
access : read-write
PD10 : Port D pull-down bit
bits : 10 - 10 (1 bit)
access : read-write
PD11 : Port D pull-down bit
bits : 11 - 11 (1 bit)
access : read-write
PD12 : Port D pull-down bit
bits : 12 - 12 (1 bit)
access : read-write
PD13 : Port D pull-down bit
bits : 13 - 13 (1 bit)
access : read-write
PD14 : Port D pull-down bit
bits : 14 - 14 (1 bit)
access : read-write
PD15 : Port D pull-down bit
bits : 15 - 15 (1 bit)
access : read-write
PWR port E pull-up control register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PU0 : Port E pull-up bit
bits : 0 - 0 (1 bit)
access : read-write
PU1 : Port E pull-up bit
bits : 1 - 1 (1 bit)
access : read-write
PU2 : Port E pull-up bit
bits : 2 - 2 (1 bit)
access : read-write
PU3 : Port E pull-up bit
bits : 3 - 3 (1 bit)
access : read-write
PU4 : Port E pull-up bit
bits : 4 - 4 (1 bit)
access : read-write
PU5 : Port E pull-up bit
bits : 5 - 5 (1 bit)
access : read-write
PU6 : Port E pull-up bit
bits : 6 - 6 (1 bit)
access : read-write
PU7 : Port E pull-up bit
bits : 7 - 7 (1 bit)
access : read-write
PU8 : Port E pull-up bit
bits : 8 - 8 (1 bit)
access : read-write
PU9 : Port E pull-up bit
bits : 9 - 9 (1 bit)
access : read-write
PU10 : Port E pull-up bit
bits : 10 - 10 (1 bit)
access : read-write
PU11 : Port E pull-up bit
bits : 11 - 11 (1 bit)
access : read-write
PU12 : Port E pull-up bit
bits : 12 - 12 (1 bit)
access : read-write
PU13 : Port E pull-up bit
bits : 13 - 13 (1 bit)
access : read-write
PU14 : Port E pull-up bit
bits : 14 - 14 (1 bit)
access : read-write
PU15 : Port E pull-up bit
bits : 15 - 15 (1 bit)
access : read-write
PWR port E pull-down control register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD0 : Port E pull-down bit
bits : 0 - 0 (1 bit)
access : read-write
PD1 : Port E pull-down bit
bits : 1 - 1 (1 bit)
access : read-write
PD2 : Port E pull-down bit
bits : 2 - 2 (1 bit)
access : read-write
PD3 : Port E pull-down bit
bits : 3 - 3 (1 bit)
access : read-write
PD4 : Port E pull-down bit
bits : 4 - 4 (1 bit)
access : read-write
PD5 : Port E pull-down bit
bits : 5 - 5 (1 bit)
access : read-write
PD6 : Port E pull-down bit
bits : 6 - 6 (1 bit)
access : read-write
PD7 : Port E pull-down bit
bits : 7 - 7 (1 bit)
access : read-write
PD8 : Port E pull-down bit
bits : 8 - 8 (1 bit)
access : read-write
PD9 : Port E pull-down bit
bits : 9 - 9 (1 bit)
access : read-write
PD10 : Port E pull-down bit
bits : 10 - 10 (1 bit)
access : read-write
PD11 : Port E pull-down bit
bits : 11 - 11 (1 bit)
access : read-write
PD12 : Port E pull-down bit
bits : 12 - 12 (1 bit)
access : read-write
PD13 : Port E pull-down bit
bits : 13 - 13 (1 bit)
access : read-write
PD14 : Port E pull-down bit
bits : 14 - 14 (1 bit)
access : read-write
PD15 : Port E pull-down bit
bits : 15 - 15 (1 bit)
access : read-write
PWR port F pull-up control register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PU0 : Port F pull-up bit
bits : 0 - 0 (1 bit)
access : read-write
PU1 : Port F pull-up bit
bits : 1 - 1 (1 bit)
access : read-write
PU2 : Port F pull-up bit
bits : 2 - 2 (1 bit)
access : read-write
PU3 : Port F pull-up bit
bits : 3 - 3 (1 bit)
access : read-write
PU4 : Port F pull-up bit
bits : 4 - 4 (1 bit)
access : read-write
PU5 : Port F pull-up bit
bits : 5 - 5 (1 bit)
access : read-write
PU6 : Port F pull-up bit
bits : 6 - 6 (1 bit)
access : read-write
PU7 : Port F pull-up bit
bits : 7 - 7 (1 bit)
access : read-write
PU8 : Port F pull-up bit
bits : 8 - 8 (1 bit)
access : read-write
PU9 : Port F pull-up bit
bits : 9 - 9 (1 bit)
access : read-write
PU10 : Port F pull-up bit
bits : 10 - 10 (1 bit)
access : read-write
PU11 : Port F pull-up bit
bits : 11 - 11 (1 bit)
access : read-write
PU12 : Port F pull-up bit
bits : 12 - 12 (1 bit)
access : read-write
PU13 : Port F pull-up bit
bits : 13 - 13 (1 bit)
access : read-write
PU14 : Port F pull-up bit
bits : 14 - 14 (1 bit)
access : read-write
PU15 : Port F pull-up bit
bits : 15 - 15 (1 bit)
access : read-write
PWR port F pull-down control register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD0 : Port F pull-down bit
bits : 0 - 0 (1 bit)
access : read-write
PD1 : Port F pull-down bit
bits : 1 - 1 (1 bit)
access : read-write
PD2 : Port F pull-down bit
bits : 2 - 2 (1 bit)
access : read-write
PD3 : Port F pull-down bit
bits : 3 - 3 (1 bit)
access : read-write
PD4 : Port F pull-down bit
bits : 4 - 4 (1 bit)
access : read-write
PD5 : Port F pull-down bit
bits : 5 - 5 (1 bit)
access : read-write
PD6 : Port F pull-down bit
bits : 6 - 6 (1 bit)
access : read-write
PD7 : Port F pull-down bit
bits : 7 - 7 (1 bit)
access : read-write
PD8 : Port F pull-down bit
bits : 8 - 8 (1 bit)
access : read-write
PD9 : Port F pull-down bit
bits : 9 - 9 (1 bit)
access : read-write
PD10 : Port F pull-down bit
bits : 10 - 10 (1 bit)
access : read-write
PD11 : Port F pull-down bit
bits : 11 - 11 (1 bit)
access : read-write
PD12 : Port F pull-down bit
bits : 12 - 12 (1 bit)
access : read-write
PD13 : Port F pull-down bit
bits : 13 - 13 (1 bit)
access : read-write
PD14 : Port F pull-down bit
bits : 14 - 14 (1 bit)
access : read-write
PD15 : Port F pull-down bit
bits : 15 - 15 (1 bit)
access : read-write
PWR control register 3
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGSEL : Regulator selection Note: REGSEL is reserved and must be kept at reset value in packages without SMPS.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LDO selected
0x1 : B_0x1
SMPS selected
End of enumeration elements list.
FSTEN : Fast soft start
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LDO/SMPS fast startup disabled (limited inrush current)
0x1 : B_0x1
LDO/SMPS fast startup enabled
End of enumeration elements list.
PWR port G pull-up control register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PU0 : Port G pull-up bit
bits : 0 - 0 (1 bit)
access : read-write
PU1 : Port G pull-up bit
bits : 1 - 1 (1 bit)
access : read-write
PU2 : Port G pull-up bit
bits : 2 - 2 (1 bit)
access : read-write
PU3 : Port G pull-up bit
bits : 3 - 3 (1 bit)
access : read-write
PU4 : Port G pull-up bit
bits : 4 - 4 (1 bit)
access : read-write
PU5 : Port G pull-up bit
bits : 5 - 5 (1 bit)
access : read-write
PU6 : Port G pull-up bit
bits : 6 - 6 (1 bit)
access : read-write
PU7 : Port G pull-up bit
bits : 7 - 7 (1 bit)
access : read-write
PU8 : Port G pull-up bit
bits : 8 - 8 (1 bit)
access : read-write
PU9 : Port G pull-up bit
bits : 9 - 9 (1 bit)
access : read-write
PU10 : Port G pull-up bit
bits : 10 - 10 (1 bit)
access : read-write
PU11 : Port G pull-up bit
bits : 11 - 11 (1 bit)
access : read-write
PU12 : Port G pull-up bit
bits : 12 - 12 (1 bit)
access : read-write
PU13 : Port G pull-up bit
bits : 13 - 13 (1 bit)
access : read-write
PU14 : Port G pull-up bit
bits : 14 - 14 (1 bit)
access : read-write
PU15 : Port G pull-up bit
bits : 15 - 15 (1 bit)
access : read-write
PWR port G pull-down control register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD0 : Port G pull-down bit
bits : 0 - 0 (1 bit)
access : read-write
PD1 : Port G pull-down bit
bits : 1 - 1 (1 bit)
access : read-write
PD2 : Port G pull-down bit
bits : 2 - 2 (1 bit)
access : read-write
PD3 : Port G pull-down bit
bits : 3 - 3 (1 bit)
access : read-write
PD4 : Port G pull-down bit
bits : 4 - 4 (1 bit)
access : read-write
PD5 : Port G pull-down bit
bits : 5 - 5 (1 bit)
access : read-write
PD6 : Port G pull-down bit
bits : 6 - 6 (1 bit)
access : read-write
PD7 : Port G pull-down bit
bits : 7 - 7 (1 bit)
access : read-write
PD8 : Port G pull-down bit
bits : 8 - 8 (1 bit)
access : read-write
PD9 : Port G pull-down bit
bits : 9 - 9 (1 bit)
access : read-write
PD10 : Port G pull-down bit
bits : 10 - 10 (1 bit)
access : read-write
PD11 : Port G pull-down bit
bits : 11 - 11 (1 bit)
access : read-write
PD12 : Port G pull-down bit
bits : 12 - 12 (1 bit)
access : read-write
PD13 : Port G pull-down bit
bits : 13 - 13 (1 bit)
access : read-write
PD14 : Port G pull-down bit
bits : 14 - 14 (1 bit)
access : read-write
PD15 : Port G pull-down bit
bits : 15 - 15 (1 bit)
access : read-write
PWR port H pull-up control register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PU0 : Port H pull-up bit
bits : 0 - 0 (1 bit)
access : read-write
PU1 : Port H pull-up bit
bits : 1 - 1 (1 bit)
access : read-write
PU2 : Port H pull-up bit
bits : 2 - 2 (1 bit)
access : read-write
PU3 : Port H pull-up bit
bits : 3 - 3 (1 bit)
access : read-write
PU4 : Port H pull-up bit
bits : 4 - 4 (1 bit)
access : read-write
PU5 : Port H pull-up bit
bits : 5 - 5 (1 bit)
access : read-write
PU6 : Port H pull-up bit
bits : 6 - 6 (1 bit)
access : read-write
PU7 : Port H pull-up bit
bits : 7 - 7 (1 bit)
access : read-write
PU8 : Port H pull-up bit
bits : 8 - 8 (1 bit)
access : read-write
PU9 : Port H pull-up bit
bits : 9 - 9 (1 bit)
access : read-write
PU10 : Port H pull-up bit
bits : 10 - 10 (1 bit)
access : read-write
PU11 : Port H pull-up bit
bits : 11 - 11 (1 bit)
access : read-write
PU12 : Port H pull-up bit
bits : 12 - 12 (1 bit)
access : read-write
PU13 : Port H pull-up bit
bits : 13 - 13 (1 bit)
access : read-write
PU14 : Port H pull-up bit
bits : 14 - 14 (1 bit)
access : read-write
PU15 : Port H pull-up bit
bits : 15 - 15 (1 bit)
access : read-write
PWR port H pull-down control register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD0 : Port H pull-down bit
bits : 0 - 0 (1 bit)
access : read-write
PD1 : Port H pull-down bit
bits : 1 - 1 (1 bit)
access : read-write
PD2 : Port H pull-down bit
bits : 2 - 2 (1 bit)
access : read-write
PD3 : Port H pull-down bit
bits : 3 - 3 (1 bit)
access : read-write
PD4 : Port H pull-down bit
bits : 4 - 4 (1 bit)
access : read-write
PD5 : Port H pull-down bit
bits : 5 - 5 (1 bit)
access : read-write
PD6 : Port H pull-down bit
bits : 6 - 6 (1 bit)
access : read-write
PD7 : Port H pull-down bit
bits : 7 - 7 (1 bit)
access : read-write
PD8 : Port H pull-down bit
bits : 8 - 8 (1 bit)
access : read-write
PD9 : Port H pull-down bit
bits : 9 - 9 (1 bit)
access : read-write
PD10 : Port H pull-down bit
bits : 10 - 10 (1 bit)
access : read-write
PD11 : Port H pull-down bit
bits : 11 - 11 (1 bit)
access : read-write
PD12 : Port H pull-down bit
bits : 12 - 12 (1 bit)
access : read-write
PD13 : Port H pull-down bit
bits : 13 - 13 (1 bit)
access : read-write
PD14 : Port H pull-down bit
bits : 14 - 14 (1 bit)
access : read-write
PD15 : Port H pull-down bit
bits : 15 - 15 (1 bit)
access : read-write
PWR port I pull-up control register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PU0 : Port I pull-up bit
bits : 0 - 0 (1 bit)
access : read-write
PU1 : Port I pull-up bit
bits : 1 - 1 (1 bit)
access : read-write
PU2 : Port I pull-up bit
bits : 2 - 2 (1 bit)
access : read-write
PU3 : Port I pull-up bit
bits : 3 - 3 (1 bit)
access : read-write
PU4 : Port I pull-up bit
bits : 4 - 4 (1 bit)
access : read-write
PU5 : Port I pull-up bit
bits : 5 - 5 (1 bit)
access : read-write
PU6 : Port I pull-up bit
bits : 6 - 6 (1 bit)
access : read-write
PU7 : Port I pull-up bit
bits : 7 - 7 (1 bit)
access : read-write
PWR port I pull-down control register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD0 : Port I pull-down bit
bits : 0 - 0 (1 bit)
access : read-write
PD1 : Port I pull-down bit
bits : 1 - 1 (1 bit)
access : read-write
PD2 : Port I pull-down bit
bits : 2 - 2 (1 bit)
access : read-write
PD3 : Port I pull-down bit
bits : 3 - 3 (1 bit)
access : read-write
PD4 : Port I pull-down bit
bits : 4 - 4 (1 bit)
access : read-write
PD5 : Port I pull-down bit
bits : 5 - 5 (1 bit)
access : read-write
PD6 : Port I pull-down bit
bits : 6 - 6 (1 bit)
access : read-write
PD7 : Port I pull-down bit
bits : 7 - 7 (1 bit)
access : read-write
PWR voltage scaling register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOSTRDY : EPOD booster ready This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 50 MHz only after this bit is set.
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Power booster not ready
0x1 : B_0x1
Power booster ready
End of enumeration elements list.
VOSRDY : Ready bit for VCORE voltage scaling output selection
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
Not ready, voltage level < VOS selected level
0x1 : B_0x1
Ready, voltage level ≥ VOS selected level
End of enumeration elements list.
VOS : Voltage scaling range selection This field is protected against non-secure access when SYSCLKSEC = 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC = 1 in RCC_SECCFGR and SPRIV = 1 in PWR_PRIVCFGR, or when SYSCLKSEC = 0 and NSPRIV = 1.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Range 4 (lowest power)
0x1 : B_0x1
Range 3
0x2 : B_0x2
Range 2
0x3 : B_0x3
Range 1 (highest frequency). This value cannot be written when VCOREMEN = 1 in TAMP_OR register.
End of enumeration elements list.
BOOSTEN : EPOD booster enable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Booster disabled
0x1 : B_0x1
Booster enabled
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.