Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
RCC clock control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSISON : MSIS clock enable Set and cleared by software. Cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSIS oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator. Set by hardware when used directly or indirectly as system clock.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
MSIS (MSI system) oscillator OFF
0x1 : B_0x1
MSIS (MSI system) oscillator ON
End of enumeration elements list.
MSIKERON : MSI enable for some peripheral kernels Set and cleared by software to force MSI ON even in Stop modes. Keeping the MSI ON in Stop mode allows the communication speed not to be reduced by the MSI startup time. This bit has no effect on MSISON and MSIKON values (see autonomous mode for more details). The MSIKERON must be configured at 0 before entering Stop 3 mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect on MSI oscillator
0x1 : B_0x1
MSI oscillator forced ON even in Stop mode
End of enumeration elements list.
MSISRDY : MSIS clock ready flag Set by hardware to indicate that the MSIS oscillator is stable. This bit is set only when MSIS is enabled by software by setting MSISON. Note: Once the MSISON bit is cleared, MSISRDY goes low after six MSIS clock cycles.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
MSIS (MSI system) oscillator not ready
0x1 : B_0x1
MSIS (MSI system) oscillator ready
End of enumeration elements list.
MSIPLLEN : MSI clock PLL-mode enable Set and cleared by software to enable/disable the PLL part of the MSI clock source. MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). A hardware protection prevents from enabling MSIPLLEN if LSE is not ready. This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE detects a LSE failure (see RCC_CSR).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
MSI PLL-mode OFF
0x1 : B_0x1
MSI PLL-mode ON
End of enumeration elements list.
MSIKON : MSIK clock enable Set and cleared by software. Cleared by hardware to stop the MSIK when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSIK oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSIK oscillator ON when STOPWUCK = 0 or STOPKERWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
MSIK (MSI kernel) oscillator disabled
0x1 : B_0x1
MSIK (MSI kernel) oscillator enabled
End of enumeration elements list.
MSIKRDY : MSIK clock ready flag Set by hardware to indicate that the MSIK is stable. This bit is set only when MSI kernel oscillator is enabled by software by setting MSIKON. Note: Once the MSIKON bit is cleared, MSIKRDY goes low after six MSIK oscillator clock cycles.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
MSIK (MSI kernel) oscillator not ready
0x1 : B_0x1
MSIK (MSI kernel) oscillator ready
End of enumeration elements list.
MSIPLLSEL : MSI clock with PLL mode selection Set and cleared by software to select which MSI output clock uses the PLL mode. This bit can be written only when the MSI PLL mode is disabled (MSIPLLEN = 0). Note: If the MSI kernel clock output uses the same oscillator source than the MSI system clock output, then the PLL mode is applied to the both clocks outputs.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL mode applied to MSIK (MSI kernel) clock output
0x1 : B_0x1
PLL mode applied to MSIS (MSI system) clock output
End of enumeration elements list.
MSIPLLFAST : MSI PLL mode fast startup Set and reset by software to enable/disable the fast PLL mode start-up of the MSI clock source. This bit is used only if PLL mode is selected (MSIPLLEN = 1). The fast start-up feature is not active the first time the PLL mode is selected. The fast start-up is active when the MSI in PLL mode returns from switch off.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
MSI PLL normal start-up
0x1 : B_0x1
MSI PLL fast start-up
End of enumeration elements list.
HSION : HSI16 clock enable Set and cleared by software. Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the HSI16 oscillator ON when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator. This bit is set by hardware if the HSI16 is used directly or indirectly as system clock.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSI16 oscillator OFF
0x1 : B_0x1
HSI16 oscillator ON
End of enumeration elements list.
HSIKERON : HSI16 enable for some peripheral kernels Set and cleared by software to force HSI16 ON even in Stop modes. Keeping the HSI16 ON in Stop mode allows the communication speed not to be reduced by the HSI16 startup time. This bit has no effect on HSION value. Refer to for more details. The HSIKERON must be configured at 0 before entering Stop 3 mode.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect on HSI16 oscillator
0x1 : B_0x1
HSI16 oscillator forced ON even in Stop mode
End of enumeration elements list.
HSIRDY : HSI16 clock ready flag Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION. Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI16 clock cycles.
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
HSI16 oscillator not ready
0x1 : B_0x1
HSI16 oscillator ready
End of enumeration elements list.
HSI48ON : HSI48 clock enable Set and cleared by software. Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSI48 oscillator OFF
0x1 : B_0x1
HSI48 oscillator ON
End of enumeration elements list.
HSI48RDY : HSI48 clock ready flag Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON.
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
HSI48 oscillator not ready
0x1 : B_0x1
HSI48 oscillator ready
End of enumeration elements list.
SHSION : SHSI clock enable Set and cleared by software. Cleared by hardware to stop the SHSI when entering in Stop, Standby or Shutdown modes.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SHSI oscillator OFF
0x1 : B_0x1
SHSI oscillator ON
End of enumeration elements list.
SHSIRDY : SHSI clock ready flag Set by hardware to indicate that the SHSI oscillator is stable. This bit is set only when SHSI is enabled by software by setting SHSION. Note: Once the SHSION bit is cleared, SHSIRDY goes low after six SHSI clock cycles.
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
SHSI oscillator not ready
0x1 : B_0x1
SHSI oscillator ready
End of enumeration elements list.
HSEON : HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSE oscillator OFF
0x1 : B_0x1
HSE oscillator ON
End of enumeration elements list.
HSERDY : HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
HSE oscillator not ready
0x1 : B_0x1
HSE oscillator ready
End of enumeration elements list.
HSEBYP : HSE crystal oscillator bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSE crystal oscillator not bypassed
0x1 : B_0x1
HSE crystal oscillator bypassed with external clock
End of enumeration elements list.
CSSON : Clock security system enable Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
clock security system OFF (clock detector OFF)
0x1 : B_0x1
clock security system ON (clock detector ON if the HSE oscillator is stable, OFF if not).
End of enumeration elements list.
HSEEXT : HSE external clock bypass mode Set and reset by software to select the external clock mode in bypass mode. External clock mode must be configured with HSEON bit to be used by the device. This bit can be written only if the HSE oscillator is disabled. This bit is active only if the HSE bypass mode is enabled.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
external HSE clock analog mode
0x1 : B_0x1
external HSE clock digital mode (through I/O Schmitt trigger)
End of enumeration elements list.
PLL1ON : PLL1 enable Set and cleared by software to enable the main PLL. Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL1 OFF
0x1 : B_0x1
PLL1 ON
End of enumeration elements list.
PLL1RDY : PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked.
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
PLL1 unlocked
0x1 : B_0x1
PLL1 locked
End of enumeration elements list.
PLL2ON : PLL2 enable Set and cleared by software to enable PLL2. Cleared by hardware when entering Stop, Standby or Shutdown mode.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL2 OFF
0x1 : B_0x1
PLL2 ON
End of enumeration elements list.
PLL2RDY : PLL2 clock ready flag Set by hardware to indicate that the PLL2 is locked.
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
PLL2 unlocked
0x1 : B_0x1
PLL2 locked
End of enumeration elements list.
PLL3ON : PLL3 enable Set and cleared by software to enable PLL3. Cleared by hardware when entering Stop, Standby or Shutdown mode.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL3 OFF
0x1 : B_0x1
PLL3 ON
End of enumeration elements list.
PLL3RDY : PLL3 clock ready flag Set by hardware to indicate that the PLL3 is locked.
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
PLL3 unlocked
0x1 : B_0x1
PLL3 locked
End of enumeration elements list.
RCC internal clock sources calibration register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSICAL : HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value.
bits : 0 - 11 (12 bit)
access : read-only
HSITRIM : HSI clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI.
bits : 16 - 20 (5 bit)
access : read-write
RCC secure configuration register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSISEC : HSI clock configuration and status bits security Set and reset by software.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
non secure
0x1 : B_0x1
secure
End of enumeration elements list.
HSESEC : HSE clock configuration bits, status bits and HSE_CSS security Set and reset by software.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
non secure
0x1 : B_0x1
secure
End of enumeration elements list.
MSISEC : MSI clock configuration and status bits security Set and reset by software.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
non secure
0x1 : B_0x1
secure
End of enumeration elements list.
LSISEC : LSI clock configuration and status bits security Set and reset by software.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
non secure
0x1 : B_0x1
secure
End of enumeration elements list.
LSESEC : LSE clock configuration and status bits security Set and reset by software.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
non secure
0x1 : B_0x1
secure
End of enumeration elements list.
SYSCLKSEC : SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security Set and reset by software.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
non secure
0x1 : B_0x1
secure
End of enumeration elements list.
PRESCSEC : AHBx/APBx prescaler configuration bits security Set and reset by software.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
non secure
0x1 : B_0x1
secure
End of enumeration elements list.
PLL1SEC : PLL1 clock configuration and status bits security Set and reset by software.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
non secure
0x1 : B_0x1
secure
End of enumeration elements list.
PLL2SEC : PLL2 clock configuration and status bits security Set and reset by software.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
non secure
0x1 : B_0x1
secure
End of enumeration elements list.
PLL3SEC : PLL3 clock configuration and status bits security Set and reset by software.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
non secure
0x1 : B_0x1
secure
End of enumeration elements list.
ICLKSEC : intermediate clock source selection security Set and reset by software.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
non secure
0x1 : B_0x1
secure
End of enumeration elements list.
HSI48SEC : HSI48 clock configuration and status bits security Set and reset by software.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
non secure
0x1 : B_0x1
secure
End of enumeration elements list.
RMVFSEC : Remove reset flag security Set and reset by software.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
non secure
0x1 : B_0x1
secure
End of enumeration elements list.
RCC privilege configuration register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPRIV : RCC secure functions privilege configuration Set and reset by software. This bit can be written only by a secure privileged access.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Read and write to RCC secure functions can be done by privileged or unprivileged access.
0x1 : B_0x1
Read and write to RCC secure functions can be done by privileged access only.
End of enumeration elements list.
NSPRIV : RCC non-secure functions privilege configuration Set and reset by software. This bit can be written only by privileged access, secure or non-secure.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Read and write to RCC non-secure functions can be done by privileged or unprivileged access.
0x1 : B_0x1
Read and write to RCC non-secure functions can be done by privileged access only.
End of enumeration elements list.
RCC clock recovery RC register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSI48CAL : HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value.
bits : 0 - 8 (9 bit)
access : read-only
RCC clock configuration register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW : system clock switch Set and cleared by software to select system clock source (SYSCLK). Configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. Configured by hardware to force MSIS or HSI16 oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK value.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
MSIS selected as system clock
0x1 : B_0x1
HSI16 selected as system clock
0x2 : B_0x2
HSE selected as system clock
0x3 : B_0x3
PLL pll1_r_ck selected as system clock
End of enumeration elements list.
SWS : system clock switch status Set and cleared by hardware to indicate which clock source is used as system clock.
bits : 2 - 3 (2 bit)
access : read-only
Enumeration:
0x0 : B_0x0
MSIS oscillator used as system clock
0x1 : B_0x1
HSI16 oscillator used as system clock
0x2 : B_0x2
HSE used as system clock
0x3 : B_0x3
PLL pll1_r_ck used as system clock
End of enumeration elements list.
STOPWUCK : wakeup from Stop and CSS backup clock selection Set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the clock security system on HSE. Warning: STOPWUCK must not be modified when the CSS is enabled by HSECSSON bit in RCC_CR and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW = 10).
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
MSIS oscillator selected as wakeup from stop clock and CSS backup clock
0x1 : B_0x1
HSI16 oscillator selected as wakeup from stop clock and CSS backup clock
End of enumeration elements list.
STOPKERWUCK : wakeup from Stop kernel clock automatic enable selection Set and cleared by software to enable automatically another oscillator when exiting Stop mode. This oscillator can be used as independent kernel clock by peripherals.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
MSIK oscillator automatically enabled when exiting Stop mode
0x1 : B_0x1
HSI16 oscillator automatically enabled when exiting Stop mode
End of enumeration elements list.
MCOSEL : microcontroller clock output Set and cleared by software. Others: reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching.
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
MCO output disabled, no clock on MCO
0x1 : B_0x1
SYSCLK system clock selected
0x2 : B_0x2
MSIS clock selected
0x3 : B_0x3
HSI16 clock selected
0x4 : B_0x4
HSE clock selected
0x5 : B_0x5
Main PLL clock pll1_r_ck selected
0x6 : B_0x6
LSI clock selected
0x7 : B_0x7
LSE clock selected
0x8 : B_0x8
Internal HSI48 clock selected
0x9 : B_0x9
MSIK clock selected
End of enumeration elements list.
MCOPRE : microcontroller clock output prescaler Set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. Others: not allowed
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
MCO divided by 1
0x1 : B_0x1
MCO divided by 2
0x2 : B_0x2
MCO divided by 4
0x3 : B_0x3
MCO divided by 8
0x4 : B_0x4
MCO divided by 16
End of enumeration elements list.
RCC clock configuration register 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPRE : AHB prescaler Set and cleared by software to control the division factor of the AHB clock (HCLK). Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to ). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xxx: SYSCLK not divided
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x8 : B_0x8
SYSCLK divided by 2
0x9 : B_0x9
SYSCLK divided by 4
0xA : B_0xA
SYSCLK divided by 8
0xB : B_0xB
SYSCLK divided by 16
0xC : B_0xC
SYSCLK divided by 64
0xD : B_0xD
SYSCLK divided by 128
0xE : B_0xE
SYSCLK divided by 256
0xF : B_0xF
SYSCLK divided by 512
End of enumeration elements list.
PPRE1 : APB1 prescaler Set and cleared by software to control the division factor of the APB1 clock (PCLK1). 0xx: HCLK not divided
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x4 : B_0x4
HCLK divided by 2
0x5 : B_0x5
HCLK divided by 4
0x6 : B_0x6
HCLK divided by 8
0x7 : B_0x7
HCLK divided by 16
End of enumeration elements list.
PPRE2 : APB2 prescaler Set and cleared by software to control the division factor of the APB2 clock (PCLK2). 0xx: HCLK not divided
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x4 : B_0x4
HCLK divided by 2
0x5 : B_0x5
HCLK divided by 4
0x6 : B_0x6
HCLK divided by 8
0x7 : B_0x7
HCLK divided by 16
End of enumeration elements list.
AHB1DIS : AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
AHB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits
0x1 : B_0x1
AHB1 clock disabled
End of enumeration elements list.
AHB2DIS1 : AHB2_1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
AHB2_1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits
0x1 : B_0x1
AHB2_1 clock disabled
End of enumeration elements list.
AHB2DIS2 : AHB2_2 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2EBNR2 are off.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
AHB2_2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits
0x1 : B_0x1
AHB2_2 clock disabled
End of enumeration elements list.
APB1DIS : APB1 clock disable This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
APB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits
0x1 : B_0x1
APB1 clock disabled
End of enumeration elements list.
APB2DIS : APB2 clock disable This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
APB2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits
0x1 : B_0x1
APB2 clock disabled
End of enumeration elements list.
RCC clock configuration register 3
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPRE3 : APB3 prescaler Set and cleared by software to control the division factor of the APB3 clock (PCLK3). 0xx: HCLK not divided
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x4 : B_0x4
HCLK divided by 2
0x5 : B_0x5
HCLK divided by 4
0x6 : B_0x6
HCLK divided by 8
0x7 : B_0x7
HCLK divided by 16
End of enumeration elements list.
AHB3DIS : AHB3 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
AHB3 clock enabled, distributed to peripherals according to their dedicated clock enable control bits
0x1 : B_0x1
AHB3 clock disabled
End of enumeration elements list.
APB3DIS : APB3 clock disable This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
APB3 clock enabled, distributed to peripherals according to their dedicated clock enable control bits
0x1 : B_0x1
APB3 clock disabled
End of enumeration elements list.
RCC PLL1 configuration register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL1SRC : PLL1 entry clock source Set and cleared by software to select PLL1 clock source. These bits can be written only when the PLL1 is disabled. In order to save power, when no PLL1 is used, the value of PLL1SRC must be 0.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock sent to PLL1
0x1 : B_0x1
MSIS clock selected as PLL1 clock entry
0x2 : B_0x2
HSI16 clock selected as PLL1 clock entry
0x3 : B_0x3
HSE clock selected as PLL1 clock entry
End of enumeration elements list.
PLL1RGE : PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x3 : B_0x3
PLL1 input (ref1_ck) clock range frequency between 8 and 16 MHz
End of enumeration elements list.
PLL1FRACEN : PLL1 fractional latch enable Set and reset by software to latch the content of PLL1FRACN into the ΣΠmodulator. In order to latch the PLL1FRACN value into the ΣΠmodulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see for details).
bits : 4 - 4 (1 bit)
access : read-write
PLL1M : Prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ...
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
division by 1 (bypass)
0x1 : B_0x1
division by 2
0x2 : B_0x2
division by 3
0xF : B_0xF
division by 16
End of enumeration elements list.
PLL1MBOOST : Prescaler for EPOD booster input clock Set and cleared by software to configure the prescaler of the PLL1, used for the EPOD booster. The EPOD booster input frequency is PLL1 input clock frequency/PLL1MBOOST. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0) and EPOD Boost mode is disabled (see ). others: reserved
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
division by 1 (bypass)
0x1 : B_0x1
division by 2
0x2 : B_0x2
division by 4
0x3 : B_0x3
division by 6
0x4 : B_0x4
division by 8
0x5 : B_0x5
division by 10
0x6 : B_0x6
division by 12
0x7 : B_0x7
division by 14
0x8 : B_0x8
division by 16
End of enumeration elements list.
PLL1PEN : PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. To save power, PLL1PEN and PLL1P bits must be set to 0 when the pll1_p_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll1_p_ck output disabled
0x1 : B_0x1
pll1_p_ck output enabled
End of enumeration elements list.
PLL1QEN : PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. To save power, PLL1QEN and PLL1Q bits must be set to 0 when the pll1_q_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll1_q_ck output disabled
0x1 : B_0x1
pll1_q_ck output enabled
End of enumeration elements list.
PLL1REN : PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1RENPLL2REN and PLL1R bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll1_r_ck output disabled
0x1 : B_0x1
pll1_r_ck output enabled
End of enumeration elements list.
RCC PLL2 configuration register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL2SRC : PLL2 entry clock source Set and cleared by software to select PLL2 clock source. These bits can be written only when the PLL2 is disabled. In order to save power, when no PLL2 is used, the value of PLL2SRC must be 0.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock sent to PLL2
0x1 : B_0x1
MSIS clock selected as PLL2 clock entry
0x2 : B_0x2
HSI16 clock selected as PLL2 clock entry
0x3 : B_0x3
HSE clock selected as PLL2 clock entry
End of enumeration elements list.
PLL2RGE : PLL2 input frequency range Set and reset by software to select the proper reference frequency range used for PLL2. This bit must be written before enabling the PLL2. 00-01-10: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x3 : B_0x3
PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz
End of enumeration elements list.
PLL2FRACEN : PLL2 fractional latch enable Set and reset by software to latch the content of PLL2FRACN into the ΣΠmodulator. In order to latch the PLL2FRACN value into the ΣΠmodulator, PLL2FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL2FRACN into the modulator (see for details).
bits : 4 - 4 (1 bit)
access : read-write
PLL2M : Prescaler for PLL2 Set and cleared by software to configure the prescaler of the PLL2. The VCO2 input frequency is PLL2 input clock frequency/PLL2M. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ...
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
division by 1 (bypass)
0x1 : B_0x1
division by 2
0x2 : B_0x2
division by 3
0xF : B_0xF
division by 16
End of enumeration elements list.
PLL2PEN : PLL2 DIVP divider output enable Set and reset by software to enable the pll2_p_ck output of the PLL2. To save power, PLL2PEN and PLL2P bits must be set to 0 when the pll2_p_ck is not used. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll2_p_ck output disabled
0x1 : B_0x1
pll2_p_ck output enabled
End of enumeration elements list.
PLL2QEN : PLL2 DIVQ divider output enable Set and reset by software to enable the pll2_q_ck output of the PLL2. To save power, PLL2QEN and PLL2Q bits must be set to 0 when the pll2_q_ck is not used. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll2_q_ck output disabled
0x1 : B_0x1
pll2_q_ck output enabled
End of enumeration elements list.
PLL2REN : PLL2 DIVR divider output enable Set and reset by software to enable the pll2_r_ck output of the PLL2. To save power, PLL2REN and PLL2R bits must be set to 0 when the pll2_r_ck is not used. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll2_r_ck output disabled
0x1 : B_0x1
pll2_r_ck output enabled
End of enumeration elements list.
RCC PLL3 configuration register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL3SRC : PLL3 entry clock source Set and cleared by software to select PLL3 clock source. These bits can be written only when the PLL3 is disabled. In order to save power, when no PLL3 is used, the value of PLL3SRC must be 00.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock sent to PLL3
0x1 : B_0x1
MSIS clock selected as PLL3 clock entry
0x2 : B_0x2
HSI16 clock selected as PLL3 clock entry
0x3 : B_0x3
HSE clock selected as PLL3 clock entry
End of enumeration elements list.
PLL3RGE : PLL3 input frequency range Set and reset by software to select the proper reference frequency range used for PLL3. This bit must be written before enabling the PLL3. 00-01-10: PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x3 : B_0x3
PLL3 input (ref3_ck) clock range frequency between 8 and 16 MHz
End of enumeration elements list.
PLL3FRACEN : PLL3 fractional latch enable Set and reset by software to latch the content of PLL3FRACN into the ΣΠmodulator. In order to latch the PLL3FRACN value into the ΣΠmodulator, PLL3FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL3FRACN into the modulator (see for details).
bits : 4 - 4 (1 bit)
access : read-write
PLL3M : Prescaler for PLL3 Set and cleared by software to configure the prescaler of the PLL3. The VCO3 input frequency is PLL3 input clock frequency/PLL3M. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ...
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
division by 1 (bypass)
0x1 : B_0x1
division by 2
0x2 : B_0x2
division by 3
0xF : B_0xF
division by 16
End of enumeration elements list.
PLL3PEN : PLL3 DIVP divider output enable Set and reset by software to enable the pll3_p_ck output of the PLL3. To save power, PLL3PEN and PLL3P bits must be set to 0 when the pll3_p_ck is not used. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll3_p_ck output disabled
0x1 : B_0x1
pll3_p_ck output enabled
End of enumeration elements list.
PLL3QEN : PLL3 DIVQ divider output enable Set and reset by software to enable the pll3_q_ck output of the PLL3. To save power, PLL3QEN and PLL3Q bits must be set to 0 when the pll3_q_ck is not used. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll3_q_ck output disabled
0x1 : B_0x1
pll3_q_ck output enabled
End of enumeration elements list.
PLL3REN : PLL3 DIVR divider output enable Set and reset by software to enable the pll3_r_ck output of the PLL3. To save power, PLL3REN and PLL3R bits must be set to 0 when the pll3_r_ck is not used. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll3_r_ck output disabled
0x1 : B_0x1
pll3_r_ck output enabled
End of enumeration elements list.
RCC PLL1 dividers register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL1N : Multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with: PLL1N between 4 and 512 input frequency Fref1_ck between 4 and 16 MHz
bits : 0 - 8 (9 bit)
access : read-write
Enumeration:
0x3 : B_0x3
PLL1N = 4
0x4 : B_0x4
PLL1N = 5
0x5 : B_0x5
PLL1N = 6
0x80 : B_0x80
PLL1N = 129 (default after reset)
0x1FF : B_0x1FF
PLL1N = 512
End of enumeration elements list.
PLL1P : PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ...
bits : 9 - 15 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Not allowed
0x1 : B_0x1
pll1_p_ck = vco1_ck / 2 (default after reset)
0x2 : B_0x2
Not allowed
0x3 : B_0x3
pll1_p_ck = vco1_ck / 4
0x7F : B_0x7F
pll1_p_ck = vco1_ck / 128
End of enumeration elements list.
PLL1Q : PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ...
bits : 16 - 22 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll1_q_ck = vco1_ck
0x1 : B_0x1
pll1_q_ck = vco1_ck / 2 (default after reset)
0x2 : B_0x2
pll1_q_ck = vco1_ck / 3
0x3 : B_0x3
pll1_q_ck = vco1_ck / 4
0x7F : B_0x7F
pll1_q_ck = vco1_ck / 128
End of enumeration elements list.
PLL1R : PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ...
bits : 24 - 30 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll1_r_ck = vco1_ck
0x1 : B_0x1
pll1_r_ck = vco1_ck / 2 (default after reset)
0x2 : B_0x2
pll1_r_ck = vco1_ck / 3
0x3 : B_0x3
pll1_r_ck = vco1_ck / 4
0x7F : B_0x7F
pll1_r_ck = vco1_ck / 128
End of enumeration elements list.
RCC PLL1 fractional divider register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL1FRACN : Fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with: PLL1N must be between 4 and 512. PLL1FRACN can be between 0 and 213- 1. The input frequency Fref1_ck must be between 4 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL1FRACEN to 0. Write the new fractional value into PLL1FRACN. Set the bit PLL1FRACEN to 1.
bits : 3 - 15 (13 bit)
access : read-write
RCC PLL2 dividers configuration register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL2N : Multiplication factor for PLL2 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL2ON = 0 and PLL2RDY = 0). ... ... Others: reserved VCO output frequency = Fref2_ck x PLL2N, when fractional value 0 has been loaded into PLL2FRACN, with: PLL2N between 4 and 512 input frequency Fref2_ck between 1MHz and 16MHz
bits : 0 - 8 (9 bit)
access : read-write
Enumeration:
0x3 : B_0x3
PLL2N = 4
0x4 : B_0x4
PLL2N = 5
0x5 : B_0x5
PLL2N = 6
0x80 : B_0x80
PLL2N = 129 (default after reset)
0x1FF : B_0x1FF
PLL2N = 512
End of enumeration elements list.
PLL2P : PLL2 DIVP division factor Set and reset by software to control the frequency of the pll2_p_ck clock. These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ...
bits : 9 - 15 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll2_p_ck = vco2_ck
0x1 : B_0x1
pll2_p_ck = vco2_ck / 2 (default after reset)
0x2 : B_0x2
pll2_p_ck = vco2_ck / 3
0x3 : B_0x3
pll2_p_ck = vco2_ck / 4
0x7F : B_0x7F
pll2_p_ck = vco2_ck / 128
End of enumeration elements list.
PLL2Q : PLL2 DIVQ division factor Set and reset by software to control the frequency of the pll2_q_ck clock. These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ...
bits : 16 - 22 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll2_q_ck = vco2_ck
0x1 : B_0x1
pll2_q_ck = vco2_ck / 2 (default after reset)
0x2 : B_0x2
pll2_q_ck = vco2_ck / 3
0x3 : B_0x3
pll2_q_ck = vco2_ck / 4
0x7F : B_0x7F
pll2_q_ck = vco2_ck / 128
End of enumeration elements list.
PLL2R : PLL2 DIVR division factor Set and reset by software to control the frequency of the pll2_r_ck clock. These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ...
bits : 24 - 30 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll2_r_ck = vco2_ck
0x1 : B_0x1
pll2_r_ck = vco2_ck / 2 (default after reset)
0x2 : B_0x2
pll2_r_ck = vco2_ck / 3
0x3 : B_0x3
pll2_r_ck = vco2_ck / 4
0x7F : B_0x7F
pll2_r_ck = vco2_ck / 128
End of enumeration elements list.
RCC PLL2 fractional divider register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL2FRACN : Fractional part of the multiplication factor for PLL2 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO. VCO output frequency = Fref2_ck x (PLL2N + (PLL2FRACN / 213)), with PLL2N must be between 4 and 512. PLL2FRACN can be between 0 and 213 - 1. The input frequency Fref2_ck must be between 4 and 16 MHz. In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL2FRACEN to 0. Write the new fractional value into PLL2FRACN. Set the bit PLL2FRACEN to 1.
bits : 3 - 15 (13 bit)
access : read-write
RCC PLL3 dividers configuration register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL3N : Multiplication factor for PLL3 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL3ON = 0 and PLL3RDY = 0). ... ... Others: reserved VCO output frequency = Fref3_ck x PLL3N, when fractional value 0 has been loaded into PLL3FRACN, with: PLL3N between 4 and 512 input frequency Fref3_ck between 4 and 16MHz
bits : 0 - 8 (9 bit)
access : read-write
Enumeration:
0x3 : B_0x3
PLL3N = 4
0x4 : B_0x4
PLL3N = 5
0x5 : B_0x5
PLL3N = 6
0x80 : B_0x80
PLL3N = 129 (default after reset)
0x1FF : B_0x1FF
PLL3N = 512
End of enumeration elements list.
PLL3P : PLL3 DIVP division factor Set and reset by software to control the frequency of the pll3_p_ck clock. These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ...
bits : 9 - 15 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll3_p_ck = vco3_ck
0x1 : B_0x1
pll3_p_ck = vco3_ck / 2 (default after reset)
0x2 : B_0x2
pll3_p_ck = vco3_ck / 3
0x3 : B_0x3
pll3_p_ck = vco3_ck / 4
0x7F : B_0x7F
pll3_p_ck = vco3_ck / 128
End of enumeration elements list.
PLL3Q : PLL3 DIVQ division factor Set and reset by software to control the frequency of the pll3_q_ck clock. These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ...
bits : 16 - 22 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll3_q_ck = vco3_ck
0x1 : B_0x1
pll3_q_ck = vco3_ck / 2 (default after reset)
0x2 : B_0x2
pll3_q_ck = vco3_ck / 3
0x3 : B_0x3
pll3_q_ck = vco3_ck / 4
0x7F : B_0x7F
pll3_q_ck = vco3_ck / 128
End of enumeration elements list.
PLL3R : PLL3 DIVR division factor Set and reset by software to control the frequency of the pll3_r_ck clock. These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ...
bits : 24 - 30 (7 bit)
access : read-write
Enumeration:
0x0 : B_0x0
pll3_r_ck = vco3_ck
0x1 : B_0x1
pll3_r_ck = vco3_ck / 2 (default after reset)
0x2 : B_0x2
pll3_r_ck = vco3_ck / 3
0x3 : B_0x3
pll3_r_ck = vco3_ck / 4
0x7F : B_0x7F
pll3_r_ck = vco3_ck / 128
End of enumeration elements list.
RCC PLL3 fractional divider register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL3FRACN : Fractional part of the multiplication factor for PLL3 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO. VCO output frequency = Fref3_ck x (PLL3N + (PLL3FRACN / 213)), with: PLL3N must be between 4 and 512. PLL3FRACN can be between 0 and 213 - 1. The input frequency Fref3_ck must be between 4 and 16 MHz. In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL3FRACEN to 0. Write the new fractional value into PLL3FRACN. Set the bit PLL3FRACEN to 1.
bits : 3 - 15 (13 bit)
access : read-write
RCC clock interrupt enable register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSIRDYIE : LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSI ready interrupt disabled
0x1 : B_0x1
LSI ready interrupt enabled
End of enumeration elements list.
LSERDYIE : LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSE ready interrupt disabled
0x1 : B_0x1
LSE ready interrupt enabled
End of enumeration elements list.
MSISRDYIE : MSIS ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSIS oscillator stabilization.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
MSIS ready interrupt disabled
0x1 : B_0x1
MSIS ready interrupt enabled
End of enumeration elements list.
HSIRDYIE : HSI16 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSI16 ready interrupt disabled
0x1 : B_0x1
HSI16 ready interrupt enabled
End of enumeration elements list.
HSERDYIE : HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSE ready interrupt disabled
0x1 : B_0x1
HSE ready interrupt enabled
End of enumeration elements list.
HSI48RDYIE : HSI48 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSI48 ready interrupt disabled
0x1 : B_0x1
HSI48 ready interrupt enabled
End of enumeration elements list.
PLL1RDYIE : PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL1 lock.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL1 lock interrupt disabled
0x1 : B_0x1
PLL1 lock interrupt enabled
End of enumeration elements list.
PLL2RDYIE : PLL2 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL2 lock.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL2 lock interrupt disabled
0x1 : B_0x1
PLL2 lock interrupt enabled
End of enumeration elements list.
PLL3RDYIE : PLL3 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL3 lock.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL3 lock interrupt disabled
0x1 : B_0x1
PLL3 lock interrupt enabled
End of enumeration elements list.
MSIKRDYIE : MSIK ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
MSIK ready interrupt disabled
0x1 : B_0x1
MSIK ready interrupt enabled
End of enumeration elements list.
SHSIRDYIE : SHSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SHSI ready interrupt disabled
0x1 : B_0x1
SHSI ready interrupt enabled
End of enumeration elements list.
RCC clock interrupt flag register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSIRDYF : LSI ready interrupt flag Set by hardware when the LSI clock becomes stable and LSIRDYIE is set. Cleared by software setting the LSIRDYC bit.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by the LSI oscillator
0x1 : B_0x1
Clock ready interrupt caused by the LSI oscillator
End of enumeration elements list.
LSERDYF : LSE ready interrupt flag Set by hardware when the LSE clock becomes stable and LSERDYIE is set. Cleared by software setting the LSERDYC bit.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by the LSE oscillator
0x1 : B_0x1
Clock ready interrupt caused by the LSE oscillator
End of enumeration elements list.
MSISRDYF : MSIS ready interrupt flag Set by hardware when the MSIS clock becomes stable and MSISRDYIE is set. Cleared by software setting the MSISRDYC bit.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by the MSIS oscillator
0x1 : B_0x1
Clock ready interrupt caused by the MSIS oscillator
End of enumeration elements list.
HSIRDYF : HSI16 ready interrupt flag Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see RCC_CR). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by the HSI16 oscillator
0x1 : B_0x1
Clock ready interrupt caused by the HSI16 oscillator
End of enumeration elements list.
HSERDYF : HSE ready interrupt flag Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by the HSE oscillator
0x1 : B_0x1
Clock ready interrupt caused by the HSE oscillator
End of enumeration elements list.
HSI48RDYF : HSI48 ready interrupt flag Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. Cleared by software setting the HSI48RDYC bit.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by the HSI48 oscillator
0x1 : B_0x1
Clock ready interrupt caused by the HSI48 oscillator
End of enumeration elements list.
PLL1RDYF : PLL1 ready interrupt flag Set by hardware when the PLL1 locks and PLL1RDYIE is set. Cleared by software setting the PLL1RDYC bit.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by PLL1 lock
0x1 : B_0x1
Clock ready interrupt caused by PLL1 lock
End of enumeration elements list.
PLL2RDYF : PLL2 ready interrupt flag Set by hardware when the PLL2 locks and PLL2RDYIE is set. Cleared by software setting the PLL2RDYC bit.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by PLL2 lock
0x1 : B_0x1
Clock ready interrupt caused by PLL2 lock
End of enumeration elements list.
PLL3RDYF : PLL3 ready interrupt flag Set by hardware when the PLL3 locks and PLL3RDYIE is set. Cleared by software setting the PLL3RDYC bit.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by PLL3 lock
0x1 : B_0x1
Clock ready interrupt caused by PLL3 lock
End of enumeration elements list.
CSSF : Clock security system interrupt flag Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit.
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No clock security interrupt caused by HSE clock failure
0x1 : B_0x1
Clock security interrupt caused by HSE clock failure
End of enumeration elements list.
MSIKRDYF : MSIK ready interrupt flag Set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set. Cleared by software setting the MSIKRDYC bit.
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by the MSIK oscillator
0x1 : B_0x1
Clock ready interrupt caused by the MSIK oscillator
End of enumeration elements list.
SHSIRDYF : SHSI ready interrupt flag Set by hardware when the SHSI clock becomes stable and SHSIRDYIE is set. Cleared by software setting the SHSIRDYC bit.
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No clock ready interrupt caused by the SHSI oscillator
0x1 : B_0x1
Clock ready interrupt caused by the SHSI oscillator
End of enumeration elements list.
RCC clock interrupt clear register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSIRDYC : LSI ready interrupt clear Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect.
bits : 0 - 0 (1 bit)
access : write-only
LSERDYC : LSE ready interrupt clear Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect.
bits : 1 - 1 (1 bit)
access : write-only
MSISRDYC : MSIS ready interrupt clear Writing this bit to 1 clears the MSISRDYF flag. Writing 0 has no effect.
bits : 2 - 2 (1 bit)
access : write-only
HSIRDYC : HSI16 ready interrupt clear Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect.
bits : 3 - 3 (1 bit)
access : write-only
HSERDYC : HSE ready interrupt clear Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect.
bits : 4 - 4 (1 bit)
access : write-only
HSI48RDYC : HSI48 ready interrupt clear Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effect.
bits : 5 - 5 (1 bit)
access : write-only
PLL1RDYC : PLL1 ready interrupt clear Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect.
bits : 6 - 6 (1 bit)
access : write-only
PLL2RDYC : PLL2 ready interrupt clear Writing this bit to 1 clears the PLL2RDYF flag. Writing 0 has no effect.
bits : 7 - 7 (1 bit)
access : write-only
PLL3RDYC : PLL3 ready interrupt clear Writing this bit to 1 clears the PLL3RDYF flag. Writing 0 has no effect.
bits : 8 - 8 (1 bit)
access : write-only
CSSC : Clock security system interrupt clear Writing this bit to 1 clears the CSSF flag. Writing 0 has no effect.
bits : 10 - 10 (1 bit)
access : write-only
MSIKRDYC : MSIK oscillator ready interrupt clear Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has no effect.
bits : 11 - 11 (1 bit)
access : write-only
SHSIRDYC : SHSI oscillator ready interrupt clear Writing this bit to 1 clears the SHSIRDYF flag. Writing 0 has no effect.
bits : 12 - 12 (1 bit)
access : write-only
RCC AHB1 peripheral reset register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPDMA1RST : GPDMA1 reset Set and cleared by software.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset GPDMA1
End of enumeration elements list.
CORDICRST : CORDIC reset Set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset CORDIC
End of enumeration elements list.
FMACRST : FMAC reset Set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset FMAC
End of enumeration elements list.
MDF1RST : MDF1 reset Set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset MDF1
End of enumeration elements list.
CRCRST : CRC reset Set and cleared by software.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset CRC
End of enumeration elements list.
TSCRST : TSC reset Set and cleared by software.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset TSC
End of enumeration elements list.
RAMCFGRST : RAMCFG reset Set and cleared by software.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset RAMCFG
End of enumeration elements list.
DMA2DRST : DMA2D reset Set and cleared by software.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset DMA2D
End of enumeration elements list.
RCC AHB2 peripheral reset register 1
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOARST : IO port A reset Set and cleared by software.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset IO port A
End of enumeration elements list.
GPIOBRST : IO port B reset Set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset IO port B
End of enumeration elements list.
GPIOCRST : IO port C reset Set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset IO port C
End of enumeration elements list.
GPIODRST : IO port D reset Set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset IO port D
End of enumeration elements list.
GPIOERST : IO port E reset Set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset IO port E
End of enumeration elements list.
GPIOFRST : IO port F reset Set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset IO port F
End of enumeration elements list.
GPIOGRST : IO port G reset Set and cleared by software.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset IO port G
End of enumeration elements list.
GPIOHRST : IO port H reset Set and cleared by software.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset IO port H
End of enumeration elements list.
GPIOIRST : IO port I reset Set and cleared by software.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset IO port I
End of enumeration elements list.
ADC1RST : ADC1 reset Set and cleared by software.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset ADC1
End of enumeration elements list.
DCMI_PSSIRST : DCMI and PSSI reset Set and cleared by software.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset DCMI and PSSI
End of enumeration elements list.
OTGRST : OTG_FS reset Set and cleared by software.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset OTG_FS
End of enumeration elements list.
AESRST : AES hardware accelerator reset Set and cleared by software.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset AES
End of enumeration elements list.
HASHRST : Hash reset Set and cleared by software.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset HASH
End of enumeration elements list.
RNGRST : Random number generator reset Set and cleared by software.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset RNG
End of enumeration elements list.
PKARST : PKA reset Set and cleared by software.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset PKA
End of enumeration elements list.
SAESRST : SAES hardware accelerator reset Set and cleared by software.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset SAES
End of enumeration elements list.
OCTOSPIMRST : OCTOSPIM reset Set and cleared by software.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset OCTOSPIM
End of enumeration elements list.
OTFDEC1RST : OTFDEC1 reset Set and cleared by software.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset OTFDEC1
End of enumeration elements list.
OTFDEC2RST : OTFDEC2 reset Set and cleared by software.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset OTFDEC2
End of enumeration elements list.
SDMMC1RST : SDMMC1 reset Set and cleared by software.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset SDMMC1
End of enumeration elements list.
SDMMC2RST : SDMMC2 reset Set and cleared by software.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset SDMMC2
End of enumeration elements list.
RCC AHB2 peripheral reset register 2
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSMCRST : Flexible memory controller reset Set and cleared by software.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset FSMC
End of enumeration elements list.
OCTOSPI1RST : OCTOSPI1 reset Set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset OCTOSPI1
End of enumeration elements list.
OCTOSPI2RST : OCTOSPI2 reset Set and cleared by software.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset OCTOSPI2
End of enumeration elements list.
RCC AHB3 peripheral reset register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPGPIO1RST : LPGPIO1 reset Set and cleared by software.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset LPGPIO1
End of enumeration elements list.
ADC4RST : ADC4 reset Set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset ADC4 interface
End of enumeration elements list.
DAC1RST : DAC1 reset Set and cleared by software.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset DAC1
End of enumeration elements list.
LPDMA1RST : LPDMA1 reset Set and cleared by software.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset LPDMA1
End of enumeration elements list.
ADF1RST : ADF1 reset Set and cleared by software.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset ADF1
End of enumeration elements list.
RCC APB1 peripheral reset register 1
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2RST : TIM2 reset Set and cleared by software.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset TIM2
End of enumeration elements list.
TIM3RST : TIM3 reset Set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset TIM3
End of enumeration elements list.
TIM4RST : TIM4 reset Set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset TIM4
End of enumeration elements list.
TIM5RST : TIM5 reset Set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset TIM5
End of enumeration elements list.
TIM6RST : TIM6 reset Set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset TIM6
End of enumeration elements list.
TIM7RST : TIM7 reset Set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset TIM7
End of enumeration elements list.
SPI2RST : SPI2 reset Set and cleared by software.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset SPI2
End of enumeration elements list.
USART2RST : USART2 reset Set and cleared by software.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset USART2
End of enumeration elements list.
USART3RST : USART3 reset Set and cleared by software.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset USART3
End of enumeration elements list.
UART4RST : UART4 reset Set and cleared by software.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset UART4
End of enumeration elements list.
UART5RST : UART5 reset Set and cleared by software.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset UART5
End of enumeration elements list.
I2C1RST : I2C1 reset Set and cleared by software.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset I2C1
End of enumeration elements list.
I2C2RST : I2C2 reset Set and cleared by software.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset I2C2
End of enumeration elements list.
CRSRST : CRS reset Set and cleared by software.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset the CRS
End of enumeration elements list.
RCC APB1 peripheral reset register 2
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C4RST : I2C4 reset Set and cleared by software
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset I2C4
End of enumeration elements list.
LPTIM2RST : LPTIM2 reset Set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset LPTIM2
End of enumeration elements list.
FDCAN1RST : FDCAN1 reset Set and cleared by software.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset FDCAN1
End of enumeration elements list.
UCPD1RST : UCPD1 reset Set and cleared by software.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset UCPD1
End of enumeration elements list.
RCC APB2 peripheral reset register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1RST : TIM1 reset Set and cleared by software.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset TIM1
End of enumeration elements list.
SPI1RST : SPI1 reset Set and cleared by software.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset SPI1
End of enumeration elements list.
TIM8RST : TIM8 reset Set and cleared by software.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset TIM8
End of enumeration elements list.
USART1RST : USART1 reset Set and cleared by software.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset USART1
End of enumeration elements list.
TIM15RST : TIM15 reset Set and cleared by software.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset TIM15
End of enumeration elements list.
TIM16RST : TIM16 reset Set and cleared by software.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset TIM16
End of enumeration elements list.
TIM17RST : TIM17 reset Set and cleared by software.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset TIM17
End of enumeration elements list.
SAI1RST : SAI1 reset Set and cleared by software.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset SAI1
End of enumeration elements list.
SAI2RST : SAI2 reset Set and cleared by software.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset SAI2
End of enumeration elements list.
RCC internal clock sources calibration register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSICAL3 : MSIRC3 clock calibration for MSI ranges 12 to 15 These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3[4:0] and the factory calibration trim value MSIRC2[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level.
bits : 0 - 4 (5 bit)
access : read-only
MSICAL2 : MSIRC2 clock calibration for MSI ranges 8 to 11 These bits are initialized at startup with the factory-programmed MSIRC2 calibration trim value for ranges 8 to 11. When MSITRIM2 is written, MSICAL2 is updated with the sum of MSITRIM2[4:0] and the factory calibration trim value MSIRC2[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level.
bits : 5 - 9 (5 bit)
access : read-only
MSICAL1 : MSIRC1 clock calibration for MSI ranges 4 to 7 These bits are initialized at startup with the factory-programmed MSIRC1 calibration trim value for ranges 4 to 7. When MSITRIM1 is written, MSICAL1 is updated with the sum of MSITRIM1[4:0] and the factory calibration trim value MSIRC1[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level.
bits : 10 - 14 (5 bit)
access : read-only
MSICAL0 : MSIRC0 clock calibration for MSI ranges 0 to 3 These bits are initialized at startup with the factory-programmed MSIRC0 calibration trim value for ranges 0 to 3. When MSITRIM0 is written, MSICAL0 is updated with the sum of MSITRIM0[4:0] and the factory-programmed calibration trim value MSIRC0[4:0].
bits : 15 - 19 (5 bit)
access : read-only
MSIBIAS : MSI bias mode selection Set by software to select the MSI bias mode. By default, the MSI bias is in continuous mode in order to maintain the output clocks accuracy. Setting this bit reduces the MSI consumption under range 4 but decrease its accuracy.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
MSI bias continuous mode (clock accuracy fast settling time)
0x1 : B_0x1
MSI bias sampling mode (ultra-low-power mode)
End of enumeration elements list.
MSIRGSEL : MSI clock range selection Set by software to select the MSIS and MSIK clocks range with MSISRANGE[3:0] and MSIKRANGE[3:0]. Write 0 has no effect. After exiting Standby or Shutdown mode, or after a reset, this bit is at 0 and the MSIS and MSIK ranges are provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR
0x1 : B_0x1
MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1
End of enumeration elements list.
MSIKRANGE : MSIK clock ranges These bits are configured by software to choose the frequency range of MSIK oscillator when MSIRGSEL is set. 16 frequency ranges are available: Note: MSIKRANGE can be modified when MSIK is OFF (MSISON = 0) or when MSIK is ready (MSIKRDY = 1). MSIKRANGE must NOT be modified when MSIK is ON and NOT ready (MSIKON = 1 and MSIKRDY = 0) MSIKRANGE is kept when the device wakes up from Stop mode, except when the MSIK range is above 24 MHz. In this case MSIKRANGE is changed by hardware into Range 2 (24 MHz).
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
range 0 around 48 MHz
0x1 : B_0x1
range 1 around 24 MHz
0x2 : B_0x2
range 2 around 16 MHz
0x3 : B_0x3
range 3 around 12 MHz
0x4 : B_0x4
range 4 around 4 MHz (reset value)
0x5 : B_0x5
range 5 around 2 MHz
0x6 : B_0x6
range 6 around 1.33 MHz
0x7 : B_0x7
range 7 around 1 MHz
0x8 : B_0x8
range 8 around 3.072 MHz
0x9 : B_0x9
range 9 around 1.536 MHz
0xA : B_0xA
range 10 around 1.024 MHz
0xB : B_0xB
range 11 around 768 kHz
0xC : B_0xC
range 12 around 400 kHz
0xD : B_0xD
range 13 around 200 kHz
0xE : B_0xE
range 14 around 133 kHz
0xF : B_0xF
range 15 around 100 kHz
End of enumeration elements list.
MSISRANGE : MSIS clock ranges These bits are configured by software to choose the frequency range of MSIS oscillator when MSIRGSEL is set. 16 frequency ranges are available: Note: MSISRANGE can be modified when MSIS is OFF (MSISON = 0) or when MSIS is ready (MSISRDY = 1). MSISRANGE must NOT be modified when MSIS is ON and NOT ready (MSISON = 1 and MSISRDY = 0) MSISRANGE is kept when the device wakes up from Stop mode, except when the MSIS range is above 24 MHz. In this case MSISRANGE is changed by hardware into Range 2 (24 MHz).
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0x0 : B_0x0
range 0 around 48 MHz
0x1 : B_0x1
range 1 around 24 MHz
0x2 : B_0x2
range 2 around 16 MHz
0x3 : B_0x3
range 3 around 12 MHz
0x4 : B_0x4
range 4 around 4 MHz (reset value)
0x5 : B_0x5
range 5 around 2 MHz
0x6 : B_0x6
range 6 around 1.33 MHz
0x7 : B_0x7
range 7 around 1 MHz
0x8 : B_0x8
range 8 around 3.072 MHz
0x9 : B_0x9
range 9 around 1.536 MHz
0xA : B_0xA
range 10 around 1.024 MHz
0xB : B_0xB
range 11 around 768 kHz
0xC : B_0xC
range 12 around 400 kHz
0xD : B_0xD
range 13 around 200 kHz
0xE : B_0xE
range 14 around 133 kHz
0xF : B_0xF
range 15 around 100 kHz
End of enumeration elements list.
RCC APB3 peripheral reset register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCFGRST : SYSCFG reset Set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset SYSCFG
End of enumeration elements list.
SPI3RST : SPI3 reset Set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset SPI3
End of enumeration elements list.
LPUART1RST : LPUART1 reset Set and cleared by software.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset LPUART1
End of enumeration elements list.
I2C3RST : I2C3 reset Set and cleared by software.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset I2C3
End of enumeration elements list.
LPTIM1RST : LPTIM1 reset Set and cleared by software.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset LPTIM1
End of enumeration elements list.
LPTIM3RST : LPTIM3 reset Set and cleared by software.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset LPTIM3
End of enumeration elements list.
LPTIM4RST : LPTIM4 reset Set and cleared by software.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset LPTIM4
End of enumeration elements list.
OPAMPRST : OPAMP reset Set and cleared by software.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset OPAMP
End of enumeration elements list.
COMPRST : COMP reset Set and cleared by software.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset COMP
End of enumeration elements list.
VREFRST : VREFBUF reset Set and cleared by software.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Reset VREFBUF
End of enumeration elements list.
RCC AHB1 peripheral clock enable register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPDMA1EN : GPDMA1 clock enable Set and cleared by software.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
GPDMA1 clock disabled
0x1 : B_0x1
GPDMA1 clock enabled
End of enumeration elements list.
CORDICEN : CORDIC clock enable Set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CORDIC clock disabled
0x1 : B_0x1
CORDIC clock enabled
End of enumeration elements list.
FMACEN : FMAC clock enable Set and reset by software.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FMAC clock disabled
0x1 : B_0x1
FMAC clock enabled
End of enumeration elements list.
MDF1EN : MDF1 clock enable Set and reset by software.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
MDF1 clock disabled
0x1 : B_0x1
MDF1 clock enabled
End of enumeration elements list.
FLASHEN : FLASH clock enable Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FLASH clock disabled
0x1 : B_0x1
FLASH clock enabled
End of enumeration elements list.
CRCEN : CRC clock enable Set and cleared by software.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CRC clock disabled
0x1 : B_0x1
CRC clock enabled
End of enumeration elements list.
TSCEN : Touch sensing controller clock enable Set and cleared by software.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TSC clock disabled
0x1 : B_0x1
TSC clock enabled
End of enumeration elements list.
RAMCFGEN : RAMCFG clock enable Set and cleared by software.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
RAMCFG clock disabled
0x1 : B_0x1
RAMCFG clock enabled
End of enumeration elements list.
DMA2DEN : DMA2D clock enable Set and cleared by software.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA2D clock disabled
0x1 : B_0x1
DMA2D clock enabled
End of enumeration elements list.
GTZC1EN : GTZC1 clock enable Set and reset by software.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
GTZC1 clock disabled
0x1 : B_0x1
GTZC1 clock enabled
End of enumeration elements list.
BKPSRAMEN : BKPSRAM clock enable Set and reset by software.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BKPSRAM clock disabled
0x1 : B_0x1
BKPSRAM clock enabled
End of enumeration elements list.
DCACHE1EN : DCACHE1 clock enable Set and reset by software. Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2 or FSMC, even if the DCACHE1 is bypassed.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DCACHE1 clock disabled
0x1 : B_0x1
DCACHE1 clock enabled
End of enumeration elements list.
SRAM1EN : SRAM1 clock enable Set and reset by software.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM1 clock disabled
0x1 : B_0x1
SRAM1 clock enabled
End of enumeration elements list.
RCC AHB2 peripheral clock enable register 1
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOAEN : IO port A clock enable Set and cleared by software.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
IO port A clock disabled
0x1 : B_0x1
IO port A clock enabled
End of enumeration elements list.
GPIOBEN : IO port B clock enable Set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
IO port B clock disabled
0x1 : B_0x1
IO port B clock enabled
End of enumeration elements list.
GPIOCEN : IO port C clock enable Set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
IO port C clock disabled
0x1 : B_0x1
IO port C clock enabled
End of enumeration elements list.
GPIODEN : IO port D clock enable Set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
IO port D clock disabled
0x1 : B_0x1
IO port D clock enabled
End of enumeration elements list.
GPIOEEN : IO port E clock enable Set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
IO port E clock disabled
0x1 : B_0x1
IO port E clock enabled
End of enumeration elements list.
GPIOFEN : IO port F clock enable Set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
IO port F clock disabled
0x1 : B_0x1
IO port F clock enabled
End of enumeration elements list.
GPIOGEN : IO port G clock enable Set and cleared by software.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
IO port G clock disabled
0x1 : B_0x1
IO port G clock enabled
End of enumeration elements list.
GPIOHEN : IO port H clock enable Set and cleared by software.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
IO port H clock disabled
0x1 : B_0x1
IO port H clock enabled
End of enumeration elements list.
GPIOIEN : IO port I clock enable Set and cleared by software.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
IO port I clock disabled
0x1 : B_0x1
IO port I clock enabled
End of enumeration elements list.
ADC1EN : ADC1 clock enable Set and cleared by software.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC1 clock disabled
0x1 : B_0x1
ADC1 clock enabled
End of enumeration elements list.
DCMI_PSSIEN : DCMI and PSSI clock enable Set and cleared by software.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DCMI and PSSI clock disabled
0x1 : B_0x1
DCMI and PSSI clock enabled
End of enumeration elements list.
OTGEN : OTG_FS clock enable Set and cleared by software.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OTG_FS clock disabled
0x1 : B_0x1
OTG_FS clock enabled
End of enumeration elements list.
AESEN : AES clock enable Set and cleared by software.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
AES clock disabled
0x1 : B_0x1
AES clock enabled
End of enumeration elements list.
HASHEN : HASH clock enable Set and cleared by software
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HASH clock disabled
0x1 : B_0x1
HASH clock enabled
End of enumeration elements list.
RNGEN : RNG clock enable Set and cleared by software.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
RNG clock disabled
0x1 : B_0x1
RNG clock enabled
End of enumeration elements list.
PKAEN : PKA clock enable Set and cleared by software.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PKA clock disabled
0x1 : B_0x1
PKA clock enabled
End of enumeration elements list.
SAESEN : SAES clock enable Set and cleared by software.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SAES clock disabled
0x1 : B_0x1
SAES clock enabled
End of enumeration elements list.
OCTOSPIMEN : OCTOSPIM clock enable Set and cleared by software.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OCTOSPIM clock disabled
0x1 : B_0x1
OCTOSPIM clock enabled
End of enumeration elements list.
OTFDEC1EN : OTFDEC1 clock enable Set and cleared by software.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OTFDEC1 clock disabled
0x1 : B_0x1
OTFDEC1 clock enabled
End of enumeration elements list.
OTFDEC2EN : OTFDEC2 clock enable Set and cleared by software.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OTFDEC2 clock disabled
0x1 : B_0x1
OTFDEC2 clock enabled
End of enumeration elements list.
SDMMC1EN : SDMMC1 clock enable Set and cleared by software.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SDMMC1 clock disabled
0x1 : B_0x1
SDMMC1 clock enabled
End of enumeration elements list.
SDMMC2EN : SDMMC2 clock enable Set and cleared by software.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SDMMC2 clock disabled
0x1 : B_0x1
SDMMC2 clock enabled
End of enumeration elements list.
SRAM2EN : SRAM2 clock enable Set and reset by software.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM2 clock disabled
0x1 : B_0x1
SRAM2 clock enabled
End of enumeration elements list.
SRAM3EN : SRAM3 clock enable Set and reset by software.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM3 clock disabled
0x1 : B_0x1
SRAM3 clock enabled
End of enumeration elements list.
RCC AHB2 peripheral clock enable register 2
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSMCEN : FSMC clock enable Set and cleared by software.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FSMC clock disabled
0x1 : B_0x1
FSMC clock enabled
End of enumeration elements list.
OCTOSPI1EN : OCTOSPI1 clock enable Set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OCTOSPI1 clock disabled
0x1 : B_0x1
OCTOSPI1 clock enabled
End of enumeration elements list.
OCTOSPI2EN : OCTOSPI2 clock enable Set and cleared by software.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OCTOSPI2 clock disabled
0x1 : B_0x1
OCTOSPI2 clock enabled
End of enumeration elements list.
RCC AHB3 peripheral clock enable register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPGPIO1EN : LPGPIO1 enable Set and cleared by software.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LPGPIO1 clock disabled
0x1 : B_0x1
LPGPIO1 clock enabled
End of enumeration elements list.
PWREN : PWR clock enable Set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PWR clock disabled
0x1 : B_0x1
PWR clock enabled
End of enumeration elements list.
ADC4EN : ADC4 clock enable Set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC4 clock disabled
0x1 : B_0x1
ADC4 clock enabled
End of enumeration elements list.
DAC1EN : DAC1 clock enable Set and cleared by software.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DAC1 clock disabled
0x1 : B_0x1
DAC1 clock enabled
End of enumeration elements list.
LPDMA1EN : LPDMA1 clock enable Set and cleared by software.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LPDMA1 clock disabled
0x1 : B_0x1
LPDMA1 clock enabled
End of enumeration elements list.
ADF1EN : ADF1 clock enable Set and cleared by software.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADF1 clock disabled
0x1 : B_0x1
ADF1 clock enabled
End of enumeration elements list.
GTZC2EN : GTZC2 clock enable Set and cleared by software.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
GTZC2 clock disabled
0x1 : B_0x1
GTZC2 clock enabled
End of enumeration elements list.
SRAM4EN : SRAM4 clock enable Set and reset by software.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM4 clock disabled
0x1 : B_0x1
SRAM4 clock enabled
End of enumeration elements list.
RCC APB1 peripheral clock enable register 1
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2EN : TIM2 clock enable Set and cleared by software.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM2 clock disabled
0x1 : B_0x1
TIM2 clock enabled
End of enumeration elements list.
TIM3EN : TIM3 clock enable Set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM3 clock disabled
0x1 : B_0x1
TIM3 clock enabled
End of enumeration elements list.
TIM4EN : TIM4 clock enable Set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM4 clock disabled
0x1 : B_0x1
TIM4 clock enabled
End of enumeration elements list.
TIM5EN : TIM5 clock enable Set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM5 clock disabled
0x1 : B_0x1
TIM5 clock enabled
End of enumeration elements list.
TIM6EN : TIM6 clock enable Set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM6 clock disabled
0x1 : B_0x1
TIM6 clock enabled
End of enumeration elements list.
TIM7EN : TIM7 clock enable Set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM7 clock disabled
0x1 : B_0x1
TIM7 clock enabled
End of enumeration elements list.
WWDGEN : WWDG clock enable Set by software to enable the window watchdog clock. Reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
WWDG clock disabled
0x1 : B_0x1
WWDG clock enabled
End of enumeration elements list.
SPI2EN : SPI2 clock enable Set and cleared by software.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SPI2 clock disabled
0x1 : B_0x1
SPI2 clock enabled
End of enumeration elements list.
USART2EN : USART2 clock enable Set and cleared by software.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
USART2 clock disabled
0x1 : B_0x1
USART2 clock enabled
End of enumeration elements list.
USART3EN : USART3 clock enable Set and cleared by software.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
USART3 clock disabled
0x1 : B_0x1
USART3 clock enabled
End of enumeration elements list.
UART4EN : UART4 clock enable Set and cleared by software.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
UART4 clock disabled
0x1 : B_0x1
UART4 clock enabled
End of enumeration elements list.
UART5EN : UART5 clock enable Set and cleared by software.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
UART5 clock disabled
0x1 : B_0x1
UART5 clock enabled
End of enumeration elements list.
I2C1EN : I2C1 clock enable Set and cleared by software.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
I2C1 clock disabled
0x1 : B_0x1
I2C1 clock enabled
End of enumeration elements list.
I2C2EN : I2C2 clock enable Set and cleared by software.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
I2C2 clock disabled
0x1 : B_0x1
I2C2 clock enabled
End of enumeration elements list.
CRSEN : CRS clock enable Set and cleared by software.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CRS clock disabled
0x1 : B_0x1
CRS clock enabled
End of enumeration elements list.
RCC APB1 peripheral clock enable register 2
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C4EN : I2C4 clock enable Set and cleared by software
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
I2C4 clock disabled
0x1 : B_0x1
I2C4 clock enabled
End of enumeration elements list.
LPTIM2EN : LPTIM2 clock enable Set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LPTIM2 clock disabled
0x1 : B_0x1
LPTIM2 clock enabled
End of enumeration elements list.
FDCAN1EN : FDCAN1 clock enable Set and cleared by software.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FDCAN1 clock disabled
0x1 : B_0x1
FDCAN1 clock enabled
End of enumeration elements list.
UCPD1EN : UCPD1 clock enable Set and cleared by software.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
UCPD1 clock disabled
0x1 : B_0x1
UCPD1 clock enabled
End of enumeration elements list.
RCC APB2 peripheral clock enable register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1EN : TIM1 clock enable Set and cleared by software.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM1 clock disabled
0x1 : B_0x1
TIM1 clock enabled
End of enumeration elements list.
SPI1EN : SPI1 clock enable Set and cleared by software.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SPI1 clock disabled
0x1 : B_0x1
SPI1 clock enabled
End of enumeration elements list.
TIM8EN : TIM8 clock enable Set and cleared by software.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM8 clock disabled
0x1 : B_0x1
TIM8 clock enabled
End of enumeration elements list.
USART1EN : USART1clock enable Set and cleared by software.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
USART1 clock disabled
0x1 : B_0x1
USART1 clock enabled
End of enumeration elements list.
TIM15EN : TIM15 clock enable Set and cleared by software.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM15 clock disabled
0x1 : B_0x1
TIM15 clock enabled
End of enumeration elements list.
TIM16EN : TIM16 clock enable Set and cleared by software.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM16 clock disabled
0x1 : B_0x1
TIM16 clock enabled
End of enumeration elements list.
TIM17EN : TIM17 clock enable Set and cleared by software.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM17 clock disabled
0x1 : B_0x1
TIM17 clock enabled
End of enumeration elements list.
SAI1EN : SAI1 clock enable Set and cleared by software.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SAI1 clock disabled
0x1 : B_0x1
SAI1 clock enabled
End of enumeration elements list.
SAI2EN : SAI2 clock enable Set and cleared by software.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SAI2 clock disabled
0x1 : B_0x1
SAI2 clock enabled
End of enumeration elements list.
RCC APB3 peripheral clock enable register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCFGEN : SYSCFG clock enable Set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SYSCFG clock disabled
0x1 : B_0x1
SYSCFG clock enabled
End of enumeration elements list.
SPI3EN : SPI3 clock enable Set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SPI3 clock disabled
0x1 : B_0x1
SPI3 clock enabled
End of enumeration elements list.
LPUART1EN : LPUART1 clock enable Set and cleared by software.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LPUART1 clock disabled
0x1 : B_0x1
LPUART1 clock enabled
End of enumeration elements list.
I2C3EN : I2C3 clock enable Set and cleared by software.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
I2C3 clock disabled
0x1 : B_0x1
I2C3 clock enabled
End of enumeration elements list.
LPTIM1EN : LPTIM1 clock enable Set and cleared by software.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LPTIM1 clock disabled
0x1 : B_0x1
LPTIM1 clock enabled
End of enumeration elements list.
LPTIM3EN : LPTIM3 clock enable Set and cleared by software.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LPTIM3 clock disabled
0x1 : B_0x1
LPTIM3 clock enabled
End of enumeration elements list.
LPTIM4EN : LPTIM4 clock enable Set and cleared by software.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LPTIM4 clock disabled
0x1 : B_0x1
LPTIM4 clock enabled
End of enumeration elements list.
OPAMPEN : OPAMP clock enable Set and cleared by software.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OPAMP clock disabled
0x1 : B_0x1
OPAMP clock enabled
End of enumeration elements list.
COMPEN : COMP clock enable Set and cleared by software.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
COMP clock disabled
0x1 : B_0x1
COMP clock enabled
End of enumeration elements list.
VREFEN : VREFBUF clock enable Set and cleared by software.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
VREFBUF clock disabled
0x1 : B_0x1
VREFBUF clock enabled
End of enumeration elements list.
RTCAPBEN : RTC and TAMP APB clock enable Set and cleared by software.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
RTC and TAMP APB clock disabled
0x1 : B_0x1
RTC and TAMP APB clock enabled
End of enumeration elements list.
RCC AHB1 peripheral clocks enable in Sleep and Stop modes register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPDMA1SMEN : GPDMA1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
GPDMA1 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
GPDMA1 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
CORDICSMEN : CORDIC clocks enable during Sleep and Stop modes Set and cleared by software during Sleep mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CORDIC clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
CORDIC clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
FMACSMEN : FMAC clocks enable during Sleep and Stop modes. Set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FMAC clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
FMAC clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
MDF1SMEN : MDF1 clocks enable during Sleep and Stop modes. Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
MDF1 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
MDF1 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
FLASHSMEN : FLASH clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FLASH clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
FLASH clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
CRCSMEN : CRC clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CRC clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
CRC clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
TSCSMEN : TSC clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TSC clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
TSC clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
RAMCFGSMEN : RAMCFG clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
RAMCFG clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
RAMCFG clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
DMA2DSMEN : DMA2D clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DMA2D clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
DMA2D clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
GTZC1SMEN : GTZC1 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
GTZC1 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
GTZC1 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
BKPSRAMSMEN : BKPSRAM clocks enable during Sleep and Stop modes Set and cleared by software
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
BKPSRAM clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
BKPSRAM clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
ICACHESMEN : ICACHE clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ICACHE clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
ICACHE clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
DCACHE1SMEN : DCACHE1 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DCACHE1 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
DCACHE1 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
SRAM1SMEN : SRAM1 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM1 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
SRAM1 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
RCC AHB2 peripheral clocks enable in Sleep and Stop modes register 1
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOASMEN : IO port A clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
IO port A clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
IO port A clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
GPIOBSMEN : IO port B clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
IO port B clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
IO port B clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
GPIOCSMEN : IO port C clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
IO port C clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
IO port C clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
GPIODSMEN : IO port D clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
IO port D clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
IO port D clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
GPIOESMEN : IO port E clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
IO port E clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
IO port E clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
GPIOFSMEN : IO port F clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
IO port F clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
IO port F clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
GPIOGSMEN : IO port G clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
IO port G clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
IO port G clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
GPIOHSMEN : IO port H clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
IO port H clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
IO port H clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
GPIOISMEN : IO port I clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
IO port I clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
IO port I clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
ADC1SMEN : ADC1 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC1 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
ADC1 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
DCMI_PSSISMEN : DCMI and PSSI clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DCMI and PSSI clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
DCMI and PSSI clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
OTGSMEN : OTG_FS clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OTG_FS clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
OTG_FS clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
AESSMEN : AES clock enable during Sleep and Stop modes Set and cleared by software
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
AES clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
AES clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
HASHSMEN : HASH clock enable during Sleep and Stop modes Set and cleared by software
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HASH clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
HASH clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
RNGSMEN : Random number generator (RNG) clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
RNG clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
RNG clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
PKASMEN : PKA clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PKA clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
PKA clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
SAESSMEN : SAES accelerator clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SAES clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
SAES clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
OCTOSPIMSMEN : OCTOSPIM clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OCTOSPIM clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
OCTOSPIM clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
OTFDEC1SMEN : OTFDEC1 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OTFDEC1 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
OTFDEC1 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
OTFDEC2SMEN : OTFDEC2 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OTFDEC2 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
OTFDEC2 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
SDMMC1SMEN : SDMMC1 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SDMMC1 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
SDMMC1 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
SDMMC2SMEN : SDMMC2 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SDMMC2 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
SDMMC2 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
SRAM2SMEN : SRAM2 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM2 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
SRAM2 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
SRAM3SMEN : SRAM3 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM3 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
SRAM3 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
RCC AHB2 peripheral clocks enable in Sleep and Stop modes register 2
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSMCSMEN : FSMC clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FSMC clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
FSMC clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
OCTOSPI1SMEN : OCTOSPI1 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OCTOSPI1 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
OCTOSPI1 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
OCTOSPI2SMEN : OCTOSPI2 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OCTOSPI2 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
OCTOSPI2 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
RCC AHB3 peripheral clocks enable in Sleep and Stop modes register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPGPIO1SMEN : LPGPIO1 enable during Sleep and Stop modes Set and cleared by software.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LPGPIO1 clock disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
LPGPIO1 clock enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
PWRSMEN : PWR clock enable during Sleep and Stop modes Set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PWR clock disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
PWR clock enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
ADC4SMEN : ADC4 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC4 clock disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
ADC4 clock enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
DAC1SMEN : DAC1 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DAC1 clock disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
DAC1 clock enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
LPDMA1SMEN : LPDMA1 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LPDMA1 clock disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
LPDMA1 clock enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
ADF1SMEN : ADF1 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADF1 clock disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
ADF1 clock enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
GTZC2SMEN : GTZC2 clock enable during Sleep and Stop modes Set and cleared by software.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
GTZC2 clock disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
GTZC2 clock enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
SRAM4SMEN : SRAM4 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM4 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
SRAM4 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
RCC internal clock sources calibration register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSITRIM3 : MSI clock trimming for ranges 12 to 15 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI.
bits : 0 - 4 (5 bit)
access : read-write
MSITRIM2 : MSI clock trimming for ranges 8 to 11 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC2[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI.
bits : 5 - 9 (5 bit)
access : read-write
MSITRIM1 : MSI clock trimming for ranges 4 to 7 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC1[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI.
bits : 10 - 14 (5 bit)
access : read-write
MSITRIM0 : MSI clock trimming for ranges 0 to 3 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC0[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI.
bits : 15 - 19 (5 bit)
access : read-write
RCC APB1 peripheral clocks enable in Sleep and Stop modes register 1
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2SMEN : TIM2 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM2 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
TIM2 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
TIM3SMEN : TIM3 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM3 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
TIM3 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
TIM4SMEN : TIM4 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM4 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
TIM4 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
TIM5SMEN : TIM5 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM5 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
TIM5 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
TIM6SMEN : TIM6 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM6 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
TIM6 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
TIM7SMEN : TIM7 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM7 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
TIM7 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
WWDGSMEN : Window watchdog clocks enable during Sleep and Stop modes Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Window watchdog clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
Window watchdog clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
SPI2SMEN : SPI2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SPI2 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
SPI2 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
USART2SMEN : USART2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
USART2 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
USART2 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
USART3SMEN : USART3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
USART3 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
USART3 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
UART4SMEN : UART4 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
UART4 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
UART4 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
UART5SMEN : UART5 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
UART5 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
UART5 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
I2C1SMEN : I2C1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
I2C1 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
I2C1 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
I2C2SMEN : I2C2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
I2C2 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
I2C2 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
CRSSMEN : CRS clock enable during Sleep and Stop modes Set and cleared by software.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CRS clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
CRS clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C4SMEN : I2C4 clocks enable during Sleep and Stop modes Set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
I2C4 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
I2C4 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
LPTIM2SMEN : LPTIM2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LPTIM2 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
LPTIM2 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
FDCAN1SMEN : FDCAN1 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
FDCAN1 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
FDCAN1 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
UCPD1SMEN : UCPD1 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
UCPD1 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
UCPD1 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
RCC APB2 peripheral clocks enable in Sleep and Stop modes register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM1SMEN : TIM1 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM1 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
TIM1 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
SPI1SMEN : SPI1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SPI1 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
SPI1 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
TIM8SMEN : TIM8 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM8 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
TIM8 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
USART1SMEN : USART1clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
USART1clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
USART1clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
TIM15SMEN : TIM15 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM15 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
TIM15 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
TIM16SMEN : TIM16 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM16 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
TIM16 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
TIM17SMEN : TIM17 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
TIM17 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
TIM17 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
SAI1SMEN : SAI1 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SAI1 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
SAI1 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
SAI2SMEN : SAI2 clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SAI2 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
SAI2 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
RCC APB3 peripheral clock enable in Sleep and Stop modes register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCFGSMEN : SYSCFG clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SYSCFG clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
SYSCFG clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
SPI3SMEN : SPI3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SPI3 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
SPI3 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
LPUART1SMEN : LPUART1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LPUART1 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
LPUART1 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
I2C3SMEN : I2C3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
I2C3 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
I2C3 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
LPTIM1SMEN : LPTIM1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LPTIM1 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
LPTIM1 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
LPTIM3SMEN : LPTIM3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LPTIM3 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
LPTIM3 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
LPTIM4SMEN : LPTIM4 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LPTIM4 clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
LPTIM4 clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
OPAMPSMEN : OPAMP clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OPAMP clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
OPAMP clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
COMPSMEN : COMP clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
COMP clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
COMP clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
VREFSMEN : VREFBUF clocks enable during Sleep and Stop modes Set and cleared by software.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
VREFBUF clocks disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
VREFBUF clocks enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
RTCAPBSMEN : RTC and TAMP APB clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
RTC and TAMP APB clock disabled by the clock gating during Sleep and Stop modes
0x1 : B_0x1
RTC and TAMP APB clock enabled by the clock gating during Sleep and Stop modes
End of enumeration elements list.
RCC SmartRun domain peripheral autonomous mode register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI3AMEN : SPI3 autonomous mode enable in Stop 0,1, 2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SPI3 autonomous mode disabled during Stop 0,1,2 mode
0x1 : B_0x1
SPI3 autonomous mode enabled during Stop 0,1,2 mode
End of enumeration elements list.
LPUART1AMEN : LPUART1 autonomous mode enable in Stop 0,1, 2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LPUART1 autonomous mode disabled during Stop 0,1,2 mode
0x1 : B_0x1
LPUART1 autonomous mode enabled during Stop 0,1,2 mode
End of enumeration elements list.
I2C3AMEN : I2C3 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
I2C3 autonomous mode disabled during Stop 0,1,2 mode
0x1 : B_0x1
I2C3 autonomous mode enabled during Stop 0,1,2 mode
End of enumeration elements list.
LPTIM1AMEN : LPTIM1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LPTIM1 autonomous mode disabled during Stop 0,1,2 mode
0x1 : B_0x1
LPTIM1 autonomous mode enabled during Stop 0,1,2 mode
End of enumeration elements list.
LPTIM3AMEN : LPTIM3 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LPTIM3 autonomous mode disabled during Stop 0,1,2 mode
0x1 : B_0x1
LPTIM3 autonomous mode enabled during Stop 0,1,2 mode
End of enumeration elements list.
LPTIM4AMEN : LPTIM4 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LPTIM4 autonomous mode disabled during Stop 0,1,2 mode
0x1 : B_0x1
LPTIM4 autonomous mode enabled during Stop 0,1,2 mode
End of enumeration elements list.
OPAMPAMEN : OPAMP autonomous mode enable in Stop 0,1,2 mode Set and cleared by software.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
OPAMP autonomous mode disabled during Stop 0,1,2 mode
0x1 : B_0x1
OPAMP autonomous mode enabled during Stop 0,1,2 mode
End of enumeration elements list.
COMPAMEN : COMP autonomous mode enable in Stop 0,1,2 mode Set and cleared by software.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
COMP autonomous mode disabled during Stop 0,1,2 mode
0x1 : B_0x1
COMP autonomous mode enabled during Stop 0,1,2 mode
End of enumeration elements list.
VREFAMEN : VREFBUF autonomous mode enable in Stop 0,1,2 mode Set and cleared by software.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
VREFBUF autonomous mode disabled during Stop 0,1,2 mode
0x1 : B_0x1
VREFBUF autonomous mode enabled during Stop 0,1,2 mode
End of enumeration elements list.
RTCAPBAMEN : RTC and TAMP autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
RTC and TAMP autonomous mode disabled during Stop 0,1,2 mode
0x1 : B_0x1
RTC and TAMP autonomous mode enabled during Stop 0,1,2 mode
End of enumeration elements list.
ADC4AMEN : ADC4 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADC4 autonomous mode disabled during Stop 0,1,2 mode
0x1 : B_0x1
ADC4 autonomous mode enabled during Stop 0,1,2 mode
End of enumeration elements list.
LPGPIO1AMEN : LPGPIO1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LPGPIO1 autonomous mode disabled during Stop 0,1,2 mode
0x1 : B_0x1
LPGPIO1 autonomous mode enabled during Stop 0,1,2 mode
End of enumeration elements list.
DAC1AMEN : DAC1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
DAC1 autonomous mode disabled during Stop 0,1,2 mode
0x1 : B_0x1
DAC1 autonomous mode enabled during Stop 0,1,2 mode
End of enumeration elements list.
LPDMA1AMEN : LPDMA1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LPDMA1 autonomous mode disabled during Stop 0,1,2 mode
0x1 : B_0x1
LPDMA1 autonomous mode enabled during Stop 0,1,2 mode
End of enumeration elements list.
ADF1AMEN : ADF1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ADF1 autonomous mode disabled during Stop 0,1,2 mode
0x1 : B_0x1
ADF1 autonomous mode enabled during Stop 0,1,2 mode
End of enumeration elements list.
SRAM4AMEN : SRAM4 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SRAM4 autonomous mode disabled during Stop 0,1,2 mode
0x1 : B_0x1
SRAM4 autonomous mode enabled during Stop 0,1,2 mode
End of enumeration elements list.
RCC peripherals independent clock configuration register 1
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USART1SEL : USART1 kernel clock source selection This bits are used to select the USART1 kernel clock source. Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PCLK2 selected
0x1 : B_0x1
SYSCLK selected
0x2 : B_0x2
HSI16 selected
0x3 : B_0x3
LSE selected
End of enumeration elements list.
USART2SEL : USART2 kernel clock source selection This bits are used to select the USART2 kernel clock source. Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PCLK1 selected
0x1 : B_0x1
SYSCLK selected
0x2 : B_0x2
HSI16 selected
0x3 : B_0x3
LSE selected
End of enumeration elements list.
USART3SEL : USART3 kernel clock source selection This bits are used to select the USART3 kernel clock source. Note: The USART3 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PCLK1 selected
0x1 : B_0x1
SYSCLK selected
0x2 : B_0x2
HSI16 selected
0x3 : B_0x3
LSE selected
End of enumeration elements list.
UART4SEL : UART4 kernel clock source selection This bits are used to select the UART4 kernel clock source. Note: The UART4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PCLK1 selected
0x1 : B_0x1
SYSCLK selected
0x2 : B_0x2
HSI16 selected
0x3 : B_0x3
LSE selected
End of enumeration elements list.
UART5SEL : UART5 kernel clock source selection These bits are used to select the UART5 kernel clock source. Note: The UART5 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PCLK1 selected
0x1 : B_0x1
SYSCLK selected
0x2 : B_0x2
HSI16 selected
0x3 : B_0x3
LSE selected
End of enumeration elements list.
I2C1SEL : I2C1 kernel clock source selection These bits are used to select the I2C1 kernel clock source. Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PCLK1 selected
0x1 : B_0x1
SYSCLK selected
0x2 : B_0x2
HSI16 selected
0x3 : B_0x3
MSIK selected
End of enumeration elements list.
I2C2SEL : I2C2 kernel clock source selection These bits are used to select the I2C2 kernel clock source. Note: The I2C2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PCLK1 selected
0x1 : B_0x1
SYSCLK selected
0x2 : B_0x2
HSI16 selected
0x3 : B_0x3
MSIK selected
End of enumeration elements list.
I2C4SEL : I2C4 kernel clock source selection These bits are used to select the I2C4 kernel clock source. Note: The I2C4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK.
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PCLK1 selected
0x1 : B_0x1
SYSCLK selected
0x2 : B_0x2
HSI16 selected
0x3 : B_0x3
MSIK selected
End of enumeration elements list.
SPI2SEL : SPI2 kernel clock source selection These bits are used to select the SPI2 kernel clock source. Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PCLK1 selected
0x1 : B_0x1
SYSCLK selected
0x2 : B_0x2
HSI16 selected
0x3 : B_0x3
MSIK selected
End of enumeration elements list.
LPTIM2SEL : Low-power timer 2 kernel clock source selection These bits are used to select the LPTIM2 kernel clock source. Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI16 if HSIKERON = 1.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PCLK1 selected
0x1 : B_0x1
LSI selected
0x2 : B_0x2
HSI16 selected
0x3 : B_0x3
LSE selected
End of enumeration elements list.
SPI1SEL : SPI1 kernel clock source selection These bits are used to select the SPI1 kernel clock source. Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PCLK2 selected
0x1 : B_0x1
SYSCLK selected
0x2 : B_0x2
HSI16 selected
0x3 : B_0x3
MSIK selected
End of enumeration elements list.
SYSTICKSEL : SysTick clock source selection These bits are used to select the SysTick clock source. Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one HCLK cycle is introduced, due to the LSE or LSI sampling with HCLK in the SysTick circuitry.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HCLK/8 selected
0x1 : B_0x1
LSI selected
0x2 : B_0x2
LSE selected
End of enumeration elements list.
FDCAN1SEL : FDCAN1 kernel clock source selection These bits are used to select the FDCAN1 kernel clock source.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSE clock selected
0x1 : B_0x1
PLL1Q (pll1_q_ck) selected
0x2 : B_0x2
PLL2 P (pll2_p_ck) selected
End of enumeration elements list.
ICLKSEL : intermediate clock source selection These bits are used to select the clock source used by OTG_FS and SDMMC.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSI48 clock selected
0x1 : B_0x1
PLL2 Q (pll2_q_ck) selected
0x2 : B_0x2
PLL1 Q (pll1_q_ck) selected
0x3 : B_0x3
MSIK clock selected
End of enumeration elements list.
TIMICSEL : Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture When the TIMICSEL2 bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4 or MSI/1024. Depending on TIMICSEL[1:0] value, MSI is either MSIK or MSIS. When TIMICSEL2 is cleared, the HSI, MSIK and MSIS clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture. 0xx: HSI, MSIK and MSIS dividers disabled Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division.
bits : 29 - 31 (3 bit)
access : read-write
Enumeration:
0x4 : B_0x4
HSI/256, MSIS/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture
0x5 : B_0x5
HSI/256, MSIS/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture
0x6 : B_0x6
HSI/256, MSIK/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture
0x7 : B_0x7
HSI/256, MSIK/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture
End of enumeration elements list.
RCC peripherals independent clock configuration register 2
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDF1SEL : MDF1 kernel clock source selection These bits are used to select the MDF1 kernel clock source. others: reserved
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HCLK selected
0x1 : B_0x1
PLL1 P (pll1_p_ck) selected
0x2 : B_0x2
PLL3 Q (pll3_q_ck) selected
0x3 : B_0x3
input pin AUDIOCLK selected
0x4 : B_0x4
MSIK clock selected
End of enumeration elements list.
SAI1SEL : SAI1 kernel clock source selection These bits are used to select the SAI1 kernel clock source. others: reserved Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible.
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL2 P (pll2_p_ck) selected
0x1 : B_0x1
PLL3 P (pll3_p_ck) selected
0x2 : B_0x2
PLL1 P (pll1_p_ck) selected
0x3 : B_0x3
input pin AUDIOCLK selected
0x4 : B_0x4
HSI16 clock selected
End of enumeration elements list.
SAI2SEL : SAI2 kernel clock source selection These bits are used to select the SAI2 kernel clock source. others: reserved Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible.
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PLL2 P (pll2_p_ck) selected
0x1 : B_0x1
PLL3 P (pll3_p_ck) selected
0x2 : B_0x2
PLL1 P (pll1_p_ck) selected
0x3 : B_0x3
input pin AUDIOCLK selected
0x4 : B_0x4
HSI16 clock selected
End of enumeration elements list.
SAESSEL : SAES kernel clock source selection This bit is used to select the SAES kernel clock source.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SHSI selected
0x1 : B_0x1
SHSI / 2 selected, can be used in Range 4
End of enumeration elements list.
RNGSEL : RNGSEL kernel clock source selection These bits are used to select the RNG kernel clock source.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HSI48 selected
0x1 : B_0x1
HSI48 / 2 selected, can be used in Range 4
0x2 : B_0x2
HSI16 selected
End of enumeration elements list.
SDMMCSEL : SDMMC1 and SDMMC2 kernel clock source selection This bit is used to select the SDMMC kernel clock source. It is recommended to change this bit only after reset and before enabling the SDMMC.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
ICLK clock selected
0x1 : B_0x1
PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode)
End of enumeration elements list.
OCTOSPISEL : OCTOSPI1 and OCTOSPI2 kernel clock source selection These bits are used to select the OCTOSPI1 and OCTOSPI2 kernel clock source.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
SYSCLK selected
0x1 : B_0x1
MSIK selected
0x2 : B_0x2
PLL1 Q (pll1_q_ck) selected, can be up to 200 MHz
0x3 : B_0x3
PLL2 Q (pll2_q_ck) selected, can be up to 200 MHz
End of enumeration elements list.
RCC peripherals independent clock configuration register 3
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPUART1SEL : LPUART1 kernel clock source selection These bits are used to select the LPUART1 kernel clock source. others: reserved Note: The LPUART1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16, LSE or MSIK.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PCLK3 selected
0x1 : B_0x1
SYSCLK selected
0x2 : B_0x2
HSI16 selected
0x3 : B_0x3
LSE selected
0x4 : B_0x4
MSIK selected
End of enumeration elements list.
SPI3SEL : SPI3 kernel clock source selection These bits are used to select the SPI3 kernel clock source. Note: The SPI3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16 or MSIK.
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PCLK3 selected
0x1 : B_0x1
SYSCLK selected
0x2 : B_0x2
HSI16 selected
0x3 : B_0x3
MSIK selected
End of enumeration elements list.
I2C3SEL : I2C3 kernel clock source selection These bits are used to select the I2C3 kernel clock source. Note: The I2C3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16 or MSIK.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
PCLK3 selected
0x1 : B_0x1
SYSCLK selected
0x2 : B_0x2
HSI16 selected
0x3 : B_0x3
MSIK selected
End of enumeration elements list.
LPTIM34SEL : LPTIM3 and LPTIM4 kernel clock source selection These bits are used to select the LPTIM3 and LPTIM4 kernel clock source. Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1 or MSIK with MSIKERON = 1.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
MSIK clock selected
0x1 : B_0x1
LSI selected
0x2 : B_0x2
HSI selected
0x3 : B_0x3
LSE selected
End of enumeration elements list.
LPTIM1SEL : LPTIM1 kernel clock source selection These bits are used to select the LPTIM1 kernel clock source. Note: The LPTIM1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1 or MSIK with MSIKERON = 1.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
MSIK clock selected
0x1 : B_0x1
LSI selected
0x2 : B_0x2
HSI16 selected
0x3 : B_0x3
LSE selected
End of enumeration elements list.
ADCDACSEL : ADC1, ADC4 and DAC1 kernel clock source selection These bits are used to select the ADC1, ADC4 and DAC1 kernel clock source. others: reserved Note: The ADC1, ADC4 and DAC1 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16 or MSIK (only ADC4 and DAC1 are functional in Stop 2 mode).
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HCLK clock selected
0x1 : B_0x1
SYSCLK selected
0x2 : B_0x2
PLL2 R (pll2_r_ck) selected
0x3 : B_0x3
HSE clock selected
0x4 : B_0x4
HSI16 clock selected
0x5 : B_0x5
MSIK clock selected
End of enumeration elements list.
DAC1SEL : DAC1 sample and hold clock source selection This bit is used to select the DAC1 sample and hold clock source.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSE selected
0x1 : B_0x1
LSI selected
End of enumeration elements list.
ADF1SEL : ADF1 kernel clock source selection These bits are used to select the ADF1 kernel clock source. others: reserved Note: The ADF1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is AUDIOCLK or MSIK.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x0 : B_0x0
HCLK selected
0x1 : B_0x1
PLL1 P (pll1_p_ck) selected
0x2 : B_0x2
PLL3 Q (pll3_q_ck) selected
0x3 : B_0x3
input pin AUDIOCLK selected
0x4 : B_0x4
MSIK clock selected
End of enumeration elements list.
RCC Backup domain control register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSEON : LSE oscillator enable Set and cleared by software.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSE oscillator OFF
0x1 : B_0x1
LSE oscillator ON
End of enumeration elements list.
LSERDY : LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
LSE oscillator not ready
0x1 : B_0x1
LSE oscillator ready
End of enumeration elements list.
LSEBYP : LSE oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSE oscillator not bypassed
0x1 : B_0x1
LSE oscillator bypassed
End of enumeration elements list.
LSEDRV : LSE oscillator drive capability Set by software to modulate the drive capability of the LSE oscillator. This field can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). Note: The oscillator is in 'Xtal mode when it is not in bypass mode.
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
'Xtal mode lower driving capability
0x1 : B_0x1
'Xtal mode medium-low driving capability
0x2 : B_0x2
'Xtal mode medium-high driving capability
0x3 : B_0x3
'Xtal mode higher driving capability
End of enumeration elements list.
LSECSSON : CSS on LSE enable Set by software to enable the CSS on LSE. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case, the software must disable the LSECSSON bit.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
CSS on LSE OFF
0x1 : B_0x1
CSS on LSE ON
End of enumeration elements list.
LSECSSD : CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the CCS on the external 32 kHz oscillator (LSE).
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No failure detected on LSE
0x1 : B_0x1
Failure detected on LSE
End of enumeration elements list.
LSESYSEN : LSE system clock (LSESYS) enable Set by software to enable always the LSE system clock generated by RCC. This clock can be used by any peripheral when its source clock is the LSE or at system level in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed. The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by the CSS on LSE, by a peripheral or any other source clock using LSE.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSESYS only enabled when requested by a peripheral or system function
0x1 : B_0x1
LSESYS enabled always generated by the RCC
End of enumeration elements list.
RTCSEL : RTC and TAMP clock source selection Set by software to select the clock source for the RTC and TAMP . Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No clock selected
0x1 : B_0x1
LSE oscillator clock selected
0x2 : B_0x2
LSI oscillator clock selected
0x3 : B_0x3
HSE oscillator clock divided by 32 selected
End of enumeration elements list.
LSESYSRDY : LSE system clock (LSESYS) ready Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles. The LSE clock must be already enabled and stable (LSEON and LSERDY are set). When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles.
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
LSESYS clock not ready
0x1 : B_0x1
LSESYS clock ready
End of enumeration elements list.
LSEGFON : LSE clock glitch filter enable Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0)
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSE glitch filter disabled
0x1 : B_0x1
LSE glitch filter enabled
End of enumeration elements list.
RTCEN : RTC and TAMP clock enable Set and cleared by software.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
RTC and TAMP clock disabled
0x1 : B_0x1
RTC and TAMP clock enabled
End of enumeration elements list.
BDRST : Backup domain software reset Set and cleared by software.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
Reset not activated
0x1 : B_0x1
Reset the entire Backup domain
End of enumeration elements list.
LSCOEN : Low-speed clock output (LSCO) enable Set and cleared by software.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSCO disabled
0x1 : B_0x1
LSCO enabled
End of enumeration elements list.
LSCOSEL : Low-speed clock output selection Set and cleared by software.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSI clock selected
0x1 : B_0x1
LSE clock selected
End of enumeration elements list.
LSION : LSI oscillator enable Set and cleared by software.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSI oscillator OFF
0x1 : B_0x1
LSI oscillator ON
End of enumeration elements list.
LSIRDY : LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSI oscillator not ready
0x1 : B_0x1
LSI oscillator ready
End of enumeration elements list.
LSIPREDIV : Low-speed clock divider configuration Set and cleared by software to enable the LSI division. This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 μs after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
LSI not divided
0x1 : B_0x1
LSI divided by 128
End of enumeration elements list.
RCC control/status register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSIKSRANGE : MSIK range after Standby mode Set by software to chose the MSIK frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSIKSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing the MSIKSRANGE does not change the current MSIK frequency.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0x4 : B_0x4
range 4 around 4M Hz (reset value)
0x5 : B_0x5
range 5 around 2 MHz
0x6 : B_0x6
range 6 around 1.5 MHz
0x7 : B_0x7
range 7 around 1 MHz
0x8 : B_0x8
range 8 around 3.072 MHz
End of enumeration elements list.
MSISSRANGE : MSIS range after Standby mode Set by software to chose the MSIS frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSISSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing the MSISSRANGE does not change the current MSIS frequency.
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0x4 : B_0x4
range 4 around 4M Hz (reset value)
0x5 : B_0x5
range 5 around 2 MHz
0x6 : B_0x6
range 6 around 1.5 MHz
0x7 : B_0x7
range 7 around 1 MHz
0x8 : B_0x8
range 8 around 3.072 MHz
End of enumeration elements list.
RMVF : Remove reset flag Set by software to clear the reset flags.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0x0 : B_0x0
No effect
0x1 : B_0x1
Clear the reset flags
End of enumeration elements list.
OBLRSTF : Option byte loader reset flag Set by hardware when a reset from the option byte loading occurs. Cleared by writing to the RMVF bit.
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No reset from option byte loading occurred
0x1 : B_0x1
Reset from option byte loading occurred
End of enumeration elements list.
PINRSTF : NRST pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit.
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No reset from NRST pin occurred
0x1 : B_0x1
Reset from NRST pin occurred
End of enumeration elements list.
BORRSTF : BOR flag Set by hardware when a BOR occurs. Cleared by writing to the RMVF bit.
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No BOR occurred
0x1 : B_0x1
BOR occurred
End of enumeration elements list.
SFTRSTF : Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit.
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No software reset occurred
0x1 : B_0x1
Software reset occurred
End of enumeration elements list.
IWDGRSTF : Independent watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by writing to the RMVF bit.
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No independent watchdog reset occurred
0x1 : B_0x1
Independent watchdog reset occurred
End of enumeration elements list.
WWDGRSTF : Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by writing to the RMVF bit.
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No window watchdog reset occurred
0x1 : B_0x1
Window watchdog reset occurred
End of enumeration elements list.
LPWRRSTF : Low-power reset flag Set by hardware when a reset occurs due to Stop, Standby or Shutdown mode entry, whereas the corresponding nRST_STOP, nRST_STBY or nRST_SHDW option bit is cleared. Cleared by writing to the RMVF bit.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0x0 : B_0x0
No illegal low-power mode reset occurred
0x1 : B_0x1
Illegal low-power mode reset occurred
End of enumeration elements list.
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