GPDMA

SDW_LOG2 : binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (GPDMA_CxBR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address GPDMA_CxSAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

SINC : source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

SBL_1 : source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within a burst. If SBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width SDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed.
bits : 4 - 9 (6 bit)
access : read-write

PAM : padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else: - Case 1: If destination data width > source data width 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer - Case 2: If destination data width < source data width 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination Note:
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

End of enumeration elements list.

SBX : source byte exchange within the unaligned half-word of each source word If the source data width is shorter than a word, this bit is ignored. If the source data width is a word:
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no byte-based exchange within the unaligned half-word of each source word

0x1 : B_0x1

the two consecutive bytes within the unaligned half-word of each source word are exchanged.

End of enumeration elements list.

SAP : source allocated port This bit is used to allocate the master port for the source transfer Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

SSEC : security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx =1 . A secure write is ignored when GPDMA_SECCFGR.SECx = 0. When GPDMA_SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer from the source is non-secure.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

DDW_LOG2 : binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0], versus DDW_LOG2[1:0]). Otherwise a user setting error is reported and no transfer is issued.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

DINC : destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

DBL_1 : destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat within a burst. If DBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width DDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed.
bits : 20 - 25 (6 bit)
access : read-write

DBX : destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte:
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no byte-based exchange within half-word

0x1 : B_0x1

the two consecutive (post PAM) bytes are exchanged in each destination half-word.

End of enumeration elements list.

DHX : destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word:
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no halfword-based exchanged within word

0x1 : B_0x1

the two consecutive (post PAM) half-words are exchanged in each destination word.

End of enumeration elements list.

DAP : destination allocated port This bit is used to allocate the master port for the destination transfer Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

DSEC : security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx = 1. A secure write is ignored when GPDMA_SECCFGR.SECx = 0. When GPDMA_SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer to the destination is non-secure.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

GPDMA_C1TR2

GPDMA channel 1 transfer register 2
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REQSEL : GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per . The user must not assign a same input hardware request (same REQSEL[6:0] value) to different active GPDMA channels (GPDMA_CxCR.EN = 1 and GPDMA_CxTR2.SWREQ = 0 for these channels). GPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting.
bits : 0 - 6 (7 bit)
access : read-write

SWREQ : software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no software request. The selected hardware request REQSEL[6:0] is taken into account.

0x1 : B_0x1

software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored.

End of enumeration elements list.

DREQ : destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: Note:
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)

0x1 : B_0x1

selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)

End of enumeration elements list.

BREQ : Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.

0x1 : B_0x1

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).

End of enumeration elements list.

TRIGM : trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (GPDMA_CxCR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored. Else, a GPDMA transfer is conditioned by at least one trigger hit: first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. – If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each programmed burst read is conditioned. – If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit. The GPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[5:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized.memorized. A trigger overrun flag is reported (GPDMA_CxSR.TOF =1 ), and an interrupt is generated if enabled (GPDMA_CxCR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and (SWREQ =1 or (SWREQ = 0 and DREQ =0 )), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger. When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1-Kbyte boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1), this shortened destination burst transfer is conditioned once by the trigger.
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with GPDMA_CxBR1.BRC[10:0] ≠ 0).

0x1 : B_0x1

channel x = 0 to 11, same as 00 channel x=12 to 15, at 2D/repeated block level, the

0x2 : B_0x2

at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.

0x3 : B_0x3

at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger.

End of enumeration elements list.

TRIGSEL : trigger event input selection These bits select the trigger event input of the GPDMA transfer (as per ), with an active trigger event if TRIGPOL[1:0] ≠ 00.
bits : 16 - 21 (6 bit)
access : read-write

TRIGPOL : trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0].
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no trigger (masked trigger event)

0x1 : B_0x1

trigger on the rising edge

0x2 : B_0x2

trigger on the falling edge

0x3 : B_0x3

same as 00

End of enumeration elements list.

TCEM : transfer complete event mode These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1.
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.

0x1 : B_0x1

channel x = 0 to 11, same as 00 channel x=12 to 15, at 2D/repeated block level (when GPDMA_CxBR1.BRC[10:0] = 0 and GPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block.

0x2 : B_0x2

at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer.

0x3 : B_0x3

at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated.

End of enumeration elements list.

GPDMA_C1BR1

GPDMA channel 1 block register 1
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BNDT : block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if GPDMA_CxLLR.UB1 = 1, this field is updated by the LLI in the memory. - if GPDMA_CxLLR.UB1 = 0 and if there is at least one non null Uxx update bit, this field is internally restored to the programmed value. - if all GPDMA_CxLLR.Uxx = 0 and if GPDMA_CxLLR.LA[15:0] = 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if GPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (GPDMA_CxTR1.PAM[1] = 1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued.
bits : 0 - 15 (16 bit)
access : read-write

GPDMA_C1SAR

GPDMA channel 1 source address register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SA : source address This field is the pointer to the address from which the next data is read. During the channel activity, depending on the source addressing mode (GPDMA_CxTR1.SINC), this field is kept fixed or incremented by the data width (GPDMA_CxTR1.SDW_LOG2[1:0]) after each single source data, reflecting the next address from which data is read. During the channel activity, this address is updated after each completed source burst, consequently to: the programmed source burst either in fixed addressing mode or in contiguous-data incremented mode. If contiguously incremented (GPDMA_CxTR1.SINC = 1), then the additional address offset value is the programmed burst size, as defined by GPDMA_CxTR1.SBL_1[5:0] and GPDMA_CxTR1.SDW_LOG2[21:0] the additional source incremented/decremented offset value as programmed by GPDMA_CxBR1.SDEC and GPDMA_CxTR3.SAO[12:0] once/if completed source block transfer, for a channel x with 2D addressing capability (x = 12 to 15). additional block repeat source incremented/decremented offset value as programmed by GPDMA_CxBR1.BRSDEC and GPDMA_CxBR2.BRSAO[15:0] In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by GPDMA from the memory, provided the LLI is set with GPDMA_CxLLR.USA = 1. Note: A source address must be aligned with the programmed data width of a source single (SA[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued. When the source block size is not a multiple of the source burst size and is a multiple of the source data width, the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied.
bits : 0 - 31 (32 bit)
access : read-write

GPDMA_C1DAR

GPDMA channel 1 destination address register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DA : destination address This field is the pointer to the address from which the next data is written. During the channel activity, depending on the destination addressing mode (GPDMA_CxTR1.DINC), this field is kept fixed or incremented by the data width (GPDMA_CxTR1.DDW_LOG2[21:0]) after each single destination data, reflecting the next address from which data is written. During the channel activity, this address is updated after each completed destination burst, consequently to: the programmed destination burst either in fixed addressing mode or in contiguous-data incremented mode. If contiguously incremented (GPDMA_CxTR1.DINC = 1), then the additional address offset value is the programmed burst size, as defined by GPDMA_CxTR1.DBL_1[5:0] and GPDMA_CxTR1.DDW_LOG2[1:0] the additional destination incremented/decremented offset value as programmed by GPDMA_CxBR1.DDEC and GPDMA_CxTR3.DAO[12:0] once/if completed destination block transfer, for a channel x with 2D addressing capability (x = 12 to 15), the additional block repeat destination incremented/decremented offset value as programmed by GPDMA_CxBR1.BRDDEC and GPDMA_CxBR2.BRDAO[15:0] In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by the GPDMA from the memory, provided the LLI is set with GPDMA_CxLLR.UDA = 1. Note: A destination address must be aligned with the programmed data width of a destination burst (DA[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued.
bits : 0 - 31 (32 bit)
access : read-write

GPDMA_C1LLR

GPDMA channel 1 linked-list address register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LA : pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list GPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list GPDMA internal register file (GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.
bits : 2 - 15 (14 bit)
access : read-write

ULL : Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxLLR update

0x1 : B_0x1

GPDMA_CxLLR update

End of enumeration elements list.

UDA : Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxDAR update

0x1 : B_0x1

GPDMA_CxDAR update

End of enumeration elements list.

USA : update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxSAR update

0x1 : B_0x1

GPDMA_CxSAR update

End of enumeration elements list.

UB1 : Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during the link transfer. If UB1 = 0 and if GPDMA_CxLLR ≠ 0, the linked-list is not completed. GPDMA_CxBR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)

0x1 : B_0x1

GPDMA_CxBR1 update

End of enumeration elements list.

UT2 : Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR2 update

0x1 : B_0x1

GPDMA_CxTR2 update

End of enumeration elements list.

UT1 : Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR1 update

0x1 : B_0x1

GPDMA_CxTR1 update

End of enumeration elements list.

GPDMA_C2LBAR

GPDMA channel 2 linked-list base address register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBA : linked-list base address of GPDMA channel x
bits : 16 - 31 (16 bit)
access : read-write

GPDMA_C2FCR

GPDMA channel 2 flag clear register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCF : transfer complete flag clear
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TCF flag cleared

End of enumeration elements list.

HTF : half transfer flag clear
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding HTF flag cleared

End of enumeration elements list.

DTEF : data transfer error flag clear
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding DTEF flag cleared

End of enumeration elements list.

ULEF : update link transfer error flag clear
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding ULEF flag cleared

End of enumeration elements list.

USEF : user setting error flag clear
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding USEF flag cleared

End of enumeration elements list.

SUSPF : completed suspension flag clear
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding SUSPF flag cleared

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TOF flag cleared

End of enumeration elements list.

GPDMA_C2SR

GPDMA channel 2 status register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDLEF : idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state).
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

channel not in idle state

0x1 : B_0x1

channel in idle state

End of enumeration elements list.

TCF : transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (GPDMA_CxTR2.TCEM[1:0]).
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no transfer complete event

0x1 : B_0x1

a transfer complete event occurred

End of enumeration elements list.

HTF : half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode (GPDMA_CxTR2.TCEM[1:0]). An half block transfer occurs when half of the bytes of the source block size (rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. An half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2)) has been transferred to the destination.
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no half transfer event

0x1 : B_0x1

an half transfer event occurred

End of enumeration elements list.

DTEF : data transfer error flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no data transfer error event

0x1 : B_0x1

a master bus error event occurred on a data transfer

End of enumeration elements list.

ULEF : update link transfer error flag
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no update link transfer error event

0x1 : B_0x1

a master bus error event occurred while updating a linked-list register from memory

End of enumeration elements list.

USEF : user setting error flag
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no user setting error event

0x1 : B_0x1

a user setting error event occurred

End of enumeration elements list.

SUSPF : completed suspension flag
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no completed suspension event

0x1 : B_0x1

a completed suspension event occurred

End of enumeration elements list.

TOF : trigger overrun flag
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no trigger overrun event

0x1 : B_0x1

a trigger overrun event occurred

End of enumeration elements list.

FIFOL : monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (see GPDMA_CxTR1.DDW_LOG2[1:0], in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0], to know how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be suspended (GPDMA_CxSR.SUSPF = 1).
bits : 16 - 23 (8 bit)
access : read-only

GPDMA_C2CR

GPDMA channel 2 control register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN : enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

write: ignored, read: channel disabled

0x1 : B_0x1

write: enable channel, read: channel enabled

End of enumeration elements list.

RESET : reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (GPDMA_CxSR.SUSPF = 1 and GPDMA_CxSR.IDLEF = GPDMA_CxCR.EN = 1) - channel in disabled state (GPDMA_CxSR.IDLEF = 1 and GPDMA_CxCR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR) before enabling again the channel (see the programming sequence in ).
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no channel reset

0x1 : B_0x1

channel reset

End of enumeration elements list.

SUSP : suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going GPDMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in .
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

write: resume channel, read: channel not suspended

0x1 : B_0x1

write: suspend channel, read: channel suspended.

End of enumeration elements list.

TCIE : transfer complete interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

HTIE : half transfer complete interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

DTEIE : data transfer error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

ULEIE : update link transfer error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

USEIE : user setting error interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

SUSPIE : completed suspension interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

TOIE : trigger overrun interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

LSM : Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until GPDMA_CxBR1.BNDT[15:0] = 0 and GPDMA_CxBR1.BRC[10:0] = 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then GPDMA_CxBR1.BNDT[15:0] = 0 and GPDMA_CxBR1.BRC[10:0] = 0 if present.

0x1 : B_0x1

channel executed once for the current LLI

End of enumeration elements list.

LAP : linked-list allocated port This bit is used to allocate the master port for the update of the GPDMA linked-list registers from the memory. Note: This bit must be written when EN=0. This bit is read-only when EN=1.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

PRIO : priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

low priority, low weight

0x1 : B_0x1

low priority, mid weight

0x2 : B_0x2

low priority, high weight

0x3 : B_0x3

high priority

End of enumeration elements list.

GPDMA_C2TR1

GPDMA channel 2 transfer register 1
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no byte-based exchange within the unaligned half-word of each source word

0x1 : B_0x1

the two consecutive bytes within the unaligned half-word of each source word are exchanged.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

DBX : destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte:
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no byte-based exchange within half-word

0x1 : B_0x1

the two consecutive (post PAM) bytes are exchanged in each destination half-word.

End of enumeration elements list.

DHX : destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word:
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no halfword-based exchanged within word

0x1 : B_0x1

the two consecutive (post PAM) half-words are exchanged in each destination word.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

GPDMA_C2TR2

GPDMA channel 2 transfer register 2
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWREQ : software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no software request. The selected hardware request REQSEL[6:0] is taken into account.

0x1 : B_0x1

software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)

0x1 : B_0x1

selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.

0x1 : B_0x1

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel x = 0 to 11, same as 00 channel x=12 to 15, at 2D/repeated block level, the

0x2 : B_0x2

at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.

0x3 : B_0x3

End of enumeration elements list.

TRIGPOL : trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0].
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no trigger (masked trigger event)

0x1 : B_0x1

trigger on the rising edge

0x2 : B_0x2

trigger on the falling edge

0x3 : B_0x3

same as 00

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.

0x1 : B_0x1

0x2 : B_0x2

0x3 : B_0x3

End of enumeration elements list.

GPDMA_C2BR1

GPDMA channel 2 block register 1
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C2SAR

GPDMA channel 2 source address register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C2DAR

GPDMA channel 2 destination address register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C2LLR

GPDMA channel 2 linked-list address register
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ULL : Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxLLR update

0x1 : B_0x1

GPDMA_CxLLR update

End of enumeration elements list.

UDA : Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxDAR update

0x1 : B_0x1

GPDMA_CxDAR update

End of enumeration elements list.

USA : update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxSAR update

0x1 : B_0x1

GPDMA_CxSAR update

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)

0x1 : B_0x1

GPDMA_CxBR1 update

End of enumeration elements list.

UT2 : Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR2 update

0x1 : B_0x1

GPDMA_CxTR2 update

End of enumeration elements list.

UT1 : Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR1 update

0x1 : B_0x1

GPDMA_CxTR1 update

End of enumeration elements list.

GPDMA_C3LBAR

GPDMA channel 3 linked-list base address register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBA : linked-list base address of GPDMA channel x
bits : 16 - 31 (16 bit)
access : read-write

GPDMA_C3FCR

GPDMA channel 3 flag clear register
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCF : transfer complete flag clear
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TCF flag cleared

End of enumeration elements list.

HTF : half transfer flag clear
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding HTF flag cleared

End of enumeration elements list.

DTEF : data transfer error flag clear
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding DTEF flag cleared

End of enumeration elements list.

ULEF : update link transfer error flag clear
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding ULEF flag cleared

End of enumeration elements list.

USEF : user setting error flag clear
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding USEF flag cleared

End of enumeration elements list.

SUSPF : completed suspension flag clear
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding SUSPF flag cleared

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TOF flag cleared

End of enumeration elements list.

GPDMA_C3SR

GPDMA channel 3 status register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

channel not in idle state

0x1 : B_0x1

channel in idle state

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no transfer complete event

0x1 : B_0x1

a transfer complete event occurred

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no half transfer event

0x1 : B_0x1

an half transfer event occurred

End of enumeration elements list.

DTEF : data transfer error flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no data transfer error event

0x1 : B_0x1

a master bus error event occurred on a data transfer

End of enumeration elements list.

ULEF : update link transfer error flag
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no update link transfer error event

0x1 : B_0x1

a master bus error event occurred while updating a linked-list register from memory

End of enumeration elements list.

USEF : user setting error flag
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no user setting error event

0x1 : B_0x1

a user setting error event occurred

End of enumeration elements list.

SUSPF : completed suspension flag
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no completed suspension event

0x1 : B_0x1

a completed suspension event occurred

End of enumeration elements list.

TOF : trigger overrun flag
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no trigger overrun event

0x1 : B_0x1

a trigger overrun event occurred

End of enumeration elements list.

GPDMA_C3CR

GPDMA channel 3 control register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

write: ignored, read: channel disabled

0x1 : B_0x1

write: enable channel, read: channel enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no channel reset

0x1 : B_0x1

channel reset

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

write: resume channel, read: channel not suspended

0x1 : B_0x1

write: suspend channel, read: channel suspended.

End of enumeration elements list.

TCIE : transfer complete interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

HTIE : half transfer complete interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

DTEIE : data transfer error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

ULEIE : update link transfer error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

USEIE : user setting error interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

SUSPIE : completed suspension interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

TOIE : trigger overrun interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel executed once for the current LLI

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

PRIO : priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

low priority, low weight

0x1 : B_0x1

low priority, mid weight

0x2 : B_0x2

low priority, high weight

0x3 : B_0x3

high priority

End of enumeration elements list.

GPDMA_C3TR1

GPDMA channel 3 transfer register 1
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no byte-based exchange within the unaligned half-word of each source word

0x1 : B_0x1

the two consecutive bytes within the unaligned half-word of each source word are exchanged.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

DBX : destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte:
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no byte-based exchange within half-word

0x1 : B_0x1

the two consecutive (post PAM) bytes are exchanged in each destination half-word.

End of enumeration elements list.

DHX : destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word:
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no halfword-based exchanged within word

0x1 : B_0x1

the two consecutive (post PAM) half-words are exchanged in each destination word.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

GPDMA_C3TR2

GPDMA channel 3 transfer register 2
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWREQ : software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no software request. The selected hardware request REQSEL[6:0] is taken into account.

0x1 : B_0x1

software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)

0x1 : B_0x1

selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.

0x1 : B_0x1

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel x = 0 to 11, same as 00 channel x=12 to 15, at 2D/repeated block level, the

0x2 : B_0x2

at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.

0x3 : B_0x3

End of enumeration elements list.

TRIGPOL : trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0].
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no trigger (masked trigger event)

0x1 : B_0x1

trigger on the rising edge

0x2 : B_0x2

trigger on the falling edge

0x3 : B_0x3

same as 00

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.

0x1 : B_0x1

0x2 : B_0x2

0x3 : B_0x3

End of enumeration elements list.

GPDMA_C3BR1

GPDMA channel 3 block register 1
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C3SAR

GPDMA channel 3 source address register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C3DAR

GPDMA channel 3 destination address register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C3LLR

GPDMA channel 3 linked-list address register
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ULL : Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxLLR update

0x1 : B_0x1

GPDMA_CxLLR update

End of enumeration elements list.

UDA : Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxDAR update

0x1 : B_0x1

GPDMA_CxDAR update

End of enumeration elements list.

USA : update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxSAR update

0x1 : B_0x1

GPDMA_CxSAR update

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)

0x1 : B_0x1

GPDMA_CxBR1 update

End of enumeration elements list.

UT2 : Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR2 update

0x1 : B_0x1

GPDMA_CxTR2 update

End of enumeration elements list.

UT1 : Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR1 update

0x1 : B_0x1

GPDMA_CxTR1 update

End of enumeration elements list.

GPDMA_C4LBAR

GPDMA channel 4 linked-list base address register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBA : linked-list base address of GPDMA channel x
bits : 16 - 31 (16 bit)
access : read-write

GPDMA_C4FCR

GPDMA channel 4 flag clear register
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCF : transfer complete flag clear
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TCF flag cleared

End of enumeration elements list.

HTF : half transfer flag clear
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding HTF flag cleared

End of enumeration elements list.

DTEF : data transfer error flag clear
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding DTEF flag cleared

End of enumeration elements list.

ULEF : update link transfer error flag clear
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding ULEF flag cleared

End of enumeration elements list.

USEF : user setting error flag clear
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding USEF flag cleared

End of enumeration elements list.

SUSPF : completed suspension flag clear
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding SUSPF flag cleared

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TOF flag cleared

End of enumeration elements list.

GPDMA_C4SR

GPDMA channel 4 status register
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

channel not in idle state

0x1 : B_0x1

channel in idle state

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no transfer complete event

0x1 : B_0x1

a transfer complete event occurred

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no half transfer event

0x1 : B_0x1

an half transfer event occurred

End of enumeration elements list.

DTEF : data transfer error flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no data transfer error event

0x1 : B_0x1

a master bus error event occurred on a data transfer

End of enumeration elements list.

ULEF : update link transfer error flag
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no update link transfer error event

0x1 : B_0x1

a master bus error event occurred while updating a linked-list register from memory

End of enumeration elements list.

USEF : user setting error flag
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no user setting error event

0x1 : B_0x1

a user setting error event occurred

End of enumeration elements list.

SUSPF : completed suspension flag
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no completed suspension event

0x1 : B_0x1

a completed suspension event occurred

End of enumeration elements list.

TOF : trigger overrun flag
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no trigger overrun event

0x1 : B_0x1

a trigger overrun event occurred

End of enumeration elements list.

GPDMA_C4CR

GPDMA channel 4 control register
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

write: ignored, read: channel disabled

0x1 : B_0x1

write: enable channel, read: channel enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no channel reset

0x1 : B_0x1

channel reset

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

write: resume channel, read: channel not suspended

0x1 : B_0x1

write: suspend channel, read: channel suspended.

End of enumeration elements list.

TCIE : transfer complete interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

HTIE : half transfer complete interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

DTEIE : data transfer error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

ULEIE : update link transfer error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

USEIE : user setting error interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

SUSPIE : completed suspension interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

TOIE : trigger overrun interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel executed once for the current LLI

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

PRIO : priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

low priority, low weight

0x1 : B_0x1

low priority, mid weight

0x2 : B_0x2

low priority, high weight

0x3 : B_0x3

high priority

End of enumeration elements list.

GPDMA_C4TR1

GPDMA channel 4 transfer register 1
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no byte-based exchange within the unaligned half-word of each source word

0x1 : B_0x1

the two consecutive bytes within the unaligned half-word of each source word are exchanged.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

DBX : destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte:
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no byte-based exchange within half-word

0x1 : B_0x1

the two consecutive (post PAM) bytes are exchanged in each destination half-word.

End of enumeration elements list.

DHX : destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word:
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no halfword-based exchanged within word

0x1 : B_0x1

the two consecutive (post PAM) half-words are exchanged in each destination word.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

GPDMA_C4TR2

GPDMA channel 4 transfer register 2
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWREQ : software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no software request. The selected hardware request REQSEL[6:0] is taken into account.

0x1 : B_0x1

software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)

0x1 : B_0x1

selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.

0x1 : B_0x1

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel x = 0 to 11, same as 00 channel x=12 to 15, at 2D/repeated block level, the

0x2 : B_0x2

at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.

0x3 : B_0x3

End of enumeration elements list.

TRIGPOL : trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0].
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no trigger (masked trigger event)

0x1 : B_0x1

trigger on the rising edge

0x2 : B_0x2

trigger on the falling edge

0x3 : B_0x3

same as 00

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.

0x1 : B_0x1

0x2 : B_0x2

0x3 : B_0x3

End of enumeration elements list.

GPDMA_C4BR1

GPDMA channel 4 block register 1
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C4SAR

GPDMA channel 4 source address register
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C4DAR

GPDMA channel 4 destination address register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C4LLR

GPDMA channel 4 linked-list address register
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ULL : Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxLLR update

0x1 : B_0x1

GPDMA_CxLLR update

End of enumeration elements list.

UDA : Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxDAR update

0x1 : B_0x1

GPDMA_CxDAR update

End of enumeration elements list.

USA : update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxSAR update

0x1 : B_0x1

GPDMA_CxSAR update

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)

0x1 : B_0x1

GPDMA_CxBR1 update

End of enumeration elements list.

UT2 : Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR2 update

0x1 : B_0x1

GPDMA_CxTR2 update

End of enumeration elements list.

UT1 : Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR1 update

0x1 : B_0x1

GPDMA_CxTR1 update

End of enumeration elements list.

GPDMA_C5LBAR

GPDMA channel 5 linked-list base address register
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBA : linked-list base address of GPDMA channel x
bits : 16 - 31 (16 bit)
access : read-write

GPDMA_C5FCR

GPDMA channel 5 flag clear register
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCF : transfer complete flag clear
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TCF flag cleared

End of enumeration elements list.

HTF : half transfer flag clear
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding HTF flag cleared

End of enumeration elements list.

DTEF : data transfer error flag clear
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding DTEF flag cleared

End of enumeration elements list.

ULEF : update link transfer error flag clear
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding ULEF flag cleared

End of enumeration elements list.

USEF : user setting error flag clear
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding USEF flag cleared

End of enumeration elements list.

SUSPF : completed suspension flag clear
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding SUSPF flag cleared

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TOF flag cleared

End of enumeration elements list.

GPDMA_C5SR

GPDMA channel 5 status register
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

channel not in idle state

0x1 : B_0x1

channel in idle state

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no transfer complete event

0x1 : B_0x1

a transfer complete event occurred

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no half transfer event

0x1 : B_0x1

an half transfer event occurred

End of enumeration elements list.

DTEF : data transfer error flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no data transfer error event

0x1 : B_0x1

a master bus error event occurred on a data transfer

End of enumeration elements list.

ULEF : update link transfer error flag
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no update link transfer error event

0x1 : B_0x1

a master bus error event occurred while updating a linked-list register from memory

End of enumeration elements list.

USEF : user setting error flag
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no user setting error event

0x1 : B_0x1

a user setting error event occurred

End of enumeration elements list.

SUSPF : completed suspension flag
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no completed suspension event

0x1 : B_0x1

a completed suspension event occurred

End of enumeration elements list.

TOF : trigger overrun flag
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no trigger overrun event

0x1 : B_0x1

a trigger overrun event occurred

End of enumeration elements list.

GPDMA_C5CR

GPDMA channel 5 control register
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

write: ignored, read: channel disabled

0x1 : B_0x1

write: enable channel, read: channel enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no channel reset

0x1 : B_0x1

channel reset

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

write: resume channel, read: channel not suspended

0x1 : B_0x1

write: suspend channel, read: channel suspended.

End of enumeration elements list.

TCIE : transfer complete interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

HTIE : half transfer complete interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

DTEIE : data transfer error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

ULEIE : update link transfer error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

USEIE : user setting error interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

SUSPIE : completed suspension interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

TOIE : trigger overrun interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel executed once for the current LLI

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

PRIO : priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

low priority, low weight

0x1 : B_0x1

low priority, mid weight

0x2 : B_0x2

low priority, high weight

0x3 : B_0x3

high priority

End of enumeration elements list.

GPDMA_C5TR1

GPDMA channel 5 transfer register 1
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no byte-based exchange within the unaligned half-word of each source word

0x1 : B_0x1

the two consecutive bytes within the unaligned half-word of each source word are exchanged.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

DBX : destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte:
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no byte-based exchange within half-word

0x1 : B_0x1

the two consecutive (post PAM) bytes are exchanged in each destination half-word.

End of enumeration elements list.

DHX : destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word:
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no halfword-based exchanged within word

0x1 : B_0x1

the two consecutive (post PAM) half-words are exchanged in each destination word.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

GPDMA_C5TR2

GPDMA channel 5 transfer register 2
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWREQ : software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no software request. The selected hardware request REQSEL[6:0] is taken into account.

0x1 : B_0x1

software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)

0x1 : B_0x1

selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.

0x1 : B_0x1

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel x = 0 to 11, same as 00 channel x=12 to 15, at 2D/repeated block level, the

0x2 : B_0x2

at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.

0x3 : B_0x3

End of enumeration elements list.

TRIGPOL : trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0].
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no trigger (masked trigger event)

0x1 : B_0x1

trigger on the rising edge

0x2 : B_0x2

trigger on the falling edge

0x3 : B_0x3

same as 00

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.

0x1 : B_0x1

0x2 : B_0x2

0x3 : B_0x3

End of enumeration elements list.

GPDMA_C5BR1

GPDMA channel 5 block register 1
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C5SAR

GPDMA channel 5 source address register
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C5DAR

GPDMA channel 5 destination address register
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C5LLR

GPDMA channel 5 linked-list address register
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ULL : Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxLLR update

0x1 : B_0x1

GPDMA_CxLLR update

End of enumeration elements list.

UDA : Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxDAR update

0x1 : B_0x1

GPDMA_CxDAR update

End of enumeration elements list.

USA : update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxSAR update

0x1 : B_0x1

GPDMA_CxSAR update

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)

0x1 : B_0x1

GPDMA_CxBR1 update

End of enumeration elements list.

UT2 : Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR2 update

0x1 : B_0x1

GPDMA_CxTR2 update

End of enumeration elements list.

UT1 : Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR1 update

0x1 : B_0x1

GPDMA_CxTR1 update

End of enumeration elements list.

GPDMA_C6LBAR

GPDMA channel 6 linked-list base address register
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBA : linked-list base address of GPDMA channel x
bits : 16 - 31 (16 bit)
access : read-write

GPDMA_C6FCR

GPDMA channel 6 flag clear register
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCF : transfer complete flag clear
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TCF flag cleared

End of enumeration elements list.

HTF : half transfer flag clear
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding HTF flag cleared

End of enumeration elements list.

DTEF : data transfer error flag clear
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding DTEF flag cleared

End of enumeration elements list.

ULEF : update link transfer error flag clear
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding ULEF flag cleared

End of enumeration elements list.

USEF : user setting error flag clear
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding USEF flag cleared

End of enumeration elements list.

SUSPF : completed suspension flag clear
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding SUSPF flag cleared

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TOF flag cleared

End of enumeration elements list.

GPDMA_C6SR

GPDMA channel 6 status register
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

channel not in idle state

0x1 : B_0x1

channel in idle state

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no transfer complete event

0x1 : B_0x1

a transfer complete event occurred

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no half transfer event

0x1 : B_0x1

an half transfer event occurred

End of enumeration elements list.

DTEF : data transfer error flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no data transfer error event

0x1 : B_0x1

a master bus error event occurred on a data transfer

End of enumeration elements list.

ULEF : update link transfer error flag
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no update link transfer error event

0x1 : B_0x1

a master bus error event occurred while updating a linked-list register from memory

End of enumeration elements list.

USEF : user setting error flag
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no user setting error event

0x1 : B_0x1

a user setting error event occurred

End of enumeration elements list.

SUSPF : completed suspension flag
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no completed suspension event

0x1 : B_0x1

a completed suspension event occurred

End of enumeration elements list.

TOF : trigger overrun flag
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no trigger overrun event

0x1 : B_0x1

a trigger overrun event occurred

End of enumeration elements list.

GPDMA_C6CR

GPDMA channel 6 control register
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

write: ignored, read: channel disabled

0x1 : B_0x1

write: enable channel, read: channel enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no channel reset

0x1 : B_0x1

channel reset

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

write: resume channel, read: channel not suspended

0x1 : B_0x1

write: suspend channel, read: channel suspended.

End of enumeration elements list.

TCIE : transfer complete interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

HTIE : half transfer complete interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

DTEIE : data transfer error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

ULEIE : update link transfer error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

USEIE : user setting error interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

SUSPIE : completed suspension interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

TOIE : trigger overrun interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel executed once for the current LLI

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

PRIO : priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

low priority, low weight

0x1 : B_0x1

low priority, mid weight

0x2 : B_0x2

low priority, high weight

0x3 : B_0x3

high priority

End of enumeration elements list.

GPDMA_C6TR1

GPDMA channel 6 transfer register 1
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no byte-based exchange within the unaligned half-word of each source word

0x1 : B_0x1

the two consecutive bytes within the unaligned half-word of each source word are exchanged.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

DBX : destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte:
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no byte-based exchange within half-word

0x1 : B_0x1

the two consecutive (post PAM) bytes are exchanged in each destination half-word.

End of enumeration elements list.

DHX : destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word:
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no halfword-based exchanged within word

0x1 : B_0x1

the two consecutive (post PAM) half-words are exchanged in each destination word.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

GPDMA_C6TR2

GPDMA channel 6 transfer register 2
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWREQ : software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no software request. The selected hardware request REQSEL[6:0] is taken into account.

0x1 : B_0x1

software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)

0x1 : B_0x1

selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.

0x1 : B_0x1

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel x = 0 to 11, same as 00 channel x=12 to 15, at 2D/repeated block level, the

0x2 : B_0x2

at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.

0x3 : B_0x3

End of enumeration elements list.

TRIGPOL : trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0].
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no trigger (masked trigger event)

0x1 : B_0x1

trigger on the rising edge

0x2 : B_0x2

trigger on the falling edge

0x3 : B_0x3

same as 00

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.

0x1 : B_0x1

0x2 : B_0x2

0x3 : B_0x3

End of enumeration elements list.

GPDMA_C6BR1

GPDMA channel 6 block register 1
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C6SAR

GPDMA channel 6 source address register
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C6DAR

GPDMA channel 6 destination address register
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C6LLR

GPDMA channel 6 linked-list address register
address_offset : 0x3CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ULL : Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxLLR update

0x1 : B_0x1

GPDMA_CxLLR update

End of enumeration elements list.

UDA : Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxDAR update

0x1 : B_0x1

GPDMA_CxDAR update

End of enumeration elements list.

USA : update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxSAR update

0x1 : B_0x1

GPDMA_CxSAR update

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)

0x1 : B_0x1

GPDMA_CxBR1 update

End of enumeration elements list.

UT2 : Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR2 update

0x1 : B_0x1

GPDMA_CxTR2 update

End of enumeration elements list.

UT1 : Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR1 update

0x1 : B_0x1

GPDMA_CxTR1 update

End of enumeration elements list.

GPDMA_C7LBAR

GPDMA channel 7 linked-list base address register
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBA : linked-list base address of GPDMA channel x
bits : 16 - 31 (16 bit)
access : read-write

GPDMA_C7FCR

GPDMA channel 7 flag clear register
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCF : transfer complete flag clear
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TCF flag cleared

End of enumeration elements list.

HTF : half transfer flag clear
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding HTF flag cleared

End of enumeration elements list.

DTEF : data transfer error flag clear
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding DTEF flag cleared

End of enumeration elements list.

ULEF : update link transfer error flag clear
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding ULEF flag cleared

End of enumeration elements list.

USEF : user setting error flag clear
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding USEF flag cleared

End of enumeration elements list.

SUSPF : completed suspension flag clear
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding SUSPF flag cleared

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TOF flag cleared

End of enumeration elements list.

GPDMA_C7SR

GPDMA channel 7 status register
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

channel not in idle state

0x1 : B_0x1

channel in idle state

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no transfer complete event

0x1 : B_0x1

a transfer complete event occurred

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no half transfer event

0x1 : B_0x1

an half transfer event occurred

End of enumeration elements list.

DTEF : data transfer error flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no data transfer error event

0x1 : B_0x1

a master bus error event occurred on a data transfer

End of enumeration elements list.

ULEF : update link transfer error flag
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no update link transfer error event

0x1 : B_0x1

a master bus error event occurred while updating a linked-list register from memory

End of enumeration elements list.

USEF : user setting error flag
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no user setting error event

0x1 : B_0x1

a user setting error event occurred

End of enumeration elements list.

SUSPF : completed suspension flag
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no completed suspension event

0x1 : B_0x1

a completed suspension event occurred

End of enumeration elements list.

TOF : trigger overrun flag
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no trigger overrun event

0x1 : B_0x1

a trigger overrun event occurred

End of enumeration elements list.

GPDMA_C7CR

GPDMA channel 7 control register
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

write: ignored, read: channel disabled

0x1 : B_0x1

write: enable channel, read: channel enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no channel reset

0x1 : B_0x1

channel reset

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

write: resume channel, read: channel not suspended

0x1 : B_0x1

write: suspend channel, read: channel suspended.

End of enumeration elements list.

TCIE : transfer complete interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

HTIE : half transfer complete interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

DTEIE : data transfer error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

ULEIE : update link transfer error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

USEIE : user setting error interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

SUSPIE : completed suspension interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

TOIE : trigger overrun interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel executed once for the current LLI

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

PRIO : priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

low priority, low weight

0x1 : B_0x1

low priority, mid weight

0x2 : B_0x2

low priority, high weight

0x3 : B_0x3

high priority

End of enumeration elements list.

GPDMA_PRIVCFGR

GPDMA privileged configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRIV0 : PRIV0
bits : 0 - 0 (1 bit)
access : read-write

PRIV1 : PRIV1
bits : 1 - 1 (1 bit)
access : read-write

PRIV2 : PRIV2
bits : 2 - 2 (1 bit)
access : read-write

PRIV3 : PRIV3
bits : 3 - 3 (1 bit)
access : read-write

PRIV4 : PRIV4
bits : 4 - 4 (1 bit)
access : read-write

PRIV5 : PRIV5
bits : 5 - 5 (1 bit)
access : read-write

PRIV6 : PRIV6
bits : 6 - 6 (1 bit)
access : read-write

PRIV7 : PRIV7
bits : 7 - 7 (1 bit)
access : read-write

PRIV8 : PRIV8
bits : 8 - 8 (1 bit)
access : read-write

PRIV9 : PRIV9
bits : 9 - 9 (1 bit)
access : read-write

PRIV10 : PRIV10
bits : 10 - 10 (1 bit)
access : read-write

PRIV11 : PRIV11
bits : 11 - 11 (1 bit)
access : read-write

PRIV12 : PRIV12
bits : 12 - 12 (1 bit)
access : read-write

PRIV13 : PRIV13
bits : 13 - 13 (1 bit)
access : read-write

PRIV14 : PRIV14
bits : 14 - 14 (1 bit)
access : read-write

PRIV15 : PRIV15
bits : 15 - 15 (1 bit)
access : read-write

GPDMA_C7TR1

GPDMA channel 7 transfer register 1
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no byte-based exchange within the unaligned half-word of each source word

0x1 : B_0x1

the two consecutive bytes within the unaligned half-word of each source word are exchanged.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

DBX : destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte:
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no byte-based exchange within half-word

0x1 : B_0x1

the two consecutive (post PAM) bytes are exchanged in each destination half-word.

End of enumeration elements list.

DHX : destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word:
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no halfword-based exchanged within word

0x1 : B_0x1

the two consecutive (post PAM) half-words are exchanged in each destination word.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

GPDMA_C7TR2

GPDMA channel 7 transfer register 2
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWREQ : software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no software request. The selected hardware request REQSEL[6:0] is taken into account.

0x1 : B_0x1

software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)

0x1 : B_0x1

selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.

0x1 : B_0x1

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel x = 0 to 11, same as 00 channel x=12 to 15, at 2D/repeated block level, the

0x2 : B_0x2

at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.

0x3 : B_0x3

End of enumeration elements list.

TRIGPOL : trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0].
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no trigger (masked trigger event)

0x1 : B_0x1

trigger on the rising edge

0x2 : B_0x2

trigger on the falling edge

0x3 : B_0x3

same as 00

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.

0x1 : B_0x1

0x2 : B_0x2

0x3 : B_0x3

End of enumeration elements list.

GPDMA_C7BR1

GPDMA channel 7 block register 1
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C7SAR

GPDMA channel 7 source address register
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C7DAR

GPDMA channel 7 destination address register
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C7LLR

GPDMA channel 7 linked-list address register
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ULL : Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxLLR update

0x1 : B_0x1

GPDMA_CxLLR update

End of enumeration elements list.

UDA : Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxDAR update

0x1 : B_0x1

GPDMA_CxDAR update

End of enumeration elements list.

USA : update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxSAR update

0x1 : B_0x1

GPDMA_CxSAR update

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)

0x1 : B_0x1

GPDMA_CxBR1 update

End of enumeration elements list.

UT2 : Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR2 update

0x1 : B_0x1

GPDMA_CxTR2 update

End of enumeration elements list.

UT1 : Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR1 update

0x1 : B_0x1

GPDMA_CxTR1 update

End of enumeration elements list.

GPDMA_C8LBAR

GPDMA channel 8 linked-list base address register
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBA : linked-list base address of GPDMA channel x
bits : 16 - 31 (16 bit)
access : read-write

GPDMA_C8FCR

GPDMA channel 8 flag clear register
address_offset : 0x45C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCF : transfer complete flag clear
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TCF flag cleared

End of enumeration elements list.

HTF : half transfer flag clear
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding HTF flag cleared

End of enumeration elements list.

DTEF : data transfer error flag clear
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding DTEF flag cleared

End of enumeration elements list.

ULEF : update link transfer error flag clear
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding ULEF flag cleared

End of enumeration elements list.

USEF : user setting error flag clear
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding USEF flag cleared

End of enumeration elements list.

SUSPF : completed suspension flag clear
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding SUSPF flag cleared

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TOF flag cleared

End of enumeration elements list.

GPDMA_C8SR

GPDMA channel 8 status register
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

channel not in idle state

0x1 : B_0x1

channel in idle state

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no transfer complete event

0x1 : B_0x1

a transfer complete event occurred

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no half transfer event

0x1 : B_0x1

an half transfer event occurred

End of enumeration elements list.

DTEF : data transfer error flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no data transfer error event

0x1 : B_0x1

a master bus error event occurred on a data transfer

End of enumeration elements list.

ULEF : update link transfer error flag
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no update link transfer error event

0x1 : B_0x1

a master bus error event occurred while updating a linked-list register from memory

End of enumeration elements list.

USEF : user setting error flag
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no user setting error event

0x1 : B_0x1

a user setting error event occurred

End of enumeration elements list.

SUSPF : completed suspension flag
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no completed suspension event

0x1 : B_0x1

a completed suspension event occurred

End of enumeration elements list.

TOF : trigger overrun flag
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no trigger overrun event

0x1 : B_0x1

a trigger overrun event occurred

End of enumeration elements list.

GPDMA_C8CR

GPDMA channel 8 control register
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

write: ignored, read: channel disabled

0x1 : B_0x1

write: enable channel, read: channel enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no channel reset

0x1 : B_0x1

channel reset

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

write: resume channel, read: channel not suspended

0x1 : B_0x1

write: suspend channel, read: channel suspended.

End of enumeration elements list.

TCIE : transfer complete interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

HTIE : half transfer complete interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

DTEIE : data transfer error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

ULEIE : update link transfer error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

USEIE : user setting error interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

SUSPIE : completed suspension interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

TOIE : trigger overrun interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel executed once for the current LLI

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

PRIO : priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

low priority, low weight

0x1 : B_0x1

low priority, mid weight

0x2 : B_0x2

low priority, high weight

0x3 : B_0x3

high priority

End of enumeration elements list.

GPDMA_C8TR1

GPDMA channel 8 transfer register 1
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no byte-based exchange within the unaligned half-word of each source word

0x1 : B_0x1

the two consecutive bytes within the unaligned half-word of each source word are exchanged.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

DBX : destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte:
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no byte-based exchange within half-word

0x1 : B_0x1

the two consecutive (post PAM) bytes are exchanged in each destination half-word.

End of enumeration elements list.

DHX : destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word:
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no halfword-based exchanged within word

0x1 : B_0x1

the two consecutive (post PAM) half-words are exchanged in each destination word.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

GPDMA_C8TR2

GPDMA channel 8 transfer register 2
address_offset : 0x494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWREQ : software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no software request. The selected hardware request REQSEL[6:0] is taken into account.

0x1 : B_0x1

software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)

0x1 : B_0x1

selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.

0x1 : B_0x1

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel x = 0 to 11, same as 00 channel x=12 to 15, at 2D/repeated block level, the

0x2 : B_0x2

at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.

0x3 : B_0x3

End of enumeration elements list.

TRIGPOL : trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0].
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no trigger (masked trigger event)

0x1 : B_0x1

trigger on the rising edge

0x2 : B_0x2

trigger on the falling edge

0x3 : B_0x3

same as 00

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.

0x1 : B_0x1

0x2 : B_0x2

0x3 : B_0x3

End of enumeration elements list.

GPDMA_C8BR1

GPDMA channel 8 block register 1
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C8SAR

GPDMA channel 8 source address register
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C8DAR

GPDMA channel 8 destination address register
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C8LLR

GPDMA channel 8 linked-list address register
address_offset : 0x4CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ULL : Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxLLR update

0x1 : B_0x1

GPDMA_CxLLR update

End of enumeration elements list.

UDA : Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxDAR update

0x1 : B_0x1

GPDMA_CxDAR update

End of enumeration elements list.

USA : update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxSAR update

0x1 : B_0x1

GPDMA_CxSAR update

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)

0x1 : B_0x1

GPDMA_CxBR1 update

End of enumeration elements list.

UT2 : Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR2 update

0x1 : B_0x1

GPDMA_CxTR2 update

End of enumeration elements list.

UT1 : Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR1 update

0x1 : B_0x1

GPDMA_CxTR1 update

End of enumeration elements list.

GPDMA_C9LBAR

GPDMA channel 9 linked-list base address register
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBA : linked-list base address of GPDMA channel x
bits : 16 - 31 (16 bit)
access : read-write

GPDMA_C9FCR

GPDMA channel 9 flag clear register
address_offset : 0x4DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCF : transfer complete flag clear
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TCF flag cleared

End of enumeration elements list.

HTF : half transfer flag clear
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding HTF flag cleared

End of enumeration elements list.

DTEF : data transfer error flag clear
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding DTEF flag cleared

End of enumeration elements list.

ULEF : update link transfer error flag clear
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding ULEF flag cleared

End of enumeration elements list.

USEF : user setting error flag clear
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding USEF flag cleared

End of enumeration elements list.

SUSPF : completed suspension flag clear
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding SUSPF flag cleared

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TOF flag cleared

End of enumeration elements list.

GPDMA_C9SR

GPDMA channel 9 status register
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

channel not in idle state

0x1 : B_0x1

channel in idle state

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no transfer complete event

0x1 : B_0x1

a transfer complete event occurred

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no half transfer event

0x1 : B_0x1

an half transfer event occurred

End of enumeration elements list.

DTEF : data transfer error flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no data transfer error event

0x1 : B_0x1

a master bus error event occurred on a data transfer

End of enumeration elements list.

ULEF : update link transfer error flag
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no update link transfer error event

0x1 : B_0x1

a master bus error event occurred while updating a linked-list register from memory

End of enumeration elements list.

USEF : user setting error flag
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no user setting error event

0x1 : B_0x1

a user setting error event occurred

End of enumeration elements list.

SUSPF : completed suspension flag
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no completed suspension event

0x1 : B_0x1

a completed suspension event occurred

End of enumeration elements list.

TOF : trigger overrun flag
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no trigger overrun event

0x1 : B_0x1

a trigger overrun event occurred

End of enumeration elements list.

GPDMA_C9CR

GPDMA channel 9 control register
address_offset : 0x4E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

write: ignored, read: channel disabled

0x1 : B_0x1

write: enable channel, read: channel enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no channel reset

0x1 : B_0x1

channel reset

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

write: resume channel, read: channel not suspended

0x1 : B_0x1

write: suspend channel, read: channel suspended.

End of enumeration elements list.

TCIE : transfer complete interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

HTIE : half transfer complete interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

DTEIE : data transfer error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

ULEIE : update link transfer error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

USEIE : user setting error interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

SUSPIE : completed suspension interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

TOIE : trigger overrun interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel executed once for the current LLI

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

PRIO : priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

low priority, low weight

0x1 : B_0x1

low priority, mid weight

0x2 : B_0x2

low priority, high weight

0x3 : B_0x3

high priority

End of enumeration elements list.

GPDMA_C0LBAR

GPDMA channel 0 linked-list base address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBA : linked-list base address of GPDMA channel x
bits : 16 - 31 (16 bit)
access : read-write

GPDMA_C9TR1

GPDMA channel 9 transfer register 1
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no byte-based exchange within the unaligned half-word of each source word

0x1 : B_0x1

the two consecutive bytes within the unaligned half-word of each source word are exchanged.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

DBX : destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte:
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no byte-based exchange within half-word

0x1 : B_0x1

the two consecutive (post PAM) bytes are exchanged in each destination half-word.

End of enumeration elements list.

DHX : destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word:
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no halfword-based exchanged within word

0x1 : B_0x1

the two consecutive (post PAM) half-words are exchanged in each destination word.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

GPDMA_C9TR2

GPDMA channel 9 transfer register 2
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWREQ : software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no software request. The selected hardware request REQSEL[6:0] is taken into account.

0x1 : B_0x1

software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)

0x1 : B_0x1

selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.

0x1 : B_0x1

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel x = 0 to 11, same as 00 channel x=12 to 15, at 2D/repeated block level, the

0x2 : B_0x2

at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.

0x3 : B_0x3

End of enumeration elements list.

TRIGPOL : trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0].
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no trigger (masked trigger event)

0x1 : B_0x1

trigger on the rising edge

0x2 : B_0x2

trigger on the falling edge

0x3 : B_0x3

same as 00

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.

0x1 : B_0x1

0x2 : B_0x2

0x3 : B_0x3

End of enumeration elements list.

GPDMA_C9BR1

GPDMA channel 9 block register 1
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C9SAR

GPDMA channel 9 source address register
address_offset : 0x51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C9DAR

GPDMA channel 9 destination address register
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C9LLR

GPDMA channel 9 linked-list address register
address_offset : 0x54C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ULL : Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxLLR update

0x1 : B_0x1

GPDMA_CxLLR update

End of enumeration elements list.

UDA : Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxDAR update

0x1 : B_0x1

GPDMA_CxDAR update

End of enumeration elements list.

USA : update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxSAR update

0x1 : B_0x1

GPDMA_CxSAR update

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)

0x1 : B_0x1

GPDMA_CxBR1 update

End of enumeration elements list.

UT2 : Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR2 update

0x1 : B_0x1

GPDMA_CxTR2 update

End of enumeration elements list.

UT1 : Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR1 update

0x1 : B_0x1

GPDMA_CxTR1 update

End of enumeration elements list.

GPDMA_C10LBAR

GPDMA channel 10 linked-list base address register
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBA : linked-list base address of GPDMA channel x
bits : 16 - 31 (16 bit)
access : read-write

GPDMA_C10FCR

GPDMA channel 10 flag clear register
address_offset : 0x55C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCF : transfer complete flag clear
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TCF flag cleared

End of enumeration elements list.

HTF : half transfer flag clear
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding HTF flag cleared

End of enumeration elements list.

DTEF : data transfer error flag clear
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding DTEF flag cleared

End of enumeration elements list.

ULEF : update link transfer error flag clear
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding ULEF flag cleared

End of enumeration elements list.

USEF : user setting error flag clear
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding USEF flag cleared

End of enumeration elements list.

SUSPF : completed suspension flag clear
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding SUSPF flag cleared

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TOF flag cleared

End of enumeration elements list.

GPDMA_C10SR

GPDMA channel 10 status register
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

channel not in idle state

0x1 : B_0x1

channel in idle state

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no transfer complete event

0x1 : B_0x1

a transfer complete event occurred

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no half transfer event

0x1 : B_0x1

an half transfer event occurred

End of enumeration elements list.

DTEF : data transfer error flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no data transfer error event

0x1 : B_0x1

a master bus error event occurred on a data transfer

End of enumeration elements list.

ULEF : update link transfer error flag
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no update link transfer error event

0x1 : B_0x1

a master bus error event occurred while updating a linked-list register from memory

End of enumeration elements list.

USEF : user setting error flag
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no user setting error event

0x1 : B_0x1

a user setting error event occurred

End of enumeration elements list.

SUSPF : completed suspension flag
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no completed suspension event

0x1 : B_0x1

a completed suspension event occurred

End of enumeration elements list.

TOF : trigger overrun flag
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no trigger overrun event

0x1 : B_0x1

a trigger overrun event occurred

End of enumeration elements list.

GPDMA_C10CR

GPDMA channel 10 control register
address_offset : 0x564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

write: ignored, read: channel disabled

0x1 : B_0x1

write: enable channel, read: channel enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no channel reset

0x1 : B_0x1

channel reset

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

write: resume channel, read: channel not suspended

0x1 : B_0x1

write: suspend channel, read: channel suspended.

End of enumeration elements list.

TCIE : transfer complete interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

HTIE : half transfer complete interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

DTEIE : data transfer error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

ULEIE : update link transfer error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

USEIE : user setting error interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

SUSPIE : completed suspension interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

TOIE : trigger overrun interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel executed once for the current LLI

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

PRIO : priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

low priority, low weight

0x1 : B_0x1

low priority, mid weight

0x2 : B_0x2

low priority, high weight

0x3 : B_0x3

high priority

End of enumeration elements list.

GPDMA_C10TR1

GPDMA channel 10 transfer register 1
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no byte-based exchange within the unaligned half-word of each source word

0x1 : B_0x1

the two consecutive bytes within the unaligned half-word of each source word are exchanged.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

DBX : destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte:
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no byte-based exchange within half-word

0x1 : B_0x1

the two consecutive (post PAM) bytes are exchanged in each destination half-word.

End of enumeration elements list.

DHX : destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word:
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no halfword-based exchanged within word

0x1 : B_0x1

the two consecutive (post PAM) half-words are exchanged in each destination word.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

GPDMA_C10TR2

GPDMA channel 10 transfer register 2
address_offset : 0x594 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWREQ : software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no software request. The selected hardware request REQSEL[6:0] is taken into account.

0x1 : B_0x1

software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)

0x1 : B_0x1

selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.

0x1 : B_0x1

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel x = 0 to 11, same as 00 channel x=12 to 15, at 2D/repeated block level, the

0x2 : B_0x2

at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.

0x3 : B_0x3

End of enumeration elements list.

TRIGPOL : trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0].
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no trigger (masked trigger event)

0x1 : B_0x1

trigger on the rising edge

0x2 : B_0x2

trigger on the falling edge

0x3 : B_0x3

same as 00

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.

0x1 : B_0x1

0x2 : B_0x2

0x3 : B_0x3

End of enumeration elements list.

GPDMA_C10BR1

GPDMA channel 10 block register 1
address_offset : 0x598 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C10SAR

GPDMA channel 10 source address register
address_offset : 0x59C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C10DAR

GPDMA channel 10 destination address register
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C0FCR

GPDMA channel 0 flag clear register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCF : transfer complete flag clear
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TCF flag cleared

End of enumeration elements list.

HTF : half transfer flag clear
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding HTF flag cleared

End of enumeration elements list.

DTEF : data transfer error flag clear
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding DTEF flag cleared

End of enumeration elements list.

ULEF : update link transfer error flag clear
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding ULEF flag cleared

End of enumeration elements list.

USEF : user setting error flag clear
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding USEF flag cleared

End of enumeration elements list.

SUSPF : completed suspension flag clear
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding SUSPF flag cleared

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TOF flag cleared

End of enumeration elements list.

GPDMA_C10LLR

GPDMA channel 10 linked-list address register
address_offset : 0x5CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ULL : Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxLLR update

0x1 : B_0x1

GPDMA_CxLLR update

End of enumeration elements list.

UDA : Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxDAR update

0x1 : B_0x1

GPDMA_CxDAR update

End of enumeration elements list.

USA : update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxSAR update

0x1 : B_0x1

GPDMA_CxSAR update

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)

0x1 : B_0x1

GPDMA_CxBR1 update

End of enumeration elements list.

UT2 : Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR2 update

0x1 : B_0x1

GPDMA_CxTR2 update

End of enumeration elements list.

UT1 : Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR1 update

0x1 : B_0x1

GPDMA_CxTR1 update

End of enumeration elements list.

GPDMA_C11LBAR

GPDMA channel 11 linked-list base address register
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBA : linked-list base address of GPDMA channel x
bits : 16 - 31 (16 bit)
access : read-write

GPDMA_C11FCR

GPDMA channel 11 flag clear register
address_offset : 0x5DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCF : transfer complete flag clear
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TCF flag cleared

End of enumeration elements list.

HTF : half transfer flag clear
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding HTF flag cleared

End of enumeration elements list.

DTEF : data transfer error flag clear
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding DTEF flag cleared

End of enumeration elements list.

ULEF : update link transfer error flag clear
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding ULEF flag cleared

End of enumeration elements list.

USEF : user setting error flag clear
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding USEF flag cleared

End of enumeration elements list.

SUSPF : completed suspension flag clear
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding SUSPF flag cleared

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TOF flag cleared

End of enumeration elements list.

GPDMA_C11SR

GPDMA channel 11 status register
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

channel not in idle state

0x1 : B_0x1

channel in idle state

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no transfer complete event

0x1 : B_0x1

a transfer complete event occurred

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no half transfer event

0x1 : B_0x1

an half transfer event occurred

End of enumeration elements list.

DTEF : data transfer error flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no data transfer error event

0x1 : B_0x1

a master bus error event occurred on a data transfer

End of enumeration elements list.

ULEF : update link transfer error flag
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no update link transfer error event

0x1 : B_0x1

a master bus error event occurred while updating a linked-list register from memory

End of enumeration elements list.

USEF : user setting error flag
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no user setting error event

0x1 : B_0x1

a user setting error event occurred

End of enumeration elements list.

SUSPF : completed suspension flag
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no completed suspension event

0x1 : B_0x1

a completed suspension event occurred

End of enumeration elements list.

TOF : trigger overrun flag
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no trigger overrun event

0x1 : B_0x1

a trigger overrun event occurred

End of enumeration elements list.

GPDMA_C11CR

GPDMA channel 11 control register
address_offset : 0x5E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

write: ignored, read: channel disabled

0x1 : B_0x1

write: enable channel, read: channel enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no channel reset

0x1 : B_0x1

channel reset

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

write: resume channel, read: channel not suspended

0x1 : B_0x1

write: suspend channel, read: channel suspended.

End of enumeration elements list.

TCIE : transfer complete interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

HTIE : half transfer complete interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

DTEIE : data transfer error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

ULEIE : update link transfer error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

USEIE : user setting error interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

SUSPIE : completed suspension interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

TOIE : trigger overrun interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel executed once for the current LLI

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

PRIO : priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

low priority, low weight

0x1 : B_0x1

low priority, mid weight

0x2 : B_0x2

low priority, high weight

0x3 : B_0x3

high priority

End of enumeration elements list.

GPDMA_C0SR

GPDMA channel 0 status register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

channel not in idle state

0x1 : B_0x1

channel in idle state

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no transfer complete event

0x1 : B_0x1

a transfer complete event occurred

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no half transfer event

0x1 : B_0x1

an half transfer event occurred

End of enumeration elements list.

DTEF : data transfer error flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no data transfer error event

0x1 : B_0x1

a master bus error event occurred on a data transfer

End of enumeration elements list.

ULEF : update link transfer error flag
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no update link transfer error event

0x1 : B_0x1

a master bus error event occurred while updating a linked-list register from memory

End of enumeration elements list.

USEF : user setting error flag
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no user setting error event

0x1 : B_0x1

a user setting error event occurred

End of enumeration elements list.

SUSPF : completed suspension flag
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no completed suspension event

0x1 : B_0x1

a completed suspension event occurred

End of enumeration elements list.

TOF : trigger overrun flag
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no trigger overrun event

0x1 : B_0x1

a trigger overrun event occurred

End of enumeration elements list.

GPDMA_C11TR1

GPDMA channel 11 transfer register 1
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no byte-based exchange within the unaligned half-word of each source word

0x1 : B_0x1

the two consecutive bytes within the unaligned half-word of each source word are exchanged.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

DBX : destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte:
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no byte-based exchange within half-word

0x1 : B_0x1

the two consecutive (post PAM) bytes are exchanged in each destination half-word.

End of enumeration elements list.

DHX : destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word:
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no halfword-based exchanged within word

0x1 : B_0x1

the two consecutive (post PAM) half-words are exchanged in each destination word.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

GPDMA_C11TR2

GPDMA channel 11 transfer register 2
address_offset : 0x614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWREQ : software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no software request. The selected hardware request REQSEL[6:0] is taken into account.

0x1 : B_0x1

software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)

0x1 : B_0x1

selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.

0x1 : B_0x1

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel x = 0 to 11, same as 00 channel x=12 to 15, at 2D/repeated block level, the

0x2 : B_0x2

at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.

0x3 : B_0x3

End of enumeration elements list.

TRIGPOL : trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0].
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no trigger (masked trigger event)

0x1 : B_0x1

trigger on the rising edge

0x2 : B_0x2

trigger on the falling edge

0x3 : B_0x3

same as 00

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.

0x1 : B_0x1

0x2 : B_0x2

0x3 : B_0x3

End of enumeration elements list.

GPDMA_C11BR1

GPDMA channel 11 block register 1
address_offset : 0x618 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C11SAR

GPDMA channel 11 source address register
address_offset : 0x61C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C11DAR

GPDMA channel 11 destination address register
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C0CR

GPDMA channel 0 control register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

write: ignored, read: channel disabled

0x1 : B_0x1

write: enable channel, read: channel enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no channel reset

0x1 : B_0x1

channel reset

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

write: resume channel, read: channel not suspended

0x1 : B_0x1

write: suspend channel, read: channel suspended.

End of enumeration elements list.

TCIE : transfer complete interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

HTIE : half transfer complete interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

DTEIE : data transfer error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

ULEIE : update link transfer error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

USEIE : user setting error interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

SUSPIE : completed suspension interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

TOIE : trigger overrun interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel executed once for the current LLI

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

PRIO : priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

low priority, low weight

0x1 : B_0x1

low priority, mid weight

0x2 : B_0x2

low priority, high weight

0x3 : B_0x3

high priority

End of enumeration elements list.

GPDMA_C11LLR

GPDMA channel 11 linked-list address register
address_offset : 0x64C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ULL : Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxLLR update

0x1 : B_0x1

GPDMA_CxLLR update

End of enumeration elements list.

UDA : Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxDAR update

0x1 : B_0x1

GPDMA_CxDAR update

End of enumeration elements list.

USA : update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxSAR update

0x1 : B_0x1

GPDMA_CxSAR update

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)

0x1 : B_0x1

GPDMA_CxBR1 update

End of enumeration elements list.

UT2 : Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR2 update

0x1 : B_0x1

GPDMA_CxTR2 update

End of enumeration elements list.

UT1 : Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR1 update

0x1 : B_0x1

GPDMA_CxTR1 update

End of enumeration elements list.

GPDMA_C12LBAR

GPDMA channel 12 linked-list base address register
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBA : linked-list base address of GPDMA channel x
bits : 16 - 31 (16 bit)
access : read-write

GPDMA_C12FCR

GPDMA channel 12 flag clear register
address_offset : 0x65C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCF : transfer complete flag clear
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TCF flag cleared

End of enumeration elements list.

HTF : half transfer flag clear
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding HTF flag cleared

End of enumeration elements list.

DTEF : data transfer error flag clear
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding DTEF flag cleared

End of enumeration elements list.

ULEF : update link transfer error flag clear
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding ULEF flag cleared

End of enumeration elements list.

USEF : user setting error flag clear
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding USEF flag cleared

End of enumeration elements list.

SUSPF : completed suspension flag clear
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding SUSPF flag cleared

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TOF flag cleared

End of enumeration elements list.

GPDMA_C12SR

GPDMA channel 12 status register
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

channel not in idle state

0x1 : B_0x1

channel in idle state

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no transfer complete event

0x1 : B_0x1

a transfer complete event occurred

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no half transfer event

0x1 : B_0x1

an half transfer event occurred

End of enumeration elements list.

DTEF : data transfer error flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no data transfer error event

0x1 : B_0x1

a master bus error event occurred on a data transfer

End of enumeration elements list.

ULEF : update link transfer error flag
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no update link transfer error event

0x1 : B_0x1

a master bus error event occurred while updating a linked-list register from memory

End of enumeration elements list.

USEF : user setting error flag
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no user setting error event

0x1 : B_0x1

a user setting error event occurred

End of enumeration elements list.

SUSPF : completed suspension flag
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no completed suspension event

0x1 : B_0x1

a completed suspension event occurred

End of enumeration elements list.

TOF : trigger overrun flag
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no trigger overrun event

0x1 : B_0x1

a trigger overrun event occurred

End of enumeration elements list.

GPDMA_C12CR

GPDMA channel 12 control register
address_offset : 0x664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

write: ignored, read: channel disabled

0x1 : B_0x1

write: enable channel, read: channel enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no channel reset

0x1 : B_0x1

channel reset

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

write: resume channel, read: channel not suspended

0x1 : B_0x1

write: suspend channel, read: channel suspended.

End of enumeration elements list.

TCIE : transfer complete interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

HTIE : half transfer complete interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

DTEIE : data transfer error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

ULEIE : update link transfer error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

USEIE : user setting error interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

SUSPIE : completed suspension interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

TOIE : trigger overrun interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel executed once for the current LLI

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

PRIO : priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

low priority, low weight

0x1 : B_0x1

low priority, mid weight

0x2 : B_0x2

low priority, high weight

0x3 : B_0x3

high priority

End of enumeration elements list.

GPDMA_C12TR1

GPDMA channel 12 transfer register 1
address_offset : 0x690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no byte-based exchange within the unaligned half-word of each source word

0x1 : B_0x1

the two consecutive bytes within the unaligned half-word of each source word are exchanged.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

DBX : destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte:
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no byte-based exchange within half-word

0x1 : B_0x1

the two consecutive (post PAM) bytes are exchanged in each destination half-word.

End of enumeration elements list.

DHX : destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word:
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no halfword-based exchanged within word

0x1 : B_0x1

the two consecutive (post PAM) half-words are exchanged in each destination word.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

GPDMA_C12TR2

GPDMA channel 12 transfer register 2
address_offset : 0x694 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWREQ : software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no software request. The selected hardware request REQSEL[6:0] is taken into account.

0x1 : B_0x1

software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)

0x1 : B_0x1

selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.

0x1 : B_0x1

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel x = 0 to 11, same as 00 channel x=12 to 15, at 2D/repeated block level, the

0x2 : B_0x2

at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.

0x3 : B_0x3

End of enumeration elements list.

TRIGPOL : trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0].
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no trigger (masked trigger event)

0x1 : B_0x1

trigger on the rising edge

0x2 : B_0x2

trigger on the falling edge

0x3 : B_0x3

same as 00

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.

0x1 : B_0x1

0x2 : B_0x2

0x3 : B_0x3

End of enumeration elements list.

GPDMA_C12BR1

GPDMA channel 12 alternate block register 1
address_offset : 0x698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BNDT : block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if GPDMA_CxLLR.UB1 = 1, this field is updated by the LLI in the memory. - if GPDMA_CxLLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all GPDMA_CxLLR.Uxx = 0 and if GPDMA_CxLLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if GPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (GPDMA_CxTR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued.
bits : 0 - 15 (16 bit)
access : read-write

BRC : Block repeat counter This field contains the number of repetitions of the current block (0 to 2047). When the channel is enabled, this field becomes read-only. After decrements, this field indicates the remaining number of blocks, excluding the current one. This counter is hardware decremented for each completed block transfer. Once the last block transfer is completed (BRC[10:0] = BNDT[15:0] = 0): If GPDMA_CxLLR.UB1 = 1, all GPDMA_CxBR1 fields are updated by the next LLI in the memory. If GPDMA_CxLLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. if all GPDMA_CxLLR.Uxx = 0 and if GPDMA_CxLLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). if GPDMA_CxLLR = 0, this field is kept as zero following the last LLI and data transfer.
bits : 16 - 26 (11 bit)
access : read-write

SDEC : source address decrement
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxTR3.SAO to the current GPDMA_CxSAR value (current source address)

0x1 : B_0x1

At the end of a programmed burst transfer from the source, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxTR3.SAO to the current GPDMA_CxSAR value (current source address)

End of enumeration elements list.

DDEC : destination address decrement
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxTR3.DAO to the current GPDMA_CxDAR value (current destination address)

0x1 : B_0x1

At the end of a programmed burst transfer to the destination, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxTR3.DAO to the current GPDMA_CxDAR value (current destination address)

End of enumeration elements list.

BRSDEC : Block repeat source address decrement Note: On top of this increment/decrement (depending on BRSDEC), GPDMA_CxSAR is in the same time also updated by the increment/decrement (depending on SDEC) of the GPDMA_CxTR3.SAO value, as it is done after any programmed burst transfer.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

at the end of a block transfer, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxBR2.BRSAO to the current GPDMA_CxSAR value (current source address)

0x1 : B_0x1

at the end of a block transfer, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRSAO from the current GPDMA_CxSAR value (current source address)

End of enumeration elements list.

BRDDEC : Block repeat destination address decrement Note: On top of this increment/decrement (depending on BRDDEC), GPDMA_CxDAR is in the same time also updated by the increment/decrement (depending on DDEC) of the GPDMA_CxTR3.DAO value, as it is usually done at the end of each programmed burst transfer.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

at the end of a block transfer, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxBR2.BRDAO to the current GPDMA_CxDAR value (current destination address)

0x1 : B_0x1

at the end of a block transfer, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRDAO from the current GPDMA_CxDAR value (current destination address)

End of enumeration elements list.

GPDMA_C12SAR

GPDMA channel 12 source address register
address_offset : 0x69C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C12DAR

GPDMA channel 12 destination address register
address_offset : 0x6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C12TR3

GPDMA channel 12 transfer register 3
address_offset : 0x6A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAO : source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (GPDMA_CxTR1.SINC = 1). Note: A source address offset must be aligned with the programmed data width of a source burst (SAO[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied.
bits : 0 - 12 (13 bit)
access : read-write

DAO : destination address offset increment The destination address, pointed by GPDMA_CxDAR, is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (GPDMA_CxTR1.DINC = 1). Note: A destination address offset must be aligned with the programmed data width of a destination burst (DAO[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued.
bits : 16 - 28 (13 bit)
access : read-write

GPDMA_C12BR2

GPDMA channel 12 block register 2
address_offset : 0x6A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRSAO : Block repeated source address offset For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (GPDMA_CxSAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (BRSAO[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued.
bits : 0 - 15 (16 bit)
access : read-write

BRDAO : Block repeated destination address offset For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (GPDMA_CxDAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (BRDAO[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued.
bits : 16 - 31 (16 bit)
access : read-write

GPDMA_C12LLR

GPDMA channel 12 alternate linked-list address register
address_offset : 0x6CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ULL : Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxLLR update

0x1 : B_0x1

GPDMA_CxLLR update

End of enumeration elements list.

UB2 : Update GPDMA_CxBR2 from memory This bit controls the update of GPDMA_CxBR2 from the memory during the link transfer.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxBR2 update

0x1 : B_0x1

GPDMA_CxBR2 update

End of enumeration elements list.

UT3 : Update GPDMA_CxTR3 from memory This bit controls the update of GPDMA_CxTR3 from the memory during the link transfer.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR3 update

0x1 : B_0x1

GPDMA_CxTR3 update

End of enumeration elements list.

UDA : Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxDAR update

0x1 : B_0x1

GPDMA_CxDAR update

End of enumeration elements list.

USA : update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxSAR update

0x1 : B_0x1

GPDMA_CxSAR update

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)

0x1 : B_0x1

GPDMA_CxBR1 update

End of enumeration elements list.

UT2 : Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR2 update

0x1 : B_0x1

GPDMA_CxTR2 update

End of enumeration elements list.

UT1 : Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR1 update

0x1 : B_0x1

GPDMA_CxTR1 update

End of enumeration elements list.

GPDMA_C13LBAR

GPDMA channel 13 linked-list base address register
address_offset : 0x6D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBA : linked-list base address of GPDMA channel x
bits : 16 - 31 (16 bit)
access : read-write

GPDMA_C13FCR

GPDMA channel 13 flag clear register
address_offset : 0x6DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCF : transfer complete flag clear
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TCF flag cleared

End of enumeration elements list.

HTF : half transfer flag clear
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding HTF flag cleared

End of enumeration elements list.

DTEF : data transfer error flag clear
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding DTEF flag cleared

End of enumeration elements list.

ULEF : update link transfer error flag clear
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding ULEF flag cleared

End of enumeration elements list.

USEF : user setting error flag clear
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding USEF flag cleared

End of enumeration elements list.

SUSPF : completed suspension flag clear
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding SUSPF flag cleared

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TOF flag cleared

End of enumeration elements list.

GPDMA_C13SR

GPDMA channel 13 status register
address_offset : 0x6E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

channel not in idle state

0x1 : B_0x1

channel in idle state

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no transfer complete event

0x1 : B_0x1

a transfer complete event occurred

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no half transfer event

0x1 : B_0x1

an half transfer event occurred

End of enumeration elements list.

DTEF : data transfer error flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no data transfer error event

0x1 : B_0x1

a master bus error event occurred on a data transfer

End of enumeration elements list.

ULEF : update link transfer error flag
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no update link transfer error event

0x1 : B_0x1

a master bus error event occurred while updating a linked-list register from memory

End of enumeration elements list.

USEF : user setting error flag
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no user setting error event

0x1 : B_0x1

a user setting error event occurred

End of enumeration elements list.

SUSPF : completed suspension flag
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no completed suspension event

0x1 : B_0x1

a completed suspension event occurred

End of enumeration elements list.

TOF : trigger overrun flag
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no trigger overrun event

0x1 : B_0x1

a trigger overrun event occurred

End of enumeration elements list.

GPDMA_C13CR

GPDMA channel 13 control register
address_offset : 0x6E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

write: ignored, read: channel disabled

0x1 : B_0x1

write: enable channel, read: channel enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no channel reset

0x1 : B_0x1

channel reset

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

write: resume channel, read: channel not suspended

0x1 : B_0x1

write: suspend channel, read: channel suspended.

End of enumeration elements list.

TCIE : transfer complete interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

HTIE : half transfer complete interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

DTEIE : data transfer error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

ULEIE : update link transfer error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

USEIE : user setting error interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

SUSPIE : completed suspension interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

TOIE : trigger overrun interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel executed once for the current LLI

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

PRIO : priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

low priority, low weight

0x1 : B_0x1

low priority, mid weight

0x2 : B_0x2

low priority, high weight

0x3 : B_0x3

high priority

End of enumeration elements list.

GPDMA_C13TR1

GPDMA channel 13 transfer register 1
address_offset : 0x710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no byte-based exchange within the unaligned half-word of each source word

0x1 : B_0x1

the two consecutive bytes within the unaligned half-word of each source word are exchanged.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

DBX : destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte:
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no byte-based exchange within half-word

0x1 : B_0x1

the two consecutive (post PAM) bytes are exchanged in each destination half-word.

End of enumeration elements list.

DHX : destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word:
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no halfword-based exchanged within word

0x1 : B_0x1

the two consecutive (post PAM) half-words are exchanged in each destination word.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

GPDMA_C13TR2

GPDMA channel 13 transfer register 2
address_offset : 0x714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWREQ : software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no software request. The selected hardware request REQSEL[6:0] is taken into account.

0x1 : B_0x1

software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)

0x1 : B_0x1

selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.

0x1 : B_0x1

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel x = 0 to 11, same as 00 channel x=12 to 15, at 2D/repeated block level, the

0x2 : B_0x2

at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.

0x3 : B_0x3

End of enumeration elements list.

TRIGPOL : trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0].
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no trigger (masked trigger event)

0x1 : B_0x1

trigger on the rising edge

0x2 : B_0x2

trigger on the falling edge

0x3 : B_0x3

same as 00

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.

0x1 : B_0x1

0x2 : B_0x2

0x3 : B_0x3

End of enumeration elements list.

GPDMA_C13BR1

GPDMA channel 13 alternate block register 1
address_offset : 0x718 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BNDT : block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if GPDMA_CxLLR.UB1 = 1, this field is updated by the LLI in the memory. - if GPDMA_CxLLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all GPDMA_CxLLR.Uxx = 0 and if GPDMA_CxLLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if GPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (GPDMA_CxTR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued.
bits : 0 - 15 (16 bit)
access : read-write

SDEC : source address decrement
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

End of enumeration elements list.

DDEC : destination address decrement
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at the end of a block transfer, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxBR2.BRSAO to the current GPDMA_CxSAR value (current source address)

0x1 : B_0x1

at the end of a block transfer, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRSAO from the current GPDMA_CxSAR value (current source address)

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at the end of a block transfer, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxBR2.BRDAO to the current GPDMA_CxDAR value (current destination address)

0x1 : B_0x1

at the end of a block transfer, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRDAO from the current GPDMA_CxDAR value (current destination address)

End of enumeration elements list.

GPDMA_C13SAR

GPDMA channel 13 source address register
address_offset : 0x71C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C13DAR

GPDMA channel 13 destination address register
address_offset : 0x720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C13TR3

GPDMA channel 13 transfer register 3
address_offset : 0x724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C13BR2

GPDMA channel 13 block register 2
address_offset : 0x728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C13LLR

GPDMA channel 13 alternate linked-list address register
address_offset : 0x74C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ULL : Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxLLR update

0x1 : B_0x1

GPDMA_CxLLR update

End of enumeration elements list.

UB2 : Update GPDMA_CxBR2 from memory This bit controls the update of GPDMA_CxBR2 from the memory during the link transfer.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxBR2 update

0x1 : B_0x1

GPDMA_CxBR2 update

End of enumeration elements list.

UT3 : Update GPDMA_CxTR3 from memory This bit controls the update of GPDMA_CxTR3 from the memory during the link transfer.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR3 update

0x1 : B_0x1

GPDMA_CxTR3 update

End of enumeration elements list.

UDA : Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxDAR update

0x1 : B_0x1

GPDMA_CxDAR update

End of enumeration elements list.

USA : update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxSAR update

0x1 : B_0x1

GPDMA_CxSAR update

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)

0x1 : B_0x1

GPDMA_CxBR1 update

End of enumeration elements list.

UT2 : Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR2 update

0x1 : B_0x1

GPDMA_CxTR2 update

End of enumeration elements list.

UT1 : Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR1 update

0x1 : B_0x1

GPDMA_CxTR1 update

End of enumeration elements list.

GPDMA_C14LBAR

GPDMA channel 14 linked-list base address register
address_offset : 0x750 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBA : linked-list base address of GPDMA channel x
bits : 16 - 31 (16 bit)
access : read-write

GPDMA_C14FCR

GPDMA channel 14 flag clear register
address_offset : 0x75C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCF : transfer complete flag clear
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TCF flag cleared

End of enumeration elements list.

HTF : half transfer flag clear
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding HTF flag cleared

End of enumeration elements list.

DTEF : data transfer error flag clear
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding DTEF flag cleared

End of enumeration elements list.

ULEF : update link transfer error flag clear
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding ULEF flag cleared

End of enumeration elements list.

USEF : user setting error flag clear
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding USEF flag cleared

End of enumeration elements list.

SUSPF : completed suspension flag clear
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding SUSPF flag cleared

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TOF flag cleared

End of enumeration elements list.

GPDMA_C14SR

GPDMA channel 14 status register
address_offset : 0x760 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

channel not in idle state

0x1 : B_0x1

channel in idle state

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no transfer complete event

0x1 : B_0x1

a transfer complete event occurred

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no half transfer event

0x1 : B_0x1

an half transfer event occurred

End of enumeration elements list.

DTEF : data transfer error flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no data transfer error event

0x1 : B_0x1

a master bus error event occurred on a data transfer

End of enumeration elements list.

ULEF : update link transfer error flag
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no update link transfer error event

0x1 : B_0x1

a master bus error event occurred while updating a linked-list register from memory

End of enumeration elements list.

USEF : user setting error flag
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no user setting error event

0x1 : B_0x1

a user setting error event occurred

End of enumeration elements list.

SUSPF : completed suspension flag
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no completed suspension event

0x1 : B_0x1

a completed suspension event occurred

End of enumeration elements list.

TOF : trigger overrun flag
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no trigger overrun event

0x1 : B_0x1

a trigger overrun event occurred

End of enumeration elements list.

GPDMA_C14CR

GPDMA channel 14 control register
address_offset : 0x764 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

write: ignored, read: channel disabled

0x1 : B_0x1

write: enable channel, read: channel enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no channel reset

0x1 : B_0x1

channel reset

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

write: resume channel, read: channel not suspended

0x1 : B_0x1

write: suspend channel, read: channel suspended.

End of enumeration elements list.

TCIE : transfer complete interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

HTIE : half transfer complete interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

DTEIE : data transfer error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

ULEIE : update link transfer error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

USEIE : user setting error interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

SUSPIE : completed suspension interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

TOIE : trigger overrun interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel executed once for the current LLI

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

PRIO : priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

low priority, low weight

0x1 : B_0x1

low priority, mid weight

0x2 : B_0x2

low priority, high weight

0x3 : B_0x3

high priority

End of enumeration elements list.

GPDMA_C14TR1

GPDMA channel 14 transfer register 1
address_offset : 0x790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no byte-based exchange within the unaligned half-word of each source word

0x1 : B_0x1

the two consecutive bytes within the unaligned half-word of each source word are exchanged.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

DBX : destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte:
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no byte-based exchange within half-word

0x1 : B_0x1

the two consecutive (post PAM) bytes are exchanged in each destination half-word.

End of enumeration elements list.

DHX : destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word:
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no halfword-based exchanged within word

0x1 : B_0x1

the two consecutive (post PAM) half-words are exchanged in each destination word.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

GPDMA_C14TR2

GPDMA channel 14 transfer register 2
address_offset : 0x794 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWREQ : software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no software request. The selected hardware request REQSEL[6:0] is taken into account.

0x1 : B_0x1

software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)

0x1 : B_0x1

selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.

0x1 : B_0x1

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel x = 0 to 11, same as 00 channel x=12 to 15, at 2D/repeated block level, the

0x2 : B_0x2

at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.

0x3 : B_0x3

End of enumeration elements list.

TRIGPOL : trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0].
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no trigger (masked trigger event)

0x1 : B_0x1

trigger on the rising edge

0x2 : B_0x2

trigger on the falling edge

0x3 : B_0x3

same as 00

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.

0x1 : B_0x1

0x2 : B_0x2

0x3 : B_0x3

End of enumeration elements list.

GPDMA_C14BR1

GPDMA channel 14 alternate block register 1
address_offset : 0x798 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BNDT : block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if GPDMA_CxLLR.UB1 = 1, this field is updated by the LLI in the memory. - if GPDMA_CxLLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all GPDMA_CxLLR.Uxx = 0 and if GPDMA_CxLLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if GPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (GPDMA_CxTR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued.
bits : 0 - 15 (16 bit)
access : read-write

SDEC : source address decrement
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

End of enumeration elements list.

DDEC : destination address decrement
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at the end of a block transfer, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxBR2.BRSAO to the current GPDMA_CxSAR value (current source address)

0x1 : B_0x1

at the end of a block transfer, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRSAO from the current GPDMA_CxSAR value (current source address)

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at the end of a block transfer, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxBR2.BRDAO to the current GPDMA_CxDAR value (current destination address)

0x1 : B_0x1

at the end of a block transfer, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRDAO from the current GPDMA_CxDAR value (current destination address)

End of enumeration elements list.

GPDMA_C14SAR

GPDMA channel 14 source address register
address_offset : 0x79C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C14DAR

GPDMA channel 14 destination address register
address_offset : 0x7A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C14TR3

GPDMA channel 14 transfer register 3
address_offset : 0x7A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C14BR2

GPDMA channel 14 block register 2
address_offset : 0x7A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C14LLR

GPDMA channel 14 alternate linked-list address register
address_offset : 0x7CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ULL : Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxLLR update

0x1 : B_0x1

GPDMA_CxLLR update

End of enumeration elements list.

UB2 : Update GPDMA_CxBR2 from memory This bit controls the update of GPDMA_CxBR2 from the memory during the link transfer.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxBR2 update

0x1 : B_0x1

GPDMA_CxBR2 update

End of enumeration elements list.

UT3 : Update GPDMA_CxTR3 from memory This bit controls the update of GPDMA_CxTR3 from the memory during the link transfer.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR3 update

0x1 : B_0x1

GPDMA_CxTR3 update

End of enumeration elements list.

UDA : Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxDAR update

0x1 : B_0x1

GPDMA_CxDAR update

End of enumeration elements list.

USA : update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxSAR update

0x1 : B_0x1

GPDMA_CxSAR update

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)

0x1 : B_0x1

GPDMA_CxBR1 update

End of enumeration elements list.

UT2 : Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR2 update

0x1 : B_0x1

GPDMA_CxTR2 update

End of enumeration elements list.

UT1 : Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR1 update

0x1 : B_0x1

GPDMA_CxTR1 update

End of enumeration elements list.

GPDMA_C15LBAR

GPDMA channel 15 linked-list base address register
address_offset : 0x7D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBA : linked-list base address of GPDMA channel x
bits : 16 - 31 (16 bit)
access : read-write

GPDMA_C15FCR

GPDMA channel 15 flag clear register
address_offset : 0x7DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCF : transfer complete flag clear
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TCF flag cleared

End of enumeration elements list.

HTF : half transfer flag clear
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding HTF flag cleared

End of enumeration elements list.

DTEF : data transfer error flag clear
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding DTEF flag cleared

End of enumeration elements list.

ULEF : update link transfer error flag clear
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding ULEF flag cleared

End of enumeration elements list.

USEF : user setting error flag clear
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding USEF flag cleared

End of enumeration elements list.

SUSPF : completed suspension flag clear
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding SUSPF flag cleared

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TOF flag cleared

End of enumeration elements list.

GPDMA_C15SR

GPDMA channel 15 status register
address_offset : 0x7E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

channel not in idle state

0x1 : B_0x1

channel in idle state

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no transfer complete event

0x1 : B_0x1

a transfer complete event occurred

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no half transfer event

0x1 : B_0x1

an half transfer event occurred

End of enumeration elements list.

DTEF : data transfer error flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no data transfer error event

0x1 : B_0x1

a master bus error event occurred on a data transfer

End of enumeration elements list.

ULEF : update link transfer error flag
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no update link transfer error event

0x1 : B_0x1

a master bus error event occurred while updating a linked-list register from memory

End of enumeration elements list.

USEF : user setting error flag
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no user setting error event

0x1 : B_0x1

a user setting error event occurred

End of enumeration elements list.

SUSPF : completed suspension flag
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no completed suspension event

0x1 : B_0x1

a completed suspension event occurred

End of enumeration elements list.

TOF : trigger overrun flag
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no trigger overrun event

0x1 : B_0x1

a trigger overrun event occurred

End of enumeration elements list.

GPDMA_C15CR

GPDMA channel 15 control register
address_offset : 0x7E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

write: ignored, read: channel disabled

0x1 : B_0x1

write: enable channel, read: channel enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no channel reset

0x1 : B_0x1

channel reset

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

write: resume channel, read: channel not suspended

0x1 : B_0x1

write: suspend channel, read: channel suspended.

End of enumeration elements list.

TCIE : transfer complete interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

HTIE : half transfer complete interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

DTEIE : data transfer error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

ULEIE : update link transfer error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

USEIE : user setting error interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

SUSPIE : completed suspension interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

TOIE : trigger overrun interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel executed once for the current LLI

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

PRIO : priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

low priority, low weight

0x1 : B_0x1

low priority, mid weight

0x2 : B_0x2

low priority, high weight

0x3 : B_0x3

high priority

End of enumeration elements list.

GPDMA_RCFGLOCKR

GPDMA configuration lock register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCK0 : LOCK0
bits : 0 - 0 (1 bit)
access : read-write

LOCK1 : LOCK1
bits : 1 - 1 (1 bit)
access : read-write

LOCK2 : LOCK2
bits : 2 - 2 (1 bit)
access : read-write

LOCK3 : LOCK3
bits : 3 - 3 (1 bit)
access : read-write

LOCK4 : LOCK4
bits : 4 - 4 (1 bit)
access : read-write

LOCK5 : LOCK5
bits : 5 - 5 (1 bit)
access : read-write

LOCK6 : LOCK6
bits : 6 - 6 (1 bit)
access : read-write

LOCK7 : LOCK7
bits : 7 - 7 (1 bit)
access : read-write

LOCK8 : LOCK8
bits : 8 - 8 (1 bit)
access : read-write

LOCK9 : LOCK9
bits : 9 - 9 (1 bit)
access : read-write

LOCK10 : LOCK10
bits : 10 - 10 (1 bit)
access : read-write

LOCK11 : LOCK11
bits : 11 - 11 (1 bit)
access : read-write

LOCK12 : LOCK12
bits : 12 - 12 (1 bit)
access : read-write

LOCK13 : LOCK13
bits : 13 - 13 (1 bit)
access : read-write

LOCK14 : LOCK14
bits : 14 - 14 (1 bit)
access : read-write

LOCK15 : LOCK15
bits : 15 - 15 (1 bit)
access : read-write

GPDMA_C15TR1

GPDMA channel 15 transfer register 1
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no byte-based exchange within the unaligned half-word of each source word

0x1 : B_0x1

the two consecutive bytes within the unaligned half-word of each source word are exchanged.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

DBX : destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte:
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no byte-based exchange within half-word

0x1 : B_0x1

the two consecutive (post PAM) bytes are exchanged in each destination half-word.

End of enumeration elements list.

DHX : destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word:
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no halfword-based exchanged within word

0x1 : B_0x1

the two consecutive (post PAM) half-words are exchanged in each destination word.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

GPDMA_C15TR2

GPDMA channel 15 transfer register 2
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWREQ : software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no software request. The selected hardware request REQSEL[6:0] is taken into account.

0x1 : B_0x1

software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)

0x1 : B_0x1

selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.

0x1 : B_0x1

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel x = 0 to 11, same as 00 channel x=12 to 15, at 2D/repeated block level, the

0x2 : B_0x2

at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.

0x3 : B_0x3

End of enumeration elements list.

TRIGPOL : trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0].
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no trigger (masked trigger event)

0x1 : B_0x1

trigger on the rising edge

0x2 : B_0x2

trigger on the falling edge

0x3 : B_0x3

same as 00

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.

0x1 : B_0x1

0x2 : B_0x2

0x3 : B_0x3

End of enumeration elements list.

GPDMA_C15BR1

GPDMA channel 15 alternate block register 1
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BNDT : block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if GPDMA_CxLLR.UB1 = 1, this field is updated by the LLI in the memory. - if GPDMA_CxLLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all GPDMA_CxLLR.Uxx = 0 and if GPDMA_CxLLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if GPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (GPDMA_CxTR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued.
bits : 0 - 15 (16 bit)
access : read-write

SDEC : source address decrement
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

End of enumeration elements list.

DDEC : destination address decrement
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at the end of a block transfer, the GPDMA_CxSAR register is updated by adding the programmed offset GPDMA_CxBR2.BRSAO to the current GPDMA_CxSAR value (current source address)

0x1 : B_0x1

at the end of a block transfer, the GPDMA_CxSAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRSAO from the current GPDMA_CxSAR value (current source address)

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at the end of a block transfer, the GPDMA_CxDAR register is updated by adding the programmed offset GPDMA_CxBR2.BRDAO to the current GPDMA_CxDAR value (current destination address)

0x1 : B_0x1

at the end of a block transfer, the GPDMA_CxDAR register is updated by subtracting the programmed offset GPDMA_CxBR2.BRDAO from the current GPDMA_CxDAR value (current destination address)

End of enumeration elements list.

GPDMA_C15SAR

GPDMA channel 15 source address register
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C15DAR

GPDMA channel 15 destination address register
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C15TR3

GPDMA channel 15 transfer register 3
address_offset : 0x824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C15BR2

GPDMA channel 15 block register 2
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C15LLR

GPDMA channel 15 alternate linked-list address register
address_offset : 0x84C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ULL : Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxLLR update

0x1 : B_0x1

GPDMA_CxLLR update

End of enumeration elements list.

UB2 : Update GPDMA_CxBR2 from memory This bit controls the update of GPDMA_CxBR2 from the memory during the link transfer.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxBR2 update

0x1 : B_0x1

GPDMA_CxBR2 update

End of enumeration elements list.

UT3 : Update GPDMA_CxTR3 from memory This bit controls the update of GPDMA_CxTR3 from the memory during the link transfer.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR3 update

0x1 : B_0x1

GPDMA_CxTR3 update

End of enumeration elements list.

UDA : Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxDAR update

0x1 : B_0x1

GPDMA_CxDAR update

End of enumeration elements list.

USA : update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxSAR update

0x1 : B_0x1

GPDMA_CxSAR update

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)

0x1 : B_0x1

GPDMA_CxBR1 update

End of enumeration elements list.

UT2 : Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR2 update

0x1 : B_0x1

GPDMA_CxTR2 update

End of enumeration elements list.

UT1 : Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR1 update

0x1 : B_0x1

GPDMA_CxTR1 update

End of enumeration elements list.

GPDMA_C0TR1

GPDMA channel 0 transfer register 1
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

0x0 : B_0x0

source data is transferred as right aligned, left-truncated down to the destination data width

0x1 : B_0x1

source data is transferred as left-aligned, right-truncated down to the destination data width

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no byte-based exchange within the unaligned half-word of each source word

0x1 : B_0x1

the two consecutive bytes within the unaligned half-word of each source word are exchanged.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

byte

0x1 : B_0x1

half-word (2 bytes)

0x2 : B_0x2

word (4 bytes)

0x3 : B_0x3

user setting error reported and no transfer issued

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

fixed burst

0x1 : B_0x1

contiguously incremented burst

End of enumeration elements list.

DBX : destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte:
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no byte-based exchange within half-word

0x1 : B_0x1

the two consecutive (post PAM) bytes are exchanged in each destination half-word.

End of enumeration elements list.

DHX : destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word:
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no halfword-based exchanged within word

0x1 : B_0x1

the two consecutive (post PAM) half-words are exchanged in each destination word.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

GPDMA transfer non-secure

0x1 : B_0x1

GPDMA transfer secure

End of enumeration elements list.

GPDMA_C0TR2

GPDMA channel 0 transfer register 2
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWREQ : software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no software request. The selected hardware request REQSEL[6:0] is taken into account.

0x1 : B_0x1

software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored.

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)

0x1 : B_0x1

selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.

0x1 : B_0x1

the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel x = 0 to 11, same as 00 channel x=12 to 15, at 2D/repeated block level, the

0x2 : B_0x2

at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.

0x3 : B_0x3

End of enumeration elements list.

TRIGPOL : trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0].
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no trigger (masked trigger event)

0x1 : B_0x1

trigger on the rising edge

0x2 : B_0x2

trigger on the falling edge

0x3 : B_0x3

same as 00

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.

0x1 : B_0x1

0x2 : B_0x2

0x3 : B_0x3

End of enumeration elements list.

GPDMA_C0BR1

GPDMA channel 0 block register 1
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C0SAR

GPDMA channel 0 source address register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_C0DAR

GPDMA channel 0 destination address register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPDMA_MISR

GPDMA non-secure masked interrupt status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIS0 : MIS0
bits : 0 - 0 (1 bit)
access : read-only

MIS1 : MIS1
bits : 1 - 1 (1 bit)
access : read-only

MIS2 : MIS2
bits : 2 - 2 (1 bit)
access : read-only

MIS3 : MIS3
bits : 3 - 3 (1 bit)
access : read-only

MIS4 : MIS4
bits : 4 - 4 (1 bit)
access : read-only

MIS5 : MIS5
bits : 5 - 5 (1 bit)
access : read-only

MIS6 : MIS6
bits : 6 - 6 (1 bit)
access : read-only

MIS7 : MIS7
bits : 7 - 7 (1 bit)
access : read-only

MIS8 : MIS8
bits : 8 - 8 (1 bit)
access : read-only

MIS9 : MIS9
bits : 9 - 9 (1 bit)
access : read-only

MIS10 : MIS10
bits : 10 - 10 (1 bit)
access : read-only

MIS11 : MIS11
bits : 11 - 11 (1 bit)
access : read-only

MIS12 : MIS12
bits : 12 - 12 (1 bit)
access : read-only

MIS13 : MIS13
bits : 13 - 13 (1 bit)
access : read-only

MIS14 : MIS14
bits : 14 - 14 (1 bit)
access : read-only

MIS15 : MIS15
bits : 15 - 15 (1 bit)
access : read-only

GPDMA_C0LLR

GPDMA channel 0 linked-list address register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ULL : Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxLLR update

0x1 : B_0x1

GPDMA_CxLLR update

End of enumeration elements list.

UDA : Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxDAR update

0x1 : B_0x1

GPDMA_CxDAR update

End of enumeration elements list.

USA : update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxSAR update

0x1 : B_0x1

GPDMA_CxSAR update

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)

0x1 : B_0x1

GPDMA_CxBR1 update

End of enumeration elements list.

UT2 : Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR2 update

0x1 : B_0x1

GPDMA_CxTR2 update

End of enumeration elements list.

UT1 : Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

no GPDMA_CxTR1 update

0x1 : B_0x1

GPDMA_CxTR1 update

End of enumeration elements list.

GPDMA_C1LBAR

GPDMA channel 1 linked-list base address register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBA : linked-list base address of GPDMA channel x
bits : 16 - 31 (16 bit)
access : read-write

GPDMA_C1FCR

GPDMA channel 1 flag clear register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCF : transfer complete flag clear
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TCF flag cleared

End of enumeration elements list.

HTF : half transfer flag clear
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding HTF flag cleared

End of enumeration elements list.

DTEF : data transfer error flag clear
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding DTEF flag cleared

End of enumeration elements list.

ULEF : update link transfer error flag clear
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding ULEF flag cleared

End of enumeration elements list.

USEF : user setting error flag clear
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding USEF flag cleared

End of enumeration elements list.

SUSPF : completed suspension flag clear
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding SUSPF flag cleared

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

0x0 : B_0x0

no effect

0x1 : B_0x1

corresponding TOF flag cleared

End of enumeration elements list.

GPDMA_C1SR

GPDMA channel 1 status register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

channel not in idle state

0x1 : B_0x1

channel in idle state

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no transfer complete event

0x1 : B_0x1

a transfer complete event occurred

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no half transfer event

0x1 : B_0x1

an half transfer event occurred

End of enumeration elements list.

DTEF : data transfer error flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no data transfer error event

0x1 : B_0x1

a master bus error event occurred on a data transfer

End of enumeration elements list.

ULEF : update link transfer error flag
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no update link transfer error event

0x1 : B_0x1

a master bus error event occurred while updating a linked-list register from memory

End of enumeration elements list.

USEF : user setting error flag
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no user setting error event

0x1 : B_0x1

a user setting error event occurred

End of enumeration elements list.

SUSPF : completed suspension flag
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no completed suspension event

0x1 : B_0x1

a completed suspension event occurred

End of enumeration elements list.

TOF : trigger overrun flag
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

no trigger overrun event

0x1 : B_0x1

a trigger overrun event occurred

End of enumeration elements list.

GPDMA_C1CR

GPDMA channel 1 control register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Enumeration:

0x0 : B_0x0

write: ignored, read: channel disabled

0x1 : B_0x1

write: enable channel, read: channel enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

no channel reset

0x1 : B_0x1

channel reset

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

write: resume channel, read: channel not suspended

0x1 : B_0x1

write: suspend channel, read: channel suspended.

End of enumeration elements list.

TCIE : transfer complete interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

HTIE : half transfer complete interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

DTEIE : data transfer error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

ULEIE : update link transfer error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

USEIE : user setting error interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

SUSPIE : completed suspension interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

TOIE : trigger overrun interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

interrupt disabled

0x1 : B_0x1

interrupt enabled

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

0x1 : B_0x1

channel executed once for the current LLI

End of enumeration elements list.

Enumeration:

0x0 : B_0x0

port 0 (AHB) allocated

0x1 : B_0x1

port 1 (AHB) allocated

End of enumeration elements list.

PRIO : priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0x0 : B_0x0

low priority, low weight

0x1 : B_0x1

low priority, mid weight

0x2 : B_0x2

low priority, high weight

0x3 : B_0x3

high priority

End of enumeration elements list.

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GPDMA

Peripheral Memory Blocks

Registers

GPDMA_SECCFGR

GPDMA_SMISR

GPDMA_C1TR1

GPDMA_C1TR2

GPDMA_C1BR1

GPDMA_C1SAR

GPDMA_C1DAR

GPDMA_C1LLR

GPDMA_C2LBAR

GPDMA_C2FCR

GPDMA_C2SR

GPDMA_C2CR

GPDMA_C2TR1

GPDMA_C2TR2

GPDMA_C2BR1

GPDMA_C2SAR

GPDMA_C2DAR

GPDMA_C2LLR

GPDMA_C3LBAR

GPDMA_C3FCR

GPDMA_C3SR

GPDMA_C3CR

GPDMA_C3TR1

GPDMA_C3TR2

GPDMA_C3BR1

GPDMA_C3SAR

GPDMA_C3DAR

GPDMA_C3LLR

GPDMA_C4LBAR

GPDMA_C4FCR

GPDMA_C4SR

GPDMA_C4CR

GPDMA_C4TR1

GPDMA_C4TR2

GPDMA_C4BR1

GPDMA_C4SAR

GPDMA_C4DAR

GPDMA_C4LLR

GPDMA_C5LBAR

GPDMA_C5FCR

GPDMA_C5SR

GPDMA_C5CR

GPDMA_C5TR1

GPDMA_C5TR2

GPDMA_C5BR1

GPDMA_C5SAR

GPDMA_C5DAR

GPDMA_C5LLR

GPDMA_C6LBAR

GPDMA_C6FCR

GPDMA_C6SR

GPDMA_C6CR

GPDMA_C6TR1

GPDMA_C6TR2

GPDMA_C6BR1

GPDMA_C6SAR

GPDMA_C6DAR

GPDMA_C6LLR

GPDMA_C7LBAR

GPDMA_C7FCR

GPDMA_C7SR

GPDMA_C7CR

GPDMA_PRIVCFGR

GPDMA_C7TR1

GPDMA_C7TR2

GPDMA_C7BR1

GPDMA_C7SAR

GPDMA_C7DAR

GPDMA_C7LLR

GPDMA_C8LBAR

GPDMA_C8FCR

GPDMA_C8SR

GPDMA_C8CR

GPDMA_C8TR1

GPDMA_C8TR2

GPDMA_C8BR1