LPDMA_SECCFGR

LPDMA_SMISR

LPDMA_C1TR1

LPDMA_C1TR2

LPDMA_C1BR1

LPDMA_C1SAR

LPDMA_C1DAR

LPDMA_C1LLR

LPDMA_C2LBAR

LPDMA_C2FCR

LPDMA_C2SR

LPDMA_C2CR

LPDMA_C2TR1

LPDMA_C2TR2

LPDMA_C2BR1

LPDMA_C2SAR

LPDMA_C2DAR

LPDMA_C2LLR

LPDMA_C3LBAR

LPDMA_C3FCR

LPDMA_C3SR

LPDMA_C3CR

LPDMA_C3TR1

LPDMA_C3TR2

LPDMA_C3BR1

LPDMA_C3SAR

LPDMA_C3DAR

LPDMA_C3LLR

LPDMA_PRIVCFGR

LPDMA_C0LBAR

LPDMA_C0FCR

LPDMA_C0SR

LPDMA_C0CR

LPDMA_RCFGLOCKR

LPDMA_C0TR1

LPDMA_C0TR2

LPDMA_C0BR1

LPDMA_C0SAR

LPDMA_C0DAR

LPDMA_MISR

LPDMA_C0LLR

LPDMA_C1LBAR

LPDMA_C1FCR

LPDMA_C1SR

LPDMA_C1CR

SEC0 : SEC0
bits : 0 - 0 (1 bit)
access : read-write

SEC1 : SEC1
bits : 1 - 1 (1 bit)
access : read-write

SEC2 : SEC2
bits : 2 - 2 (1 bit)
access : read-write

SEC3 : SEC3
bits : 3 - 3 (1 bit)
access : read-write

MIS0 : MIS0
bits : 0 - 0 (1 bit)
access : read-only

MIS1 : MIS1
bits : 1 - 1 (1 bit)
access : read-only

MIS2 : MIS2
bits : 2 - 2 (1 bit)
access : read-only

MIS3 : MIS3
bits : 3 - 3 (1 bit)
access : read-only

SDW_LOG2 : binary logarithm of the source data width of a single in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. a source block size must be a multiple of the source data width (LPDMA_CxBR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address LPDMA_CxSAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SINC : source incrementing single The source address, pointed by LPDMA_CxSAR, is kept constant after a single transfer or is incremented by the offset value corresponding to a contiguous data after a single transfer.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAM : padding/alignment mode If DDW_LOG2[1:0]=SDW_LOG2[1:0]: if the data width of a single destination transfer is equal to the data width of a single source transfer, this bit is ignored. Else: Case 1: If destination data width > source data width Case 2: If destination data width < source data width
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SSEC : security attribute of the LPDMA transfer from the source If LPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx =1 . A secure write is ignored when LPDMA_SECCFGR.SECx = 0. When LPDMA_SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer from the source is non-secure.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DDW_LOG2 : binary logarithm of the destination data width of a single in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination single transfer must have an aligned address with its data width (start address LPDMA_CxDAR[2:0] versus DDW_LOG2[1:0]). Otherwise a user setting error is reported and none transfer is issued.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINC : destination incrementing single The destination address, pointed by LPDMA_CxDAR, is kept constant after a single transfer, or is incremented by the offset value corresponding to a contiguous data after a single transfer.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DSEC : security attribute of the LPDMA transfer to the destination If LPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx = 1. A secure write is ignored when LPDMA_SECCFGR.SECx = 0. When LPDMA_SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer to the destination is non-secure.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQSEL : DMA hardware request selection These bits are ignored if channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per request. Note: The user must not assign a same input hardware request (same REQSEL[4:0] value) to different active DMA channels (LPDMA_CxCR.EN = 1 and LPDMA_CxTR2.SWREQ = 0 for these channels). DMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting.
bits : 0 - 4 (5 bit)
access : read-write

SWREQ : software request This bit is internally taken into account when LPDMA_CxCR.EN is asserted.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BREQ : block hardware request If the channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIGM : trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (LPDMA_CxCR.EN asserted) with TRIGPOL[1:0] = 0b00 or 0b11, these TRIGM[1:0] bits are ignored. Else, a DMA transfer is conditioned by at least one trigger hit: The LPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 0b01 or respectively TRIGPOL[1:0] = 0b10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[4:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the LPDMA_CxTR2 with a new value for any of TRIGSEL[4:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized, and a trigger overrun flag is reported (LPDMA_CxSR.TOF = 1), an interrupt is generated if enabled (LPDMA_CxCR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun.
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIGSEL : trigger event input selection These bits select the trigger event input of the LPDMA transfer (as per Programmed LPDMA1 trigger), with an active trigger event if TRIGPOL[1:0] = 00.
bits : 16 - 20 (5 bit)
access : read-write

TRIGPOL : trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[4:0].
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCEM : transfer complete event mode These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1.
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BNDT : block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if LPDMA_CxLLR.UB1 = 1, this field is updated by the LLI in the memory. - if LPDMA_CxLLR.UB1 = 0 and if there is at least one non null Uxx update bit, this field is internally restored to the programmed value. - if all LPDMA_CxLLR.Uxx = 0 and if LPDMA_CxLLR.LA[15:0] = 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if LPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus LPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.
bits : 0 - 15 (16 bit)
access : read-write

SA : source address This field is the pointer to the address from which the next data is read. During the channel activity, depending on the source addressing mode (LPDMA_CxTR1.SINC), this field is either kept fixed or incremented by the data width (LPDMA_CxTR1.SDW_LOG2[1:0]) after each single source data, reflecting the next address from which data is read. In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by LPDMA from the memory, provided the LLI is set with LPDMA_CxLLR.USA = 1. Note: A source address must be aligned with the programmed data width of a source single (SA[32:0] versus LPDMA_CxTR1.SDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued.
bits : 0 - 31 (32 bit)
access : read-write

DA : destination address This field is the pointer to the address from which the next data is written. During the channel activity, depending on the destination addressing mode (LPDMA_CxTR1.DINC), this field is kept fixed or incremented by the data width (LPDMA_CxTR1.DDW_LOG2[21:0]) after each single destination data, reflecting the next address from which data is written. In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by DMA from the memory, provided the LLI is set with LPDMA_CxLLR.UDA = 1. Note: A destination address must be aligned with the programmed data width of a destination single (DA[2:0] versus LPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued.
bits : 0 - 31 (32 bit)
access : read-write

LA : pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file (LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.
bits : 2 - 15 (14 bit)
access : read-write

ULL : Update LPDMA_CxLLR register from memory This bit is used to control the update of the LPDMA_CxLLR register from the memory during the link transfer.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UDA : Update LPDMA_CxDAR register from memory This bit is used to control the update of the LPDMA_CxDAR register from the memory during the link transfer.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USA : update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UB1 : Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UT2 : Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UT1 : Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LBA : linked-list base address of LPDMA channel x
bits : 16 - 31 (16 bit)
access : read-write

TCF : transfer complete flag clear
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

HTF : half transfer flag clear
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

DTEF : data transfer error flag clear
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

ULEF : update link transfer error flag clear
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

USEF : user setting error flag clear
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SUSPF : completed suspension flag clear
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

IDLEF : idle flag This idle flag is de-asserted by hardware when the channel is enabled (LPDMA_CxCR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state).
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TCF : transfer complete flag A transfer complete event is a block transfer complete or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode LPDMA_CxTR2.TCEM[1:0].
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HTF : half transfer flag An half transfer event is an half block transfer that occurs when half of the bytes of the source block size (rounded-up integer of LPDMA_CxBR1.BNDT[15:0] / 2) has been transferred to the destination.
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DTEF : data transfer error flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ULEF : update link transfer error flag
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

USEF : user setting error flag
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SUSPF : completed suspension flag
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

EN : enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESET : reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (LPDMA_CxSR.SUSPF = 1 and LPDMA_CxSR.IDLEF = LPDMA_CxCR.EN = 1) - channel in disabled state (LPDMA_CxSR.IDLEF = 1 and LPDMA_CxCR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR) before enabling again the channel (see the programming sequence in ).
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SUSP : suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in sequence.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCIE : transfer complete interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HTIE : half transfer complete interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTEIE : data transfer error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ULEIE : update link transfer error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USEIE : user setting error interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SUSPIE : completed suspension interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOIE : trigger overrun interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LSM : Link step mode First the block transfer is executed as defined by the current internal register file until LPDMA_CxBR1.BNDT[15:0 ] =0). Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRIO : priority level of the channel x LPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SDW_LOG2 : binary logarithm of the source data width of a single in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. a source block size must be a multiple of the source data width (LPDMA_CxBR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address LPDMA_CxSAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SINC : source incrementing single The source address, pointed by LPDMA_CxSAR, is kept constant after a single transfer or is incremented by the offset value corresponding to a contiguous data after a single transfer.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAM : padding/alignment mode If DDW_LOG2[1:0]=SDW_LOG2[1:0]: if the data width of a single destination transfer is equal to the data width of a single source transfer, this bit is ignored. Else: Case 1: If destination data width > source data width Case 2: If destination data width < source data width
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SSEC : security attribute of the LPDMA transfer from the source If LPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx =1 . A secure write is ignored when LPDMA_SECCFGR.SECx = 0. When LPDMA_SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer from the source is non-secure.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DDW_LOG2 : binary logarithm of the destination data width of a single in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination single transfer must have an aligned address with its data width (start address LPDMA_CxDAR[2:0] versus DDW_LOG2[1:0]). Otherwise a user setting error is reported and none transfer is issued.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINC : destination incrementing single The destination address, pointed by LPDMA_CxDAR, is kept constant after a single transfer, or is incremented by the offset value corresponding to a contiguous data after a single transfer.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DSEC : security attribute of the LPDMA transfer to the destination If LPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx = 1. A secure write is ignored when LPDMA_SECCFGR.SECx = 0. When LPDMA_SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer to the destination is non-secure.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQSEL : DMA hardware request selection These bits are ignored if channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per request. Note: The user must not assign a same input hardware request (same REQSEL[4:0] value) to different active DMA channels (LPDMA_CxCR.EN = 1 and LPDMA_CxTR2.SWREQ = 0 for these channels). DMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting.
bits : 0 - 4 (5 bit)
access : read-write

SWREQ : software request This bit is internally taken into account when LPDMA_CxCR.EN is asserted.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BREQ : block hardware request If the channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIGM : trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (LPDMA_CxCR.EN asserted) with TRIGPOL[1:0] = 0b00 or 0b11, these TRIGM[1:0] bits are ignored. Else, a DMA transfer is conditioned by at least one trigger hit: The LPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 0b01 or respectively TRIGPOL[1:0] = 0b10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[4:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the LPDMA_CxTR2 with a new value for any of TRIGSEL[4:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized, and a trigger overrun flag is reported (LPDMA_CxSR.TOF = 1), an interrupt is generated if enabled (LPDMA_CxCR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun.
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIGSEL : trigger event input selection These bits select the trigger event input of the LPDMA transfer (as per Programmed LPDMA1 trigger), with an active trigger event if TRIGPOL[1:0] = 00.
bits : 16 - 20 (5 bit)
access : read-write

TRIGPOL : trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[4:0].
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCEM : transfer complete event mode These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1.
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BNDT : block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if LPDMA_CxLLR.UB1 = 1, this field is updated by the LLI in the memory. - if LPDMA_CxLLR.UB1 = 0 and if there is at least one non null Uxx update bit, this field is internally restored to the programmed value. - if all LPDMA_CxLLR.Uxx = 0 and if LPDMA_CxLLR.LA[15:0] = 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if LPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus LPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.
bits : 0 - 15 (16 bit)
access : read-write

SA : source address This field is the pointer to the address from which the next data is read. During the channel activity, depending on the source addressing mode (LPDMA_CxTR1.SINC), this field is either kept fixed or incremented by the data width (LPDMA_CxTR1.SDW_LOG2[1:0]) after each single source data, reflecting the next address from which data is read. In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by LPDMA from the memory, provided the LLI is set with LPDMA_CxLLR.USA = 1. Note: A source address must be aligned with the programmed data width of a source single (SA[32:0] versus LPDMA_CxTR1.SDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued.
bits : 0 - 31 (32 bit)
access : read-write

DA : destination address This field is the pointer to the address from which the next data is written. During the channel activity, depending on the destination addressing mode (LPDMA_CxTR1.DINC), this field is kept fixed or incremented by the data width (LPDMA_CxTR1.DDW_LOG2[21:0]) after each single destination data, reflecting the next address from which data is written. In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by DMA from the memory, provided the LLI is set with LPDMA_CxLLR.UDA = 1. Note: A destination address must be aligned with the programmed data width of a destination single (DA[2:0] versus LPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued.
bits : 0 - 31 (32 bit)
access : read-write

LA : pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file (LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.
bits : 2 - 15 (14 bit)
access : read-write

ULL : Update LPDMA_CxLLR register from memory This bit is used to control the update of the LPDMA_CxLLR register from the memory during the link transfer.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UDA : Update LPDMA_CxDAR register from memory This bit is used to control the update of the LPDMA_CxDAR register from the memory during the link transfer.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USA : update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UB1 : Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UT2 : Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UT1 : Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LBA : linked-list base address of LPDMA channel x
bits : 16 - 31 (16 bit)
access : read-write

TCF : transfer complete flag clear
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

HTF : half transfer flag clear
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

DTEF : data transfer error flag clear
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

ULEF : update link transfer error flag clear
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

USEF : user setting error flag clear
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SUSPF : completed suspension flag clear
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

IDLEF : idle flag This idle flag is de-asserted by hardware when the channel is enabled (LPDMA_CxCR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state).
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TCF : transfer complete flag A transfer complete event is a block transfer complete or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode LPDMA_CxTR2.TCEM[1:0].
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HTF : half transfer flag An half transfer event is an half block transfer that occurs when half of the bytes of the source block size (rounded-up integer of LPDMA_CxBR1.BNDT[15:0] / 2) has been transferred to the destination.
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DTEF : data transfer error flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ULEF : update link transfer error flag
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

USEF : user setting error flag
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SUSPF : completed suspension flag
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

EN : enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESET : reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (LPDMA_CxSR.SUSPF = 1 and LPDMA_CxSR.IDLEF = LPDMA_CxCR.EN = 1) - channel in disabled state (LPDMA_CxSR.IDLEF = 1 and LPDMA_CxCR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR) before enabling again the channel (see the programming sequence in ).
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SUSP : suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in sequence.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCIE : transfer complete interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HTIE : half transfer complete interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTEIE : data transfer error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ULEIE : update link transfer error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USEIE : user setting error interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SUSPIE : completed suspension interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOIE : trigger overrun interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LSM : Link step mode First the block transfer is executed as defined by the current internal register file until LPDMA_CxBR1.BNDT[15:0 ] =0). Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRIO : priority level of the channel x LPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SDW_LOG2 : binary logarithm of the source data width of a single in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. a source block size must be a multiple of the source data width (LPDMA_CxBR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address LPDMA_CxSAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SINC : source incrementing single The source address, pointed by LPDMA_CxSAR, is kept constant after a single transfer or is incremented by the offset value corresponding to a contiguous data after a single transfer.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAM : padding/alignment mode If DDW_LOG2[1:0]=SDW_LOG2[1:0]: if the data width of a single destination transfer is equal to the data width of a single source transfer, this bit is ignored. Else: Case 1: If destination data width > source data width Case 2: If destination data width < source data width
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SSEC : security attribute of the LPDMA transfer from the source If LPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx =1 . A secure write is ignored when LPDMA_SECCFGR.SECx = 0. When LPDMA_SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer from the source is non-secure.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DDW_LOG2 : binary logarithm of the destination data width of a single in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination single transfer must have an aligned address with its data width (start address LPDMA_CxDAR[2:0] versus DDW_LOG2[1:0]). Otherwise a user setting error is reported and none transfer is issued.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINC : destination incrementing single The destination address, pointed by LPDMA_CxDAR, is kept constant after a single transfer, or is incremented by the offset value corresponding to a contiguous data after a single transfer.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DSEC : security attribute of the LPDMA transfer to the destination If LPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx = 1. A secure write is ignored when LPDMA_SECCFGR.SECx = 0. When LPDMA_SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer to the destination is non-secure.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQSEL : DMA hardware request selection These bits are ignored if channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per request. Note: The user must not assign a same input hardware request (same REQSEL[4:0] value) to different active DMA channels (LPDMA_CxCR.EN = 1 and LPDMA_CxTR2.SWREQ = 0 for these channels). DMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting.
bits : 0 - 4 (5 bit)
access : read-write

SWREQ : software request This bit is internally taken into account when LPDMA_CxCR.EN is asserted.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BREQ : block hardware request If the channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIGM : trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (LPDMA_CxCR.EN asserted) with TRIGPOL[1:0] = 0b00 or 0b11, these TRIGM[1:0] bits are ignored. Else, a DMA transfer is conditioned by at least one trigger hit: The LPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 0b01 or respectively TRIGPOL[1:0] = 0b10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[4:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the LPDMA_CxTR2 with a new value for any of TRIGSEL[4:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized, and a trigger overrun flag is reported (LPDMA_CxSR.TOF = 1), an interrupt is generated if enabled (LPDMA_CxCR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun.
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIGSEL : trigger event input selection These bits select the trigger event input of the LPDMA transfer (as per Programmed LPDMA1 trigger), with an active trigger event if TRIGPOL[1:0] = 00.
bits : 16 - 20 (5 bit)
access : read-write

TRIGPOL : trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[4:0].
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCEM : transfer complete event mode These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1.
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BNDT : block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if LPDMA_CxLLR.UB1 = 1, this field is updated by the LLI in the memory. - if LPDMA_CxLLR.UB1 = 0 and if there is at least one non null Uxx update bit, this field is internally restored to the programmed value. - if all LPDMA_CxLLR.Uxx = 0 and if LPDMA_CxLLR.LA[15:0] = 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if LPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus LPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.
bits : 0 - 15 (16 bit)
access : read-write

SA : source address This field is the pointer to the address from which the next data is read. During the channel activity, depending on the source addressing mode (LPDMA_CxTR1.SINC), this field is either kept fixed or incremented by the data width (LPDMA_CxTR1.SDW_LOG2[1:0]) after each single source data, reflecting the next address from which data is read. In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by LPDMA from the memory, provided the LLI is set with LPDMA_CxLLR.USA = 1. Note: A source address must be aligned with the programmed data width of a source single (SA[32:0] versus LPDMA_CxTR1.SDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued.
bits : 0 - 31 (32 bit)
access : read-write

DA : destination address This field is the pointer to the address from which the next data is written. During the channel activity, depending on the destination addressing mode (LPDMA_CxTR1.DINC), this field is kept fixed or incremented by the data width (LPDMA_CxTR1.DDW_LOG2[21:0]) after each single destination data, reflecting the next address from which data is written. In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by DMA from the memory, provided the LLI is set with LPDMA_CxLLR.UDA = 1. Note: A destination address must be aligned with the programmed data width of a destination single (DA[2:0] versus LPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued.
bits : 0 - 31 (32 bit)
access : read-write

LA : pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file (LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.
bits : 2 - 15 (14 bit)
access : read-write

ULL : Update LPDMA_CxLLR register from memory This bit is used to control the update of the LPDMA_CxLLR register from the memory during the link transfer.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UDA : Update LPDMA_CxDAR register from memory This bit is used to control the update of the LPDMA_CxDAR register from the memory during the link transfer.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USA : update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UB1 : Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UT2 : Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UT1 : Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRIV0 : PRIV0
bits : 0 - 0 (1 bit)
access : read-write

PRIV1 : PRIV1
bits : 1 - 1 (1 bit)
access : read-write

PRIV2 : PRIV2
bits : 2 - 2 (1 bit)
access : read-write

PRIV3 : PRIV3
bits : 3 - 3 (1 bit)
access : read-write

LBA : linked-list base address of LPDMA channel x
bits : 16 - 31 (16 bit)
access : read-write

TCF : transfer complete flag clear
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

HTF : half transfer flag clear
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

DTEF : data transfer error flag clear
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

ULEF : update link transfer error flag clear
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

USEF : user setting error flag clear
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SUSPF : completed suspension flag clear
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

IDLEF : idle flag This idle flag is de-asserted by hardware when the channel is enabled (LPDMA_CxCR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state).
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TCF : transfer complete flag A transfer complete event is a block transfer complete or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode LPDMA_CxTR2.TCEM[1:0].
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HTF : half transfer flag An half transfer event is an half block transfer that occurs when half of the bytes of the source block size (rounded-up integer of LPDMA_CxBR1.BNDT[15:0] / 2) has been transferred to the destination.
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DTEF : data transfer error flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ULEF : update link transfer error flag
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

USEF : user setting error flag
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SUSPF : completed suspension flag
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOF : trigger overrun flag clear
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

EN : enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESET : reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (LPDMA_CxSR.SUSPF = 1 and LPDMA_CxSR.IDLEF = LPDMA_CxCR.EN = 1) - channel in disabled state (LPDMA_CxSR.IDLEF = 1 and LPDMA_CxCR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR) before enabling again the channel (see the programming sequence in ).
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SUSP : suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in sequence.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCIE : transfer complete interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HTIE : half transfer complete interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTEIE : data transfer error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ULEIE : update link transfer error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration: