\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
SYSCFG secure configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCFGSEC : SYSCFG clock control security
bits : 0 - 0 (1 bit)
CLASSBSEC : CLASSBSEC
bits : 1 - 1 (1 bit)
FPUSEC : FPUSEC
bits : 3 - 3 (1 bit)
SYSCFG CPU secure lock register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKSVTAIRCR : LOCKSVTAIRCR
bits : 0 - 0 (1 bit)
LOCKSMPU : LOCKSMPU
bits : 1 - 1 (1 bit)
LOCKSAU : LOCKSAU
bits : 2 - 2 (1 bit)
configuration register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLL : LOCKUP (hardfault) output enable bit
bits : 0 - 0 (1 bit)
SPL : SRAM ECC lock bit
bits : 1 - 1 (1 bit)
PVDL : PVD lock enable bit
bits : 2 - 2 (1 bit)
ECCL : ECC Lock
bits : 3 - 3 (1 bit)
memory erase status register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCLR : MCLR
bits : 0 - 0 (1 bit)
IPMEE : IPMEE
bits : 16 - 16 (1 bit)
compensation cell control/status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN1 : EN1
bits : 0 - 0 (1 bit)
access : read-write
CS1 : CS1
bits : 1 - 1 (1 bit)
access : read-write
EN2 : EN2
bits : 2 - 2 (1 bit)
access : read-write
CS2 : CS2
bits : 3 - 3 (1 bit)
access : read-write
RDY1 : RDY1
bits : 8 - 8 (1 bit)
access : read-only
RDY2 : RDY2
bits : 9 - 9 (1 bit)
access : read-only
compensation cell value register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NCV1 : NCV1
bits : 0 - 3 (4 bit)
PCV1 : PCV1
bits : 4 - 7 (4 bit)
NCV2 : NCV2
bits : 8 - 11 (4 bit)
PCV2 : PCV2
bits : 12 - 15 (4 bit)
compensation cell code register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NCC1 : NCC1
bits : 0 - 3 (4 bit)
PCC1 : PCC1
bits : 4 - 7 (4 bit)
NCC2 : NCC2
bits : 8 - 11 (4 bit)
PCC2 : PCC2
bits : 12 - 15 (4 bit)
RSS command register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSSCMD : RSS commands
bits : 0 - 15 (16 bit)
configuration register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOSTEN : I/O analog switch voltage booster enable
bits : 8 - 8 (1 bit)
ANASWVDD : GPIO analog switch control voltage selection
bits : 9 - 9 (1 bit)
PB6_FMP : PB6_FMP
bits : 16 - 16 (1 bit)
PB7_FMP : PB7_FMP
bits : 17 - 17 (1 bit)
PB8_FMP : PB8_FMP
bits : 18 - 18 (1 bit)
PB9_FMP : PB9_FMP
bits : 19 - 19 (1 bit)
USB Type C and Power Delivery register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1ENRXFILTER : CC1ENRXFILTER
bits : 0 - 0 (1 bit)
CC2ENRXFILTER : CC2ENRXFILTER
bits : 1 - 1 (1 bit)
FPU interrupt mask register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPU_IE : Floating point unit interrupts enable bits
bits : 0 - 5 (6 bit)
SYSCFG CPU non-secure lock register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKNSVTOR : VTOR_NS register lock
bits : 0 - 0 (1 bit)
LOCKNSMPU : Non-secure MPU registers lock
bits : 1 - 1 (1 bit)
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