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SYSCFG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

SECCFGR

CSLOCKR

CFGR2

MESR

CCCSR

CCVR

CCCR

RSSCMDR

CFGR1

UCPDR

FPUIMR

CNSLCKR


SECCFGR

SYSCFG secure configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECCFGR SECCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGSEC CLASSBSEC FPUSEC

SYSCFGSEC : SYSCFG clock control security
bits : 0 - 0 (1 bit)

CLASSBSEC : CLASSBSEC
bits : 1 - 1 (1 bit)

FPUSEC : FPUSEC
bits : 3 - 3 (1 bit)


CSLOCKR

SYSCFG CPU secure lock register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSLOCKR CSLOCKR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKSVTAIRCR LOCKSMPU LOCKSAU

LOCKSVTAIRCR : LOCKSVTAIRCR
bits : 0 - 0 (1 bit)

LOCKSMPU : LOCKSMPU
bits : 1 - 1 (1 bit)

LOCKSAU : LOCKSAU
bits : 2 - 2 (1 bit)


CFGR2

configuration register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR2 CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLL SPL PVDL ECCL

CLL : LOCKUP (hardfault) output enable bit
bits : 0 - 0 (1 bit)

SPL : SRAM ECC lock bit
bits : 1 - 1 (1 bit)

PVDL : PVD lock enable bit
bits : 2 - 2 (1 bit)

ECCL : ECC Lock
bits : 3 - 3 (1 bit)


MESR

memory erase status register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MESR MESR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCLR IPMEE

MCLR : MCLR
bits : 0 - 0 (1 bit)

IPMEE : IPMEE
bits : 16 - 16 (1 bit)


CCCSR

compensation cell control/status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCCSR CCCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN1 CS1 EN2 CS2 RDY1 RDY2

EN1 : EN1
bits : 0 - 0 (1 bit)
access : read-write

CS1 : CS1
bits : 1 - 1 (1 bit)
access : read-write

EN2 : EN2
bits : 2 - 2 (1 bit)
access : read-write

CS2 : CS2
bits : 3 - 3 (1 bit)
access : read-write

RDY1 : RDY1
bits : 8 - 8 (1 bit)
access : read-only

RDY2 : RDY2
bits : 9 - 9 (1 bit)
access : read-only


CCVR

compensation cell value register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CCVR CCVR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NCV1 PCV1 NCV2 PCV2

NCV1 : NCV1
bits : 0 - 3 (4 bit)

PCV1 : PCV1
bits : 4 - 7 (4 bit)

NCV2 : NCV2
bits : 8 - 11 (4 bit)

PCV2 : PCV2
bits : 12 - 15 (4 bit)


CCCR

compensation cell code register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCCR CCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NCC1 PCC1 NCC2 PCC2

NCC1 : NCC1
bits : 0 - 3 (4 bit)

PCC1 : PCC1
bits : 4 - 7 (4 bit)

NCC2 : NCC2
bits : 8 - 11 (4 bit)

PCC2 : PCC2
bits : 12 - 15 (4 bit)


RSSCMDR

RSS command register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSSCMDR RSSCMDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSSCMD

RSSCMD : RSS commands
bits : 0 - 15 (16 bit)


CFGR1

configuration register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR1 CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOOSTEN ANASWVDD PB6_FMP PB7_FMP PB8_FMP PB9_FMP

BOOSTEN : I/O analog switch voltage booster enable
bits : 8 - 8 (1 bit)

ANASWVDD : GPIO analog switch control voltage selection
bits : 9 - 9 (1 bit)

PB6_FMP : PB6_FMP
bits : 16 - 16 (1 bit)

PB7_FMP : PB7_FMP
bits : 17 - 17 (1 bit)

PB8_FMP : PB8_FMP
bits : 18 - 18 (1 bit)

PB9_FMP : PB9_FMP
bits : 19 - 19 (1 bit)


UCPDR

USB Type C and Power Delivery register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UCPDR UCPDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1ENRXFILTER CC2ENRXFILTER

CC1ENRXFILTER : CC1ENRXFILTER
bits : 0 - 0 (1 bit)

CC2ENRXFILTER : CC2ENRXFILTER
bits : 1 - 1 (1 bit)


FPUIMR

FPU interrupt mask register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPUIMR FPUIMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPU_IE

FPU_IE : Floating point unit interrupts enable bits
bits : 0 - 5 (6 bit)


CNSLCKR

SYSCFG CPU non-secure lock register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNSLCKR CNSLCKR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKNSVTOR LOCKNSMPU

LOCKNSVTOR : VTOR_NS register lock
bits : 0 - 0 (1 bit)

LOCKNSMPU : Non-secure MPU registers lock
bits : 1 - 1 (1 bit)



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