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DBGMCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

IDCODE

APB2FZR

DBGMCU_DBG_AUTH_HOST (DBG_AUTH_HOST)

DBGMCU_DBG_AUTH_DEVICE (DBG_AUTH_DEVICE)

APB3FZR

AHB1FZR

AHB3FZR

CR

APB1LFZR

APB1HFZR

DBGMCU_SR (SR)

PIDR4

PIDR0

PIDR1

PIDR2

PIDR3

CIDR0

CIDR1

CIDR2

CIDR3


IDCODE

DBGMCU_IDCODE
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDCODE IDCODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEV_ID REV_ID

DEV_ID : Device dentification
bits : 0 - 11 (12 bit)

REV_ID : Revision
bits : 16 - 31 (16 bit)


APB2FZR

Debug MCU APB2 peripheral freeze register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2FZR APB2FZR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_TIM1_STOP DBG_TIM8_STOP DBG_TIM15_STOP DBG_TIM16_STOP DBG_TIM17_STOP

DBG_TIM1_STOP : TIM1 counter stopped when core is halted
bits : 11 - 11 (1 bit)

DBG_TIM8_STOP : TIM8 stop in debug
bits : 13 - 13 (1 bit)

DBG_TIM15_STOP : TIM15 counter stopped when core is halted
bits : 16 - 16 (1 bit)

DBG_TIM16_STOP : TIM16 counter stopped when core is halted
bits : 17 - 17 (1 bit)

DBG_TIM17_STOP : DBG_TIM17_STOP
bits : 18 - 18 (1 bit)


DBGMCU_DBG_AUTH_HOST (DBG_AUTH_HOST)

DBGMCU debug host authentication register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DBGMCU_DBG_AUTH_HOST DBGMCU_DBG_AUTH_HOST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUTH_KEY

AUTH_KEY : Device authentication key The device specific 64-bit authentication key (OEM key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory.
bits : 0 - 31 (32 bit)


DBGMCU_DBG_AUTH_DEVICE (DBG_AUTH_DEVICE)

DBGMCU debug device authentication register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DBGMCU_DBG_AUTH_DEVICE DBGMCU_DBG_AUTH_DEVICE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUTH_ID

AUTH_ID : Device specific ID Device specific ID used for RDP regression.
bits : 0 - 31 (32 bit)


APB3FZR

Debug MCU APB3 peripheral freeze register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB3FZR APB3FZR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_I2C3_STOP DBG_LPTIM1_STOP DBG_LPTIM3_STOP DBG_LPTIM4_STOP DBG_RTC_STOP

DBG_I2C3_STOP : I2C3 stop in debug
bits : 10 - 10 (1 bit)

DBG_LPTIM1_STOP : LPTIM1 stop in debug
bits : 17 - 17 (1 bit)

DBG_LPTIM3_STOP : LPTIM3 stop in debug
bits : 18 - 18 (1 bit)

DBG_LPTIM4_STOP : LPTIM4 stop in debug
bits : 19 - 19 (1 bit)

DBG_RTC_STOP : RTC stop in debug
bits : 30 - 30 (1 bit)


AHB1FZR

Debug MCU AHB1 peripheral freeze register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB1FZR AHB1FZR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_GPDMA0_STOP DBG_GPDMA1_STOP DBG_GPDMA2_STOP DBG_GPDMA3_STOP DBG_GPDMA4_STOP DBG_GPDMA5_STOP DBG_GPDMA6_STOP DBG_GPDMA7_STOP DBG_GPDMA8_STOP DBG_GPDMA9_STOP DBG_GPDMA10_STOP DBG_GPDMA11_STOP DBG_GPDMA12_STOP DBG_GPDMA13_STOP DBG_GPDMA14_STOP DBG_GPDMA15_STOP

DBG_GPDMA0_STOP : GPDMA channel 0 stop in debug
bits : 0 - 0 (1 bit)

DBG_GPDMA1_STOP : GPDMA channel 1 stop in debug
bits : 1 - 1 (1 bit)

DBG_GPDMA2_STOP : GPDMA channel 2 stop in debug
bits : 2 - 2 (1 bit)

DBG_GPDMA3_STOP : GPDMA channel 3 stop in debug
bits : 3 - 3 (1 bit)

DBG_GPDMA4_STOP : GPDMA channel 4 stop in debug
bits : 4 - 4 (1 bit)

DBG_GPDMA5_STOP : GPDMA channel 5 stop in debug
bits : 5 - 5 (1 bit)

DBG_GPDMA6_STOP : GPDMA channel 6 stop in debug
bits : 6 - 6 (1 bit)

DBG_GPDMA7_STOP : GPDMA channel 7 stop in debug
bits : 7 - 7 (1 bit)

DBG_GPDMA8_STOP : GPDMA channel 8 stop in debug
bits : 8 - 8 (1 bit)

DBG_GPDMA9_STOP : GPDMA channel 9 stop in debug
bits : 9 - 9 (1 bit)

DBG_GPDMA10_STOP : GPDMA channel 10 stop in debug
bits : 10 - 10 (1 bit)

DBG_GPDMA11_STOP : GPDMA channel 11 stop in debug
bits : 11 - 11 (1 bit)

DBG_GPDMA12_STOP : GPDMA channel 12 stop in debug
bits : 12 - 12 (1 bit)

DBG_GPDMA13_STOP : GPDMA channel 13 stop in debug
bits : 13 - 13 (1 bit)

DBG_GPDMA14_STOP : GPDMA channel 14 stop in debug
bits : 14 - 14 (1 bit)

DBG_GPDMA15_STOP : GPDMA channel 15 stop in debug
bits : 15 - 15 (1 bit)


AHB3FZR

Debug MCU AHB3 peripheral freeze register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB3FZR AHB3FZR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_LPDMA0_STOP DBG_LPDMA1_STOP DBG_LPDMA2_STOP DBG_LPDMA3_STOP

DBG_LPDMA0_STOP : LPDMA channel 0 stop in debug
bits : 0 - 0 (1 bit)

DBG_LPDMA1_STOP : LPDMA channel 1 stop in debug
bits : 1 - 1 (1 bit)

DBG_LPDMA2_STOP : LPDMA channel 2 stop in debug
bits : 2 - 2 (1 bit)

DBG_LPDMA3_STOP : LPDMA channel 3 stop in debug
bits : 3 - 3 (1 bit)


CR

Debug MCU configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_STOP DBG_STANDBY TRACE_IOEN TRACE_EN TRACE_MODE

DBG_STOP : Debug Stop mode
bits : 1 - 1 (1 bit)

DBG_STANDBY : Debug Standby mode
bits : 2 - 2 (1 bit)

TRACE_IOEN : Trace pin assignment control
bits : 4 - 4 (1 bit)

TRACE_EN : trace port and clock enable
bits : 5 - 5 (1 bit)

TRACE_MODE : Trace pin assignment control
bits : 6 - 7 (2 bit)


APB1LFZR

Debug MCU APB1L peripheral freeze register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1LFZR APB1LFZR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_TIM2_STOP DBG_TIM3_STOP DBG_TIM4_STOP DBG_TIM5_STOP DBG_TIM6_STOP DBG_TIM7_STOP DBG_WWDG_STOP DBG_IWDG_STOP DBG_I2C1_STOP DBG_I2C2_STOP

DBG_TIM2_STOP : TIM2 stop in debug
bits : 0 - 0 (1 bit)

DBG_TIM3_STOP : TIM3 stop in debug
bits : 1 - 1 (1 bit)

DBG_TIM4_STOP : TIM4 stop in debug
bits : 2 - 2 (1 bit)

DBG_TIM5_STOP : TIM5 stop in debug
bits : 3 - 3 (1 bit)

DBG_TIM6_STOP : TIM6 stop in debug
bits : 4 - 4 (1 bit)

DBG_TIM7_STOP : TIM7 stop in debug
bits : 5 - 5 (1 bit)

DBG_WWDG_STOP : Window watchdog counter stop in debug
bits : 11 - 11 (1 bit)

DBG_IWDG_STOP : Independent watchdog counter stop in debug
bits : 12 - 12 (1 bit)

DBG_I2C1_STOP : I2C1 SMBUS timeout stop in debug
bits : 21 - 21 (1 bit)

DBG_I2C2_STOP : I2C2 SMBUS timeout stop in debug
bits : 22 - 22 (1 bit)


APB1HFZR

Debug MCU APB1H peripheral freeze register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1HFZR APB1HFZR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_I2C4_STOP DBG_LPTIM2_STOP

DBG_I2C4_STOP : I2C4 stop in debug
bits : 1 - 1 (1 bit)

DBG_LPTIM2_STOP : LPTIM2 stop in debug
bits : 5 - 5 (1 bit)


DBGMCU_SR (SR)

DBGMCU status register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DBGMCU_SR DBGMCU_SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AP_PRESENT AP_LOCKED

AP_PRESENT : Bit n identifies whether access port AP n is present in device Bit n = 0: APn absent Bit n = 1: APn present
bits : 0 - 7 (8 bit)

AP_LOCKED : DECLARATION TO BE CONFIRMED by PRODUCT OWNER! Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked) Bit n = 0: APn locked Bit n = 1: APn enabled
bits : 8 - 15 (8 bit)


PIDR4

Debug MCU CoreSight peripheral identity register 4
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR4 PIDR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEP106CON KCOUNT_4

JEP106CON : JEP106 continuation code
bits : 0 - 3 (4 bit)

KCOUNT_4 : register file size
bits : 4 - 7 (4 bit)


PIDR0

Debug MCU CoreSight peripheral identity register 0
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR0 PIDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARTNUM

PARTNUM : part number bits [7:0]
bits : 0 - 7 (8 bit)


PIDR1

Debug MCU CoreSight peripheral identity register 1
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR1 PIDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARTNUM JEP106ID

PARTNUM : part number bits [11:8]
bits : 0 - 3 (4 bit)

JEP106ID : JEP106 identity code bits [3:0]
bits : 4 - 7 (4 bit)


PIDR2

Debug MCU CoreSight peripheral identity register 2
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR2 PIDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEP106ID JEDEC REVISION

JEP106ID : JEP106 identity code bits [6:4]
bits : 0 - 2 (3 bit)

JEDEC : JEDEC assigned value
bits : 3 - 3 (1 bit)

REVISION : component revision number
bits : 4 - 7 (4 bit)


PIDR3

Debug MCU CoreSight peripheral identity register 3
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR3 PIDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMOD REVAND

CMOD : customer modified
bits : 0 - 3 (4 bit)

REVAND : metal fix version
bits : 4 - 7 (4 bit)


CIDR0

Debug MCU CoreSight component identity register 0
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR0 CIDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLE

PREAMBLE : component identification bits [7:0]
bits : 0 - 7 (8 bit)


CIDR1

Debug MCU CoreSight component identity register 1
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR1 CIDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLE CLASS

PREAMBLE : component identification bits [11:8]
bits : 0 - 3 (4 bit)

CLASS : component identification bits [15:12] - component class
bits : 4 - 7 (4 bit)


CIDR2

Debug MCU CoreSight component identity register 2
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR2 CIDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLE

PREAMBLE : component identification bits [23:16]
bits : 0 - 7 (8 bit)


CIDR3

Debug MCU CoreSight component identity register 3
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR3 CIDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLE

PREAMBLE : component identification bits [31:24]
bits : 0 - 7 (8 bit)



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