UCPD_CFGR1

UCPD_IMR

UCPD_SR

UCPD_ICR

UCPD_TX_ORDSETR

UCPD_TX_PAYSZR

UCPD_TXDR

UCPD_RX_ORDSETR

UCPD_RX_PAYSZR

UCPD_RXDR

UCPD_RX_ORDEXTR1

UCPD_RX_ORDEXTR2

UCPD_CFGR2

UCPD_CFGR3

UCPD_CR

HBITCLKDIV : Division ratio for producing half-bit clock The bitfield determines the division ratio (the bitfield value plus one) of a ucpd_clk divider producing half-bit clock (hbit_clk).
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IFRGAP : Division ratio for producing inter-frame gap timer clock The bitfield determines the division ratio (the bitfield value minus one) of a ucpd_clk divider producing inter-frame gap timer clock (tInterFrameGap). The division ratio 15 is to apply for Tx clock at the USB PD 2.0 specification nominal value. The division ratios below 15 are to apply for Tx clock below nominal, and the division ratios above 15 for Tx clock above nominal.
bits : 6 - 10 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRANSWIN : Transition window duration The bitfield determines the division ratio (the bitfield value minus one) of a hbit_clk divider producing tTransitionWindow interval. Set a value that produces an interval of 12 to 20 us, taking into account the ucpd_clk frequency and the HBITCLKDIV[5:0] bitfield setting.
bits : 11 - 15 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PSC_USBPDCLK : Pre-scaler division ratio for generating ucpd_clk The bitfield determines the division ratio of a kernel clock pre-scaler producing UCPD peripheral clock (ucpd_clk). It is recommended to use the pre-scaler so as to set the ucpd_clk frequency in the range from 6 to 9 MHz.
bits : 17 - 19 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXORDSETEN : Receiver ordered set enable The bitfield determines the types of ordered sets that the receiver must detect. When set/cleared, each bit enables/disables a specific function: 0bxxxxxxxx1: SOP detect enabled 0bxxxxxxx1x: SOP' detect enabled 0bxxxxxx1xx: SOP'' detect enabled 0bxxxxx1xxx: Hard Reset detect enabled 0bxxxx1xxxx: Cable Detect reset enabled 0bxxx1xxxxx: SOP'_Debug enabled 0bxx1xxxxxx: SOP''_Debug enabled 0bx1xxxxxxx: SOP extension#1 enabled 0b1xxxxxxxx: SOP extension#2 enabled
bits : 20 - 28 (9 bit)
access : read-write

TXDMAEN : Transmission DMA mode enable When set, the bit enables DMA mode for transmission.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXDMAEN : Reception DMA mode enable When set, the bit enables DMA mode for reception.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UCPDEN : UCPD peripheral enable General enable of the UCPD peripheral. Upon disabling, the peripheral instantly quits any ongoing activity and all control bits and bitfields default to their reset values. They must be set to their desired values each time the peripheral transits from disabled to enabled state.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXISIE : TXIS interrupt enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXMSGDISCIE : TXMSGDISC interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXMSGSENTIE : TXMSGSENT interrupt enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXMSGABTIE : TXMSGABT interrupt enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HRSTDISCIE : HRSTDISC interrupt enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HRSTSENTIE : HRSTSENT interrupt enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXUNDIE : TXUND interrupt enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXNEIE : RXNE interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXORDDETIE : RXORDDET interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXHRSTDETIE : RXHRSTDET interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOVRIE : RXOVR interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXMSGENDIE : RXMSGEND interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPECEVT1IE : TYPECEVT1 interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

TYPECEVT2IE : TYPECEVT2 interrupt enable
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FRSEVTIE : FRSEVT interrupt enable
bits : 20 - 20 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXIS : Transmit interrupt status The flag indicates that the UCPD_TXDR register is empty and new data write is required (as the amount of data sent has not reached the payload size defined in the TXPAYSZ bitfield). The flag is cleared with the data write into the UCPD_TXDR register.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXMSGDISC : Message transmission discarded The flag indicates that a message transmission was dropped. The flag is cleared by setting the TXMSGDISCCF bit. Transmission of a message can be dropped if there is a concurrent receive in progress or at excessive noise on the line. After a Tx message is discarded, the flag is only raised when the CC line becomes idle.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXMSGSENT : Message transmission completed The flag indicates the completion of packet transmission. It is cleared by setting the TXMSGSENTCF bit. In the event of a message transmission interrupted by a Hard Reset, the flag is not raised.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXMSGABT : Transmit message abort The flag indicates that a Tx message is aborted due to a subsequent Hard Reset message send request taking priority during transmit. It is cleared by setting the TXMSGABTCF bit.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HRSTDISC : Hard Reset discarded The flag indicates that the Hard Reset message is discarded. The flag is cleared by setting the HRSTDISCCF bit.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HRSTSENT : Hard Reset message sent The flag indicates that the Hard Reset message is sent. The flag is cleared by setting the HRSTSENTCF bit.
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXUND : Tx data underrun detection The flag indicates that the Tx data register (UCPD_TXDR) was not written in time for a transmit message to execute normally. It is cleared by setting the TXUNDCF bit.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXNE : Receive data register not empty detection The flag indicates that the UCPD_RXDR register is not empty. It is automatically cleared upon reading UCPD_RXDR.
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXORDDET : Rx ordered set (4 K-codes) detection The flag indicates the detection of an ordered set. The relevant information is stored in the RXORDSET[2:0] bitfield of the UCPD_RX_ORDSET register. It is cleared by setting the RXORDDETCF bit.
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXHRSTDET : Rx Hard Reset receipt detection The flag indicates the receipt of valid Hard Reset message. It is cleared by setting the RXHRSTDETCF bit.
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXOVR : Rx data overflow detection The flag indicates Rx data buffer overflow. It is cleared by setting the RXOVRCF bit. The buffer overflow can occur if the received data are not read fast enough.
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXMSGEND : Rx message received The flag indicates whether a message (except Hard Reset message) has been received, regardless the CRC value. The flag is cleared by setting the RXMSGENDCF bit. The RXERR flag set when the RXMSGEND flag goes high indicates errors in the last-received message.
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXERR : Receive message error The flag indicates errors of the last Rx message declared (via RXMSGEND), such as incorrect CRC or truncated message (a line becoming static before EOP is met). It is asserted whenever the RXMSGEND flag is set.
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TYPECEVT1 : Type-C voltage level event on CC1 line The flag indicates a change of the TYPEC_VSTATE_CC1[1:0] bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit.
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TYPECEVT2 : Type-C voltage level event on CC2 line The flag indicates a change of the TYPEC_VSTATE_CC2[1:0] bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit.
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TYPEC_VSTATE_CC1 : The status bitfield indicates the voltage level on the CC1 line in its steady state. The voltage variation on the CC1 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value.
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TYPEC_VSTATE_CC2 : CC2 line voltage level The status bitfield indicates the voltage level on the CC2 line in its steady state. The voltage variation on the CC2 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value.
bits : 18 - 19 (2 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FRSEVT : FRS detection event The flag is cleared by setting the FRSEVTCF bit.
bits : 20 - 20 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXMSGDISCCF : Tx message discard flag (TXMSGDISC) clear Setting the bit clears the TXMSGDISC flag in the UCPD_SR register.
bits : 1 - 1 (1 bit)
access : write-only

TXMSGSENTCF : Tx message send flag (TXMSGSENT) clear Setting the bit clears the TXMSGSENT flag in the UCPD_SR register.
bits : 2 - 2 (1 bit)
access : write-only

TXMSGABTCF : Tx message abort flag (TXMSGABT) clear Setting the bit clears the TXMSGABT flag in the UCPD_SR register.
bits : 3 - 3 (1 bit)
access : write-only

HRSTDISCCF : Hard reset discard flag (HRSTDISC) clear Setting the bit clears the HRSTDISC flag in the UCPD_SR register.
bits : 4 - 4 (1 bit)
access : write-only

HRSTSENTCF : Hard reset send flag (HRSTSENT) clear Setting the bit clears the HRSTSENT flag in the UCPD_SR register.
bits : 5 - 5 (1 bit)
access : write-only

TXUNDCF : Tx underflow flag (TXUND) clear Setting the bit clears the TXUND flag in the UCPD_SR register.
bits : 6 - 6 (1 bit)
access : write-only

RXORDDETCF : Rx ordered set detect flag (RXORDDET) clear Setting the bit clears the RXORDDET flag in the UCPD_SR register.
bits : 9 - 9 (1 bit)
access : write-only

RXHRSTDETCF : Rx Hard Reset detect flag (RXHRSTDET) clear Setting the bit clears the RXHRSTDET flag in the UCPD_SR register.
bits : 10 - 10 (1 bit)
access : write-only

RXOVRCF : Rx overflow flag (RXOVR) clear Setting the bit clears the RXOVR flag in the UCPD_SR register.
bits : 11 - 11 (1 bit)
access : write-only

RXMSGENDCF : Rx message received flag (RXMSGEND) clear Setting the bit clears the RXMSGEND flag in the UCPD_SR register.
bits : 12 - 12 (1 bit)
access : write-only

TYPECEVT1CF : Type-C CC1 event flag (TYPECEVT1) clear Setting the bit clears the TYPECEVT1 flag in the UCPD_SR register
bits : 14 - 14 (1 bit)
access : write-only

TYPECEVT2CF : Type-C CC2 line event flag (TYPECEVT2) clear Setting the bit clears the TYPECEVT2 flag in the UCPD_SR register
bits : 15 - 15 (1 bit)
access : write-only

FRSEVTCF : FRS event flag (FRSEVT) clear Setting the bit clears the FRSEVT flag in the UCPD_SR register.
bits : 20 - 20 (1 bit)
access : write-only

TXORDSET : Ordered set to transmit The bitfield determines a full 20-bit sequence to transmit, consisting of four K-codes, each of five bits, defining the packet to transmit. The bit 0 (bit 0 of K-code1) is the first, the bit 19 (bit 4 of K‑code4) the last.
bits : 0 - 19 (20 bit)
access : read-write

TXPAYSZ : Payload size yet to transmit The bitfield is modified by software and by hardware. It contains the number of bytes of a payload (including header but excluding CRC) yet to transmit: each time a data byte is written into the UCPD_TXDR register, the bitfield value decrements and the TXIS bit is set, except when the bitfield value reaches zero. The enumerated values are standard payload sizes before the start of transmission.
bits : 0 - 9 (10 bit)
access : read-write

TXDATA : Data byte to transmit
bits : 0 - 7 (8 bit)
access : read-write

RXORDSET : Rx ordered set code detected
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXSOP3OF4 : The bit indicates the number of correct K‑codes. For debug purposes only.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXSOPKINVALID : The bitfield is for debug purposes only. Others: Invalid
bits : 4 - 6 (3 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXPAYSZ : Rx payload size received This bitfield contains the number of bytes of a payload (including header but excluding CRC) received: each time a new data byte is received in the UCPD_RXDR register, the bitfield value increments and the RXMSGEND flag is set (and an interrupt generated if enabled). The bitfield may return a spurious value when a byte reception is ongoing (the RXMSGEND flag is low).
bits : 0 - 9 (10 bit)
access : read-only

RXDATA : Data byte received
bits : 0 - 7 (8 bit)
access : read-only

RXSOPX1 : Ordered set 1 received The bitfield contains a full 20-bit sequence received, consisting of four K‑codes, each of five bits. The bit 0 (bit 0 of K‑code1) is receive first, the bit 19 (bit 4 of K‑code4) last.
bits : 0 - 19 (20 bit)
access : read-write

RXSOPX2 : Ordered set 2 received The bitfield contains a full 20-bit sequence received, consisting of four K‑codes, each of five bits. The bit 0 (bit 0 of K‑code1) is receive first, the bit 19 (bit 4 of K‑code4) last.
bits : 0 - 19 (20 bit)
access : read-write

RXFILTDIS : BMC decoder Rx pre-filter enable The sampling clock is that of the receiver (that is, after pre-scaler).
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXFILT2N3 : BMC decoder Rx pre-filter sampling method Number of consistent consecutive samples before confirming a new value.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FORCECLK : Force ClkReq clock request
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WUPEN : Wakeup from Stop mode enable Setting the bit enables the UCPD_ASYNC_INT signal.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIM1_NG_CCRPD : SW trim value for RPD resistors on the CC1 line
bits : 0 - 3 (4 bit)
access : read-write

TRIM1_NG_CC3A0 : SW trim value for Iref on the CC1 line
bits : 9 - 12 (4 bit)
access : read-write

TRIM2_NG_CCRPD : SW trim value for RPD resistors on the CC2 line
bits : 16 - 19 (4 bit)
access : read-write

TRIM2_NG_CC3A0 : SW trim value for Iref on the CC2 line
bits : 25 - 28 (4 bit)
access : read-write

TXMODE : Type of Tx packet Writing the bitfield triggers the action as follows, depending on the value: Others: invalid From V1.1 of the USB PD specification, there is a counter defined for the duration of the BIST Carrier Mode 2. To quit this mode correctly (after the tBISTContMode delay), disable the peripheral (UCPDEN = 0).
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXSEND : Command to send a Tx packet The bit is cleared by hardware as soon as the packet transmission begins or is discarded.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXHRST : Command to send a Tx Hard Reset The bit is cleared by hardware as soon as the message transmission begins or is discarded.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXMODE : Receiver mode Determines the mode of the receiver. When the bit is set, RXORDSET behaves normally, RXDR no longer receives bytes yet the CRC checking still proceeds as for a normal message.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PHYRXEN : USB Power Delivery receiver enable Both CC1 and CC2 receivers are disabled when the bit is cleared. Only the CC receiver selected via the PHYCCSEL bit is enabled when the bit is set.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PHYCCSEL : CC1/CC2 line selector for USB Power Delivery signaling The selection depends on the cable orientation as discovered at attach.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ANASUBMODE : Analog PHY sub-mode Refer to TYPEC_VSTATE_CCx for the effect of this bitfield.
bits : 7 - 8 (2 bit)
access : read-write

ANAMODE : Analog PHY operating mode The use of CC1 and CC2 depends on CCENABLE. Refer to ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield in conjunction with ANASUBMODE[1:0].
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CCENABLE : CC line enable This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) according to ANAMODE and ANASUBMODE[1:0] setting. A single line PHY can be enabled when, for example, the other line is driven by VCONN via an external VCONN switch. Enabling both PHYs is the normal usage for sink/source.
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1VCONNEN : VCONN switch enable for CC1
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC2VCONNEN : VCONN switch enable for CC2
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FRSRXEN : FRS event detection enable Setting the bit enables FRS Rx event (FRSEVT) detection on the CC line selected through the PHYCCSEL bit. 0: Disable Clear the bit when the device is attached to an FRS-incapable source/sink.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FRSTX : FRS Tx signaling enable. Setting the bit enables FRS Tx signaling. The bit is cleared by hardware after a delay respecting the USB Power Delivery specification Revision 3.0.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDCH : Rdch condition drive The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit (thus associated with VCONN), by remaining set during the source-only UnattachedWait.SRC state, to respect the Type-C state. Refer to USB Type-C ECN for Source VCONN Discharge . The CCENABLE[1:0] bitfield must be set accordingly, too.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC1TCDIS : CC1 Type-C detector disable The bit disables the Type-C detector on the CC1 line. When enabled, the Type-C detector for CC1 is configured through ANAMODE and ANASUBMODE[1:0].
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC2TCDIS : CC2 Type-C detector disable The bit disables the Type-C detector on the CC2 line. When enabled, the Type-C detector for CC2 is configured through ANAMODE and ANASUBMODE[1:0].
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.