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ADF

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

ADF_GCR

ADF_CKGCR

ADF_SITF0CR

ADF_BSMX0CR

ADF_DFLT0CR

ADF_DFLT0CICR

ADF_DFLT0RSFR

ADF_DLY0CR

ADF_DFLT0IER

ADF_DFLT0ISR

ADF_SADCR

ADF_SADCFGR

ADF_SADSDLVR

ADF_SADANLVR

ADF_DFLT0DR


ADF_GCR

ADF Global Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADF_GCR ADF_GCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGO

TRGO : Trigger output control Set by software and reset by
bits : 0 - 0 (1 bit)


ADF_CKGCR

ADF clock generator control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADF_CKGCR ADF_CKGCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKGDEN CCK0EN CCK1EN CKGMOD CCK0DIR CCK1DIR TRGSENS TRGSRC CCKDIV PROCDIV CKGACTIVE

CKGDEN : CKGEN dividers enable
bits : 0 - 0 (1 bit)

CCK0EN : ADF_CCK0 clock enable
bits : 1 - 1 (1 bit)

CCK1EN : ADF_CCK1 clock enable
bits : 2 - 2 (1 bit)

CKGMOD : Clock generator mode
bits : 4 - 4 (1 bit)

CCK0DIR : ADF_CCK0 direction
bits : 5 - 5 (1 bit)

CCK1DIR : ADF_CCK1 direction
bits : 6 - 6 (1 bit)

TRGSENS : CKGEN trigger sensitivity selection
bits : 8 - 8 (1 bit)

TRGSRC : Digital filter trigger signal selection
bits : 12 - 15 (4 bit)

CCKDIV : Divider to control the ADF_CCK clock
bits : 16 - 19 (4 bit)

PROCDIV : Divider to control the serial interface clock
bits : 24 - 30 (7 bit)

CKGACTIVE : Clock generator active flag
bits : 31 - 31 (1 bit)


ADF_SITF0CR

ADF serial interface control register 0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADF_SITF0CR ADF_SITF0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITFEN SCKSRC SITFMOD STH SITFACTIVE

SITFEN : SITFEN
bits : 0 - 0 (1 bit)

SCKSRC : SCKSRC
bits : 1 - 2 (2 bit)

SITFMOD : SITFMOD
bits : 4 - 5 (2 bit)

STH : STH
bits : 8 - 12 (5 bit)

SITFACTIVE : SITFACTIVE
bits : 31 - 31 (1 bit)


ADF_BSMX0CR

ADF bitstream matrix control register 0
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADF_BSMX0CR ADF_BSMX0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BSSEL BSMXACTIVE

BSSEL : Bitstream selection
bits : 0 - 4 (5 bit)

BSMXACTIVE : BSMX active flag
bits : 31 - 31 (1 bit)


ADF_DFLT0CR

ADF digital filter control register 0
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADF_DFLT0CR ADF_DFLT0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFLTEN DMAEN FTH ACQMOD TRGSRC NBDIS DFLTRUN DFLTACTIVE

DFLTEN : DFLT0 enable
bits : 0 - 0 (1 bit)

DMAEN : DMA requests enable
bits : 1 - 1 (1 bit)

FTH : RXFIFO threshold selection
bits : 2 - 2 (1 bit)

ACQMOD : DFLT0 trigger mode
bits : 4 - 6 (3 bit)

TRGSRC : DFLT0 trigger signal selection
bits : 12 - 15 (4 bit)

NBDIS : Number of samples to be discarded
bits : 20 - 27 (8 bit)

DFLTRUN : DFLT0 run status flag
bits : 30 - 30 (1 bit)

DFLTACTIVE : DFLT0 active flag
bits : 31 - 31 (1 bit)


ADF_DFLT0CICR

ADF digital filer configuration register 0
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADF_DFLT0CICR ADF_DFLT0CICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATSRC CICMOD MCICD SCALE

DATSRC : Source data for the digital filter
bits : 0 - 1 (2 bit)

CICMOD : Select the CIC order
bits : 4 - 6 (3 bit)

MCICD : CIC decimation ratio selection
bits : 8 - 16 (9 bit)

SCALE : Scaling factor selection
bits : 20 - 25 (6 bit)


ADF_DFLT0RSFR

ADF reshape filter configuration register 0
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADF_DFLT0RSFR ADF_DFLT0RSFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSFLTBYP RSFLTD HPFBYP HPFC

RSFLTBYP : Reshaper filter bypass
bits : 0 - 0 (1 bit)

RSFLTD : Reshaper filter decimation ratio
bits : 4 - 4 (1 bit)

HPFBYP : High-pass filter bypass
bits : 7 - 7 (1 bit)

HPFC : High-pass filter cut-off frequency
bits : 8 - 9 (2 bit)


ADF_DLY0CR

ADF delay control register 0
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADF_DLY0CR ADF_DLY0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SKPDLY SKPBF

SKPDLY : Delay to apply to a bitstream
bits : 0 - 6 (7 bit)

SKPBF : Skip busy flag
bits : 31 - 31 (1 bit)


ADF_DFLT0IER

ADF DFLT0 interrupt enable register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADF_DFLT0IER ADF_DFLT0IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTHIE DOVRIE SATIE CKABIE RFOVRIE SDDETIE SDLVLIE

FTHIE : RXFIFO threshold interrupt enable
bits : 0 - 0 (1 bit)

DOVRIE : Data overflow interrupt enable
bits : 1 - 1 (1 bit)

SATIE : Saturation detection interrupt enable
bits : 9 - 9 (1 bit)

CKABIE : Clock absence detection interrupt enable
bits : 10 - 10 (1 bit)

RFOVRIE : Reshape filter overrun interrupt enable
bits : 11 - 11 (1 bit)

SDDETIE : Sound activity detection interrupt enable
bits : 12 - 12 (1 bit)

SDLVLIE : SAD sound-level value ready enable
bits : 13 - 13 (1 bit)


ADF_DFLT0ISR

ADF DFLT0 interrupt status register 0
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADF_DFLT0ISR ADF_DFLT0ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTHF DOVRF RXNEF SATF CKABF RFOVRF SDDETF SDLVLF

FTHF : RXFIFO threshold flag
bits : 0 - 0 (1 bit)
access : read-only

DOVRF : Data overflow flag
bits : 1 - 1 (1 bit)
access : read-write

RXNEF : RXFIFO not empty flag
bits : 3 - 3 (1 bit)
access : read-only

SATF : Saturation detection flag
bits : 9 - 9 (1 bit)
access : read-write

CKABF : Clock absence detection flag
bits : 10 - 10 (1 bit)
access : read-write

RFOVRF : Reshape filter overrun detection flag
bits : 11 - 11 (1 bit)
access : read-write

SDDETF : Sound activity detection flag
bits : 12 - 12 (1 bit)
access : read-write

SDLVLF : Sound level value ready flag
bits : 13 - 13 (1 bit)
access : read-write


ADF_SADCR

ADF SAD control register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADF_SADCR ADF_SADCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SADEN DATCAP DETCFG SADST HYSTEN FRSIZE SADMOD SADACTIVE

SADEN : Sound activity detector enable
bits : 0 - 0 (1 bit)
access : read-write

DATCAP : Data capture mode
bits : 1 - 2 (2 bit)
access : read-write

DETCFG : Sound trigger event configuration
bits : 3 - 3 (1 bit)
access : read-write

SADST : SAD state
bits : 4 - 5 (2 bit)
access : read-only

HYSTEN : Hysteresis enable
bits : 7 - 7 (1 bit)
access : read-write

FRSIZE : Frame size
bits : 8 - 10 (3 bit)
access : read-write

SADMOD : SAD working mode
bits : 12 - 13 (2 bit)
access : read-write

SADACTIVE : SAD Active flag
bits : 31 - 31 (1 bit)
access : read-only


ADF_SADCFGR

ADF SAD configuration register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADF_SADCFGR ADF_SADCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SNTHR ANSLP LFRNB HGOVR ANMIN

SNTHR : SNTHR
bits : 0 - 3 (4 bit)

ANSLP : ANSLP
bits : 4 - 6 (3 bit)

LFRNB : LFRNB
bits : 8 - 10 (3 bit)

HGOVR : Hangover time window
bits : 12 - 14 (3 bit)

ANMIN : ANMIN
bits : 16 - 28 (13 bit)


ADF_SADSDLVR

ADF SAD sound level register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADF_SADSDLVR ADF_SADSDLVR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDLVL

SDLVL : SDLVL
bits : 0 - 14 (15 bit)


ADF_SADANLVR

ADF SAD ambient noise level register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADF_SADANLVR ADF_SADANLVR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ANLVL

ANLVL : ANLVL
bits : 0 - 14 (15 bit)


ADF_DFLT0DR

ADF digital filter data register 0
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADF_DFLT0DR ADF_DFLT0DR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DR

DR : DR
bits : 8 - 31 (24 bit)



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