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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

ADC_ISR

ADC_CFGR2

ADC_SMPR

ADC_AWD1TR

ADC_AWD2TR

ADC_CHSELRMOD0

ADC_CHSELRMOD1

ADC_AWD3TR

ADC_CCR

ADC_IER

ADC_DR

ADC_PWR

ADC_CR

ADC_AWD2CR

ADC_AWD3CR

ADC_CFGR1

ADC_CALFACT

ADC_OR


ADC_ISR

ADC interrupt and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_ISR ADC_ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADRDY EOSMP EOC EOS OVR AWD1 AWD2 AWD3 EOCAL LDORDY

ADRDY : ADRDY
bits : 0 - 0 (1 bit)

EOSMP : EOSMP
bits : 1 - 1 (1 bit)

EOC : EOC
bits : 2 - 2 (1 bit)

EOS : EOS
bits : 3 - 3 (1 bit)

OVR : OVR
bits : 4 - 4 (1 bit)

AWD1 : AWD1
bits : 7 - 7 (1 bit)

AWD2 : AWD2
bits : 8 - 8 (1 bit)

AWD3 : AWD3
bits : 9 - 9 (1 bit)

EOCAL : EOCAL
bits : 11 - 11 (1 bit)

LDORDY : LDORDY
bits : 12 - 12 (1 bit)


ADC_CFGR2

ADC configuration register 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CFGR2 ADC_CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVSE OVSR OVSS TOVS LFTRIG

OVSE : OVSE
bits : 0 - 0 (1 bit)

OVSR : OVSR
bits : 2 - 4 (3 bit)

OVSS : OVSS
bits : 5 - 8 (4 bit)

TOVS : TOVS
bits : 9 - 9 (1 bit)

LFTRIG : LFTRIG
bits : 29 - 29 (1 bit)


ADC_SMPR

ADC sample time register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_SMPR ADC_SMPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMP1 SMP2 SMPSEL0 SMPSEL1 SMPSEL2 SMPSEL3 SMPSEL4 SMPSEL5 SMPSEL6 SMPSEL7 SMPSEL8 SMPSEL9 SMPSEL10 SMPSEL11 SMPSEL12 SMPSEL13 SMPSEL14 SMPSEL15 SMPSEL16 SMPSEL17 SMPSEL18 SMPSEL19 SMPSEL20 SMPSEL21 SMPSEL22 SMPSEL23

SMP1 : SMP1
bits : 0 - 2 (3 bit)

SMP2 : SMP2
bits : 4 - 6 (3 bit)

SMPSEL0 : SMPSEL0
bits : 8 - 8 (1 bit)

SMPSEL1 : SMPSEL1
bits : 9 - 9 (1 bit)

SMPSEL2 : SMPSEL2
bits : 10 - 10 (1 bit)

SMPSEL3 : SMPSEL3
bits : 11 - 11 (1 bit)

SMPSEL4 : SMPSEL4
bits : 12 - 12 (1 bit)

SMPSEL5 : SMPSEL5
bits : 13 - 13 (1 bit)

SMPSEL6 : SMPSEL6
bits : 14 - 14 (1 bit)

SMPSEL7 : SMPSEL7
bits : 15 - 15 (1 bit)

SMPSEL8 : SMPSEL8
bits : 16 - 16 (1 bit)

SMPSEL9 : SMPSEL9
bits : 17 - 17 (1 bit)

SMPSEL10 : SMPSEL10
bits : 18 - 18 (1 bit)

SMPSEL11 : SMPSEL11
bits : 19 - 19 (1 bit)

SMPSEL12 : SMPSEL12
bits : 20 - 20 (1 bit)

SMPSEL13 : SMPSEL13
bits : 21 - 21 (1 bit)

SMPSEL14 : SMPSEL14
bits : 22 - 22 (1 bit)

SMPSEL15 : SMPSEL15
bits : 23 - 23 (1 bit)

SMPSEL16 : SMPSEL16
bits : 24 - 24 (1 bit)

SMPSEL17 : SMPSEL17
bits : 25 - 25 (1 bit)

SMPSEL18 : SMPSEL18
bits : 26 - 26 (1 bit)

SMPSEL19 : SMPSEL19
bits : 27 - 27 (1 bit)

SMPSEL20 : SMPSEL20
bits : 28 - 28 (1 bit)

SMPSEL21 : SMPSEL21
bits : 29 - 29 (1 bit)

SMPSEL22 : SMPSEL22
bits : 30 - 30 (1 bit)

SMPSEL23 : SMPSEL23
bits : 31 - 31 (1 bit)


ADC_AWD1TR

ADC watchdog threshold register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_AWD1TR ADC_AWD1TR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LT1 HT1

LT1 : LT1
bits : 0 - 11 (12 bit)

HT1 : HT1
bits : 16 - 27 (12 bit)


ADC_AWD2TR

ADC watchdog threshold register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_AWD2TR ADC_AWD2TR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LT2 HT2

LT2 : LT2
bits : 0 - 11 (12 bit)

HT2 : HT2
bits : 16 - 27 (12 bit)


ADC_CHSELRMOD0

ADC channel selection register [alternate]
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CHSELRMOD0 ADC_CHSELRMOD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHSEL

CHSEL : CHSEL
bits : 0 - 23 (24 bit)


ADC_CHSELRMOD1

ADC channel selection register [alternate]
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : ADC_CHSELRMOD0
reset_Mask : 0x0

ADC_CHSELRMOD1 ADC_CHSELRMOD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ1 SQ2 SQ3 SQ4 SQ5 SQ6 SQ7 SQ8

SQ1 : SQ1
bits : 0 - 3 (4 bit)

SQ2 : SQ2
bits : 4 - 7 (4 bit)

SQ3 : SQ3
bits : 8 - 11 (4 bit)

SQ4 : SQ4
bits : 12 - 15 (4 bit)

SQ5 : SQ5
bits : 16 - 19 (4 bit)

SQ6 : SQ6
bits : 20 - 23 (4 bit)

SQ7 : SQ7
bits : 24 - 27 (4 bit)

SQ8 : SQ8
bits : 28 - 31 (4 bit)


ADC_AWD3TR

ADC watchdog threshold register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_AWD3TR ADC_AWD3TR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LT3 HT3

LT3 : LT3
bits : 0 - 11 (12 bit)

HT3 : HT3
bits : 16 - 27 (12 bit)


ADC_CCR

ADC common configuration register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CCR ADC_CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESC VREFEN VSENSESEL VBATEN

PRESC : PRESC
bits : 18 - 21 (4 bit)

VREFEN : VREFEN
bits : 22 - 22 (1 bit)

VSENSESEL : VSENSESEL
bits : 23 - 23 (1 bit)

VBATEN : VBATEN
bits : 24 - 24 (1 bit)


ADC_IER

ADC interrupt enable register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_IER ADC_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADRDYIE EOSMPIE EOCIE EOSIE OVRIE AWD1IE AWD2IE AWD3IE EOCALIE LDORDYIE

ADRDYIE : ADRDYIE
bits : 0 - 0 (1 bit)

EOSMPIE : EOSMPIE
bits : 1 - 1 (1 bit)

EOCIE : EOCIE
bits : 2 - 2 (1 bit)

EOSIE : EOSIE
bits : 3 - 3 (1 bit)

OVRIE : OVRIE
bits : 4 - 4 (1 bit)

AWD1IE : AWD1IE
bits : 7 - 7 (1 bit)

AWD2IE : AWD2IE
bits : 8 - 8 (1 bit)

AWD3IE : AWD3IE
bits : 9 - 9 (1 bit)

EOCALIE : EOCALIE
bits : 11 - 11 (1 bit)

LDORDYIE : LDORDYIE
bits : 12 - 12 (1 bit)


ADC_DR

ADC data register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADC_DR ADC_DR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA
bits : 0 - 15 (16 bit)


ADC_PWR

ADC data register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_PWR ADC_PWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUTOFF DPD VREFPROT VREFSECSMP

AUTOFF : AUTOFF
bits : 0 - 0 (1 bit)

DPD : DPD
bits : 1 - 1 (1 bit)

VREFPROT : VREFPROT
bits : 2 - 2 (1 bit)

VREFSECSMP : VREFSECSMP
bits : 3 - 3 (1 bit)


ADC_CR

ADC control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CR ADC_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADEN ADDIS ADSTART ADSTP ADVREGEN ADCAL

ADEN : ADEN
bits : 0 - 0 (1 bit)
access : read-only

ADDIS : ADDIS
bits : 1 - 1 (1 bit)
access : read-only

ADSTART : ADSTART
bits : 2 - 2 (1 bit)
access : read-only

ADSTP : ADSTP
bits : 4 - 4 (1 bit)
access : read-only

ADVREGEN : ADVREGEN
bits : 28 - 28 (1 bit)
access : read-write

ADCAL : ADCAL
bits : 31 - 31 (1 bit)
access : read-only


ADC_AWD2CR

ADC Analog Watchdog 2 Configuration register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_AWD2CR ADC_AWD2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD2CH0 AWD2CH1 AWD2CH2 AWD2CH3 AWD2CH4 AWD2CH5 AWD2CH6 AWD2CH7 AWD2CH8 AWD2CH9 AWD2CH10 AWD2CH11 AWD2CH12 AWD2CH13 AWD2CH14 AWD2CH15 AWD2CH16 AWD2CH17 AWD2CH18 AWD2CH19 AWD2CH20 AWD2CH21 AWD2CH22 AWD2CH23

AWD2CH0 : AWD2CH0
bits : 0 - 0 (1 bit)

AWD2CH1 : AWD2CH1
bits : 1 - 1 (1 bit)

AWD2CH2 : AWD2CH2
bits : 2 - 2 (1 bit)

AWD2CH3 : AWD2CH3
bits : 3 - 3 (1 bit)

AWD2CH4 : AWD2CH4
bits : 4 - 4 (1 bit)

AWD2CH5 : AWD2CH5
bits : 5 - 5 (1 bit)

AWD2CH6 : AWD2CH6
bits : 6 - 6 (1 bit)

AWD2CH7 : AWD2CH7
bits : 7 - 7 (1 bit)

AWD2CH8 : AWD2CH8
bits : 8 - 8 (1 bit)

AWD2CH9 : AWD2CH9
bits : 9 - 9 (1 bit)

AWD2CH10 : AWD2CH10
bits : 10 - 10 (1 bit)

AWD2CH11 : AWD2CH11
bits : 11 - 11 (1 bit)

AWD2CH12 : AWD2CH12
bits : 12 - 12 (1 bit)

AWD2CH13 : AWD2CH13
bits : 13 - 13 (1 bit)

AWD2CH14 : AWD2CH14
bits : 14 - 14 (1 bit)

AWD2CH15 : AWD2CH15
bits : 15 - 15 (1 bit)

AWD2CH16 : AWD2CH16
bits : 16 - 16 (1 bit)

AWD2CH17 : AWD2CH17
bits : 17 - 17 (1 bit)

AWD2CH18 : AWD2CH18
bits : 18 - 18 (1 bit)

AWD2CH19 : AWD2CH19
bits : 19 - 19 (1 bit)

AWD2CH20 : AWD2CH20
bits : 20 - 20 (1 bit)

AWD2CH21 : AWD2CH21
bits : 21 - 21 (1 bit)

AWD2CH22 : AWD2CH22
bits : 22 - 22 (1 bit)

AWD2CH23 : AWD2CH23
bits : 23 - 23 (1 bit)


ADC_AWD3CR

ADC Analog Watchdog 3 Configuration register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_AWD3CR ADC_AWD3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD3CH0 AWD3CH1 AWD3CH2 AWD3CH3 AWD3CH4 AWD3CH5 AWD3CH6 AWD3CH7 AWD3CH8 AWD3CH9 AWD3CH10 AWD3CH11 AWD3CH12 AWD3CH13 AWD3CH14 AWD3CH15 AWD3CH16 AWD3CH17 AWD3CH18 AWD3CH19 AWD3CH20 AWD3CH21 AWD3CH22 AWD3CH23

AWD3CH0 : AWD3CH0
bits : 0 - 0 (1 bit)

AWD3CH1 : AWD3CH1
bits : 1 - 1 (1 bit)

AWD3CH2 : AWD3CH2
bits : 2 - 2 (1 bit)

AWD3CH3 : AWD3CH3
bits : 3 - 3 (1 bit)

AWD3CH4 : AWD3CH4
bits : 4 - 4 (1 bit)

AWD3CH5 : AWD3CH5
bits : 5 - 5 (1 bit)

AWD3CH6 : AWD3CH6
bits : 6 - 6 (1 bit)

AWD3CH7 : AWD3CH7
bits : 7 - 7 (1 bit)

AWD3CH8 : AWD3CH8
bits : 8 - 8 (1 bit)

AWD3CH9 : AWD3CH9
bits : 9 - 9 (1 bit)

AWD3CH10 : AWD3CH10
bits : 10 - 10 (1 bit)

AWD3CH11 : AWD3CH11
bits : 11 - 11 (1 bit)

AWD3CH12 : AWD3CH12
bits : 12 - 12 (1 bit)

AWD3CH13 : AWD3CH13
bits : 13 - 13 (1 bit)

AWD3CH14 : AWD3CH14
bits : 14 - 14 (1 bit)

AWD3CH15 : AWD3CH15
bits : 15 - 15 (1 bit)

AWD3CH16 : AWD3CH16
bits : 16 - 16 (1 bit)

AWD3CH17 : AWD3CH17
bits : 17 - 17 (1 bit)

AWD3CH18 : AWD3CH18
bits : 18 - 18 (1 bit)

AWD3CH19 : AWD3CH19
bits : 19 - 19 (1 bit)

AWD3CH20 : AWD3CH20
bits : 20 - 20 (1 bit)

AWD3CH21 : AWD3CH21
bits : 21 - 21 (1 bit)

AWD3CH22 : AWD3CH22
bits : 22 - 22 (1 bit)

AWD3CH23 : AWD3CH23
bits : 23 - 23 (1 bit)


ADC_CFGR1

ADC configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CFGR1 ADC_CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAEN DMACFG RES SCANDIR ALIGN EXTSEL EXTEN OVRMOD CONT WAIT DISCEN CHSELRMOD AWD1SGL AWD1EN AWD1CH

DMAEN : DMAEN
bits : 0 - 0 (1 bit)

DMACFG : DMACFG
bits : 1 - 1 (1 bit)

RES : RES
bits : 2 - 3 (2 bit)

SCANDIR : SCANDIR
bits : 4 - 4 (1 bit)

ALIGN : ALIGN
bits : 5 - 5 (1 bit)

EXTSEL : EXTSEL
bits : 6 - 8 (3 bit)

EXTEN : EXTEN
bits : 10 - 11 (2 bit)

OVRMOD : OVRMOD
bits : 12 - 12 (1 bit)

CONT : CONT
bits : 13 - 13 (1 bit)

WAIT : WAIT
bits : 14 - 14 (1 bit)

DISCEN : DISCEN
bits : 16 - 16 (1 bit)

CHSELRMOD : CHSELRMOD
bits : 21 - 21 (1 bit)

AWD1SGL : AWD1SGL
bits : 22 - 22 (1 bit)

AWD1EN : AWD1EN
bits : 23 - 23 (1 bit)

AWD1CH : AWD1CH
bits : 26 - 30 (5 bit)


ADC_CALFACT

ADC Calibration factor
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CALFACT ADC_CALFACT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALFACT

CALFACT : CALFACT
bits : 0 - 6 (7 bit)


ADC_OR

ADC option register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OR ADC_OR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHN21SEL

CHN21SEL : CHN21SEL
bits : 0 - 0 (1 bit)



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