Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
SRAM/NOR-Flash chip-select control register for bank 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MBKEN : Memory bank enable bit
bits : 0 - 0 (1 bit)
MUXEN : Address/data multiplexing enable bit
bits : 1 - 1 (1 bit)
MTYP : Memory type
bits : 2 - 3 (2 bit)
MWID : Memory data bus width
bits : 4 - 5 (2 bit)
FACCEN : Flash access enable
bits : 6 - 6 (1 bit)
BURSTEN : Burst enable bit
bits : 8 - 8 (1 bit)
WAITPOL : Wait signal polarity bit
bits : 9 - 9 (1 bit)
WAITCFG : Wait timing configuration
bits : 11 - 11 (1 bit)
WREN : Write enable bit
bits : 12 - 12 (1 bit)
WAITEN : Wait enable bit
bits : 13 - 13 (1 bit)
EXTMOD : Extended mode enable
bits : 14 - 14 (1 bit)
ASYNCWAIT : Wait signal during asynchronous transfers
bits : 15 - 15 (1 bit)
CPSIZE : CRAM Page Size
bits : 16 - 18 (3 bit)
CBURSTRW : Write burst enable
bits : 19 - 19 (1 bit)
CCLKEN : Continuous clock enable
bits : 20 - 20 (1 bit)
WFDIS : Write FIFO disable
bits : 21 - 21 (1 bit)
NBLSET : Byte lane (NBL) setup
bits : 22 - 23 (2 bit)
FMCEN : FMC controller enable
bits : 31 - 31 (1 bit)
SRAM/NOR-Flash chip-select control register for bank 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MBKEN : Memory bank enable bit
bits : 0 - 0 (1 bit)
MUXEN : Address/data multiplexing enable bit
bits : 1 - 1 (1 bit)
MTYP : Memory type
bits : 2 - 3 (2 bit)
MWID : Memory data bus width
bits : 4 - 5 (2 bit)
FACCEN : Flash access enable
bits : 6 - 6 (1 bit)
BURSTEN : Burst enable bit
bits : 8 - 8 (1 bit)
WAITPOL : Wait signal polarity bit
bits : 9 - 9 (1 bit)
WAITCFG : Wait timing configuration
bits : 11 - 11 (1 bit)
WREN : Write enable bit
bits : 12 - 12 (1 bit)
WAITEN : Wait enable bit
bits : 13 - 13 (1 bit)
EXTMOD : Extended mode enable
bits : 14 - 14 (1 bit)
ASYNCWAIT : Wait signal during asynchronous transfers
bits : 15 - 15 (1 bit)
CPSIZE : CRAM Page Size
bits : 16 - 18 (3 bit)
CBURSTRW : Write burst enable
bits : 19 - 19 (1 bit)
CCLKEN : Continuous clock enable
bits : 20 - 20 (1 bit)
WFDIS : Write FIFO disable
bits : 21 - 21 (1 bit)
NBLSET : Byte lane (NBL) setup
bits : 22 - 23 (2 bit)
FMCEN : FMC controller enable
bits : 31 - 31 (1 bit)
SRAM/NOR-Flash write timing registers 1
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDSET : Address setup phase duration
bits : 0 - 3 (4 bit)
ADDHLD : Address-hold phase duration
bits : 4 - 7 (4 bit)
DATAST : Data-phase duration
bits : 8 - 15 (8 bit)
BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)
ACCMOD : Access mode
bits : 28 - 29 (2 bit)
DATAHLD : Data hold phase duration
bits : 30 - 31 (2 bit)
SRAM/NOR-Flash write timing registers 2
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDSET : Address setup phase duration
bits : 0 - 3 (4 bit)
ADDHLD : Address-hold phase duration
bits : 4 - 7 (4 bit)
DATAST : Data-phase duration
bits : 8 - 15 (8 bit)
BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)
ACCMOD : Access mode
bits : 28 - 29 (2 bit)
DATAHLD : Data hold phase duration
bits : 30 - 31 (2 bit)
SRAM/NOR-Flash write timing registers 3
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDSET : Address setup phase duration
bits : 0 - 3 (4 bit)
ADDHLD : Address-hold phase duration
bits : 4 - 7 (4 bit)
DATAST : Data-phase duration
bits : 8 - 15 (8 bit)
BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)
ACCMOD : Access mode
bits : 28 - 29 (2 bit)
DATAHLD : Data hold phase duration
bits : 30 - 31 (2 bit)
SRAM/NOR-Flash write timing registers 4
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDSET : Address setup phase duration
bits : 0 - 3 (4 bit)
ADDHLD : Address-hold phase duration
bits : 4 - 7 (4 bit)
DATAST : Data-phase duration
bits : 8 - 15 (8 bit)
BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)
ACCMOD : Access mode
bits : 28 - 29 (2 bit)
DATAHLD : Data hold phase duration
bits : 30 - 31 (2 bit)
SRAM/NOR-Flash chip-select timing register for bank 3
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDSET : Address setup phase duration
bits : 0 - 3 (4 bit)
ADDHLD : Address-hold phase duration
bits : 4 - 7 (4 bit)
DATAST : Data-phase duration
bits : 8 - 15 (8 bit)
BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)
CLKDIV : Clock divide ratio (for FMC_CLK signal)
bits : 20 - 23 (4 bit)
DATLAT : Data latency for synchronous memory
bits : 24 - 27 (4 bit)
ACCMOD : Access mode
bits : 28 - 29 (2 bit)
DATAHLD : Data hold phase duration
bits : 30 - 31 (2 bit)
SRAM/NOR-Flash chip-select control register for bank 4
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MBKEN : Memory bank enable bit
bits : 0 - 0 (1 bit)
MUXEN : Address/data multiplexing enable bit
bits : 1 - 1 (1 bit)
MTYP : Memory type
bits : 2 - 3 (2 bit)
MWID : Memory data bus width
bits : 4 - 5 (2 bit)
FACCEN : Flash access enable
bits : 6 - 6 (1 bit)
BURSTEN : Burst enable bit
bits : 8 - 8 (1 bit)
WAITPOL : Wait signal polarity bit
bits : 9 - 9 (1 bit)
WAITCFG : Wait timing configuration
bits : 11 - 11 (1 bit)
WREN : Write enable bit
bits : 12 - 12 (1 bit)
WAITEN : Wait enable bit
bits : 13 - 13 (1 bit)
EXTMOD : Extended mode enable
bits : 14 - 14 (1 bit)
ASYNCWAIT : Wait signal during asynchronous transfers
bits : 15 - 15 (1 bit)
CPSIZE : CRAM Page Size
bits : 16 - 18 (3 bit)
CBURSTRW : Write burst enable
bits : 19 - 19 (1 bit)
CCLKEN : Continuous clock enable
bits : 20 - 20 (1 bit)
WFDIS : Write FIFO disable
bits : 21 - 21 (1 bit)
NBLSET : Byte lane (NBL) setup
bits : 22 - 23 (2 bit)
FMCEN : FMC controller enable
bits : 31 - 31 (1 bit)
SRAM/NOR-Flash chip-select timing register for bank 4
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDSET : Address setup phase duration
bits : 0 - 3 (4 bit)
ADDHLD : Address-hold phase duration
bits : 4 - 7 (4 bit)
DATAST : Data-phase duration
bits : 8 - 15 (8 bit)
BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)
CLKDIV : Clock divide ratio (for FMC_CLK signal)
bits : 20 - 23 (4 bit)
DATLAT : Data latency for synchronous memory
bits : 24 - 27 (4 bit)
ACCMOD : Access mode
bits : 28 - 29 (2 bit)
DATAHLD : Data hold phase duration
bits : 30 - 31 (2 bit)
PSRAM chip select counter register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSCOUNT : Chip select counter
bits : 0 - 15 (16 bit)
CNTB1EN : Counter Bank 1 enable
bits : 16 - 16 (1 bit)
CNTB2EN : Counter Bank 2 enable
bits : 17 - 17 (1 bit)
CNTB3EN : Counter Bank 3 enable
bits : 18 - 18 (1 bit)
CNTB4EN : Counter Bank 4 enable
bits : 19 - 19 (1 bit)
SRAM/NOR-Flash chip-select timing register for bank 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDSET : Address setup phase duration
bits : 0 - 3 (4 bit)
ADDHLD : Address-hold phase duration
bits : 4 - 7 (4 bit)
DATAST : Data-phase duration
bits : 8 - 15 (8 bit)
BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)
CLKDIV : Clock divide ratio (for FMC_CLK signal)
bits : 20 - 23 (4 bit)
DATLAT : Data latency for synchronous memory
bits : 24 - 27 (4 bit)
ACCMOD : Access mode
bits : 28 - 29 (2 bit)
DATAHLD : Data hold phase duration
bits : 30 - 31 (2 bit)
SRAM/NOR-Flash chip-select control register for bank 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MBKEN : Memory bank enable bit
bits : 0 - 0 (1 bit)
MUXEN : Address/data multiplexing enable bit
bits : 1 - 1 (1 bit)
MTYP : Memory type
bits : 2 - 3 (2 bit)
MWID : Memory data bus width
bits : 4 - 5 (2 bit)
FACCEN : Flash access enable
bits : 6 - 6 (1 bit)
BURSTEN : Burst enable bit
bits : 8 - 8 (1 bit)
WAITPOL : Wait signal polarity bit
bits : 9 - 9 (1 bit)
WAITCFG : Wait timing configuration
bits : 11 - 11 (1 bit)
WREN : Write enable bit
bits : 12 - 12 (1 bit)
WAITEN : Wait enable bit
bits : 13 - 13 (1 bit)
EXTMOD : Extended mode enable
bits : 14 - 14 (1 bit)
ASYNCWAIT : Wait signal during asynchronous transfers
bits : 15 - 15 (1 bit)
CPSIZE : CRAM Page Size
bits : 16 - 18 (3 bit)
CBURSTRW : Write burst enable
bits : 19 - 19 (1 bit)
CCLKEN : Continuous clock enable
bits : 20 - 20 (1 bit)
WFDIS : Write FIFO disable
bits : 21 - 21 (1 bit)
NBLSET : Byte lane (NBL) setup
bits : 22 - 23 (2 bit)
FMCEN : FMC controller enable
bits : 31 - 31 (1 bit)
NAND Flash control registers
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWAITEN : Wait feature enable bit
bits : 1 - 1 (1 bit)
PBKEN : NAND Flash memory bank enable bit
bits : 2 - 2 (1 bit)
PTYP : Memory type
bits : 3 - 3 (1 bit)
PWID : Data bus width
bits : 4 - 5 (2 bit)
ECCEN : ECC computation logic enable bit
bits : 6 - 6 (1 bit)
TCLR : CLE to RE delay
bits : 9 - 12 (4 bit)
TAR : ALE to RE delay
bits : 13 - 15 (3 bit)
ECCPS : ECC page size
bits : 17 - 19 (3 bit)
status and interrupt register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRS : Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set.
bits : 0 - 0 (1 bit)
access : read-write
ILS : Interrupt high-level status The flag is set by hardware and reset by software.
bits : 1 - 1 (1 bit)
access : read-write
IFS : Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set.
bits : 2 - 2 (1 bit)
access : read-write
IREN : Interrupt rising edge detection enable bit
bits : 3 - 3 (1 bit)
access : read-write
ILEN : Interrupt high-level detection enable bit
bits : 4 - 4 (1 bit)
access : read-write
IFEN : Interrupt falling edge detection enable bit
bits : 5 - 5 (1 bit)
access : read-write
FEMPT : FIFO empty. Read-only bit that provides the status of the FIFO
bits : 6 - 6 (1 bit)
access : read-only
Common memory space timing register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMSET : Common memory x setup time These bits define the number of KCK_FMC (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space:
bits : 0 - 7 (8 bit)
MEMWAIT : Common memory wait time These bits define the minimum number of KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC:
bits : 8 - 15 (8 bit)
MEMHOLD : Common memory hold time These bits define the number of KCK_FMC clock cycles for write accesses and KCK_FMC+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is de-asserted (NWE, NOE), for NAND Flash read or write access to common memory space:
bits : 16 - 23 (8 bit)
MEMHIZ : Common memory x data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space. This is only valid for write transactions:
bits : 24 - 31 (8 bit)
The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature).
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATTSET : Attribute memory setup time These bits define the number of KCK_FMC (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space:
bits : 0 - 7 (8 bit)
ATTWAIT : Attribute memory wait time These bits define the minimum number of x KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC:
bits : 8 - 15 (8 bit)
ATTHOLD : Attribute memory hold time These bits define the number of KCK_FMC clock cycles during which the address is held (and data for write access) after the command de-assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space:
bits : 16 - 23 (8 bit)
ATTHIZ : Attribute memory data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction:
bits : 24 - 31 (8 bit)
This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ECC : ECC result This field contains the value computed by the ECC computation logic. Table167 describes the contents of these bit fields.
bits : 0 - 31 (32 bit)
SRAM/NOR-Flash chip-select timing register for bank 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDSET : Address setup phase duration
bits : 0 - 3 (4 bit)
ADDHLD : Address-hold phase duration
bits : 4 - 7 (4 bit)
DATAST : Data-phase duration
bits : 8 - 15 (8 bit)
BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)
CLKDIV : Clock divide ratio (for FMC_CLK signal)
bits : 20 - 23 (4 bit)
DATLAT : Data latency for synchronous memory
bits : 24 - 27 (4 bit)
ACCMOD : Access mode
bits : 28 - 29 (2 bit)
DATAHLD : Data hold phase duration
bits : 30 - 31 (2 bit)
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