\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RNGEN : True random number generator enable
bits : 2 - 2 (1 bit)
IE : Interrupt Enable
bits : 3 - 3 (1 bit)
CED : Clock error detection
bits : 5 - 5 (1 bit)
ARDIS : Auto reset disable
bits : 7 - 7 (1 bit)
RNG_CONFIG3 : RNG configuration 3
bits : 8 - 11 (4 bit)
NISTC : Non NIST compliant
bits : 12 - 12 (1 bit)
RNG_CONFIG2 : RNG configuration 2
bits : 13 - 15 (3 bit)
CLKDIV : Clock divider factor
bits : 16 - 19 (4 bit)
RNG_CONFIG1 : RNG configuration 1
bits : 20 - 25 (6 bit)
CONDRST : Conditioning soft reset
bits : 30 - 30 (1 bit)
CONFIGLOCK : RNG Config Lock
bits : 31 - 31 (1 bit)
health test control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTCFG : health test configuration
bits : 0 - 31 (32 bit)
status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRDY : Data ready
bits : 0 - 0 (1 bit)
access : read-only
CECS : Clock error current status
bits : 1 - 1 (1 bit)
access : read-only
SECS : Seed error current status
bits : 2 - 2 (1 bit)
access : read-only
CEIS : Clock error interrupt status
bits : 5 - 5 (1 bit)
access : read-write
SEIS : Seed error interrupt status
bits : 6 - 6 (1 bit)
access : read-write
data register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RNDATA : Random data
bits : 0 - 31 (32 bit)
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