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FMAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

X1BUFCFG

CR

SR

WDATA

RDATA

X2BUFCFG

YBUFCFG

PARAM


X1BUFCFG

FMAC X1 Buffer Configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

X1BUFCFG X1BUFCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1_BASE X1_BUF_SIZE FULL_WM

X1_BASE : Base address of X1 buffer
bits : 0 - 7 (8 bit)

X1_BUF_SIZE : Allocated size of X1 buffer in 16-bit words
bits : 8 - 15 (8 bit)

FULL_WM : Watermark for buffer full flag
bits : 24 - 25 (2 bit)


CR

FMAC Control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RIEN WIEN OVFLIEN UNFLIEN SATIEN DMAREN DMAWEN CLIPEN RESET

RIEN : Enable read interrupt
bits : 0 - 0 (1 bit)

WIEN : Enable write interrupt
bits : 1 - 1 (1 bit)

OVFLIEN : Enable overflow error interrupts
bits : 2 - 2 (1 bit)

UNFLIEN : Enable underflow error interrupts
bits : 3 - 3 (1 bit)

SATIEN : Enable saturation error interrupts
bits : 4 - 4 (1 bit)

DMAREN : Enable DMA read channel requests
bits : 8 - 8 (1 bit)

DMAWEN : Enable DMA write channel requests
bits : 9 - 9 (1 bit)

CLIPEN : Enable clipping
bits : 15 - 15 (1 bit)

RESET : Reset FMAC unit
bits : 16 - 16 (1 bit)


SR

FMAC Status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 YEMPTY X1FULL OVFL UNFL SAT

YEMPTY : Y buffer empty flag
bits : 0 - 0 (1 bit)

X1FULL : X1 buffer full flag
bits : 1 - 1 (1 bit)

OVFL : Overflow error flag
bits : 8 - 8 (1 bit)

UNFL : Underflow error flag
bits : 9 - 9 (1 bit)

SAT : Saturation error flag
bits : 10 - 10 (1 bit)


WDATA

FMAC Write Data register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

WDATA WDATA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : Write data
bits : 0 - 15 (16 bit)


RDATA

FMAC Read Data register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RDATA RDATA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATA

RDATA : Read data
bits : 0 - 15 (16 bit)


X2BUFCFG

FMAC X2 Buffer Configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

X2BUFCFG X2BUFCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X2_BASE X2_BUF_SIZE

X2_BASE : Base address of X2 buffer
bits : 0 - 7 (8 bit)

X2_BUF_SIZE : Size of X2 buffer in 16-bit words
bits : 8 - 15 (8 bit)


YBUFCFG

FMAC Y Buffer Configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

YBUFCFG YBUFCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Y_BASE Y_BUF_SIZE EMPTY_WM

Y_BASE : Base address of Y buffer
bits : 0 - 7 (8 bit)

Y_BUF_SIZE : Size of Y buffer in 16-bit words
bits : 8 - 15 (8 bit)

EMPTY_WM : Watermark for buffer empty flag
bits : 24 - 25 (2 bit)


PARAM

FMAC Parameter register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PARAM PARAM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P Q R FUNC START

P : Input parameter P
bits : 0 - 7 (8 bit)

Q : Input parameter Q
bits : 8 - 15 (8 bit)

R : Input parameter R
bits : 16 - 23 (8 bit)

FUNC : Function
bits : 24 - 30 (7 bit)

START : Enable execution
bits : 31 - 31 (1 bit)



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