\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
DAC control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN1 : DAC channel1 enable
bits : 0 - 0 (1 bit)
TEN1 : DAC channel1 trigger enable
bits : 1 - 1 (1 bit)
TSEL1 : DAC channel1 trigger selection
bits : 2 - 5 (4 bit)
WAVE1 : DAC channel1 noise/triangle wave generation enable
bits : 6 - 7 (2 bit)
MAMP1 : DAC channel1 mask/amplitude selector
bits : 8 - 11 (4 bit)
DMAEN1 : DAC channel1 DMA enable
bits : 12 - 12 (1 bit)
DMAUDRIE1 : DAC channel1 DMA Underrun Interrupt enable
bits : 13 - 13 (1 bit)
CEN1 : DAC channel1 calibration enable
bits : 14 - 14 (1 bit)
EN2 : DAC channel2 enable
bits : 16 - 16 (1 bit)
TEN2 : DAC channel2 trigger enable
bits : 17 - 17 (1 bit)
TSEL2 : DAC channel2 trigger selection
bits : 18 - 21 (4 bit)
WAVE2 : DAC channel2 noise/triangle wave generation enable
bits : 22 - 23 (2 bit)
MAMP2 : DAC channel2 mask/amplitude selector
bits : 24 - 27 (4 bit)
DMAEN2 : DAC channel2 DMA enable
bits : 28 - 28 (1 bit)
DMAUDRIE2 : DAC channel2 DMA underrun interrupt enable
bits : 29 - 29 (1 bit)
CEN2 : DAC channel2 calibration enable
bits : 30 - 30 (1 bit)
DAC channel1 8-bit right aligned data holding register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 8-bit right-aligned data
bits : 0 - 7 (8 bit)
DACC1DHRB : DAC channel1 8-bit right-aligned Sdata
bits : 8 - 15 (8 bit)
DAC channel2 12-bit right aligned data holding register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC2DHR : DAC channel2 12-bit right-aligned data
bits : 0 - 11 (12 bit)
DACC2DHRB : DAC channel2 12-bit right-aligned data
bits : 16 - 27 (12 bit)
DAC channel2 12-bit left aligned data holding register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC2DHR : DAC channel2 12-bit left-aligned data
bits : 4 - 15 (12 bit)
DACC2DHRB : DAC channel2 12-bit left-aligned data B
bits : 20 - 31 (12 bit)
DAC channel2 8-bit right-aligned data holding register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC2DHR : DAC channel2 8-bit right-aligned data
bits : 0 - 7 (8 bit)
DACC2DHRB : DAC channel2 8-bit right-aligned data
bits : 8 - 15 (8 bit)
Dual DAC 12-bit right-aligned data holding register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 12-bit right-aligned data
bits : 0 - 11 (12 bit)
DACC2DHR : DAC channel2 12-bit right-aligned data
bits : 16 - 27 (12 bit)
DUAL DAC 12-bit left aligned data holding register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 12-bit left-aligned data
bits : 4 - 15 (12 bit)
DACC2DHR : DAC channel2 12-bit left-aligned data
bits : 20 - 31 (12 bit)
DUAL DAC 8-bit right aligned data holding register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 8-bit right-aligned data
bits : 0 - 7 (8 bit)
DACC2DHR : DAC channel2 8-bit right-aligned data
bits : 8 - 15 (8 bit)
DAC channel1 data output register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DACC1DOR : DAC channel1 data output
bits : 0 - 11 (12 bit)
DACC1DORB : DAC channel1 data output
bits : 16 - 27 (12 bit)
DAC channel2 data output register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DACC2DOR : DAC channel2 data output
bits : 0 - 11 (12 bit)
DACC2DORB : DAC channel2 data output
bits : 16 - 27 (12 bit)
DAC status register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAC1RDY : DAC channel1 ready status bit
bits : 11 - 11 (1 bit)
access : read-only
DORSTAT1 : DAC channel1 output register status bit
bits : 12 - 12 (1 bit)
access : read-only
DMAUDR1 : DAC channel1 DMA underrun flag
bits : 13 - 13 (1 bit)
access : read-write
CAL_FLAG1 : DAC Channel 1 calibration offset status
bits : 14 - 14 (1 bit)
access : read-only
BWST1 : DAC Channel 1 busy writing sample time flag
bits : 15 - 15 (1 bit)
access : read-only
DAC2RDY : DAC channel 2 ready status bit
bits : 27 - 27 (1 bit)
access : read-only
DORSTAT2 : DAC channel 2 output register status bit
bits : 28 - 28 (1 bit)
access : read-only
DMAUDR2 : DAC channel2 DMA underrun flag
bits : 29 - 29 (1 bit)
access : read-write
CAL_FLAG2 : DAC Channel 2 calibration offset status
bits : 30 - 30 (1 bit)
access : read-only
BWST2 : DAC Channel 2 busy writing sample time flag
bits : 31 - 31 (1 bit)
access : read-only
DAC calibration control register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OTRIM1 : DAC Channel 1 offset trimming value
bits : 0 - 4 (5 bit)
OTRIM2 : DAC Channel 2 offset trimming value
bits : 16 - 20 (5 bit)
DAC mode control register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE1 : DAC Channel 1 mode
bits : 0 - 2 (3 bit)
DMADOUBLE1 : DAC Channel1 DMA double data mode
bits : 8 - 8 (1 bit)
SINFORMAT1 : Enable signed format for DAC channel1
bits : 9 - 9 (1 bit)
HFSEL : High frequency interface mode selection
bits : 14 - 15 (2 bit)
MODE2 : DAC Channel 2 mode
bits : 16 - 18 (3 bit)
DMADOUBLE2 : DAC Channel2 DMA double data mode
bits : 24 - 24 (1 bit)
SINFORMAT2 : Enable signed format for DAC channel2
bits : 25 - 25 (1 bit)
DAC software trigger register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWTRIG1 : DAC channel1 software trigger
bits : 0 - 0 (1 bit)
SWTRIG2 : DAC channel2 software trigger
bits : 1 - 1 (1 bit)
DAC Sample and Hold sample time register 1
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSAMPLE1 : DAC Channel 1 sample Time (only valid in sample and amp hold mode)
bits : 0 - 9 (10 bit)
DAC channel2 sample and hold sample time register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSAMPLE2 : DAC Channel 2 sample Time (only valid in sample and hold mode)
bits : 0 - 9 (10 bit)
DAC Sample and Hold hold time register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THOLD1 : DAC Channel 1 hold Time (only valid in sample and hold mode)
bits : 0 - 9 (10 bit)
THOLD2 : DAC Channel 2 hold time (only valid in sample and hold mode)
bits : 16 - 25 (10 bit)
DAC Sample and Hold refresh time register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TREFRESH1 : DAC Channel 1 refresh Time (only valid in sample and hold mode)
bits : 0 - 7 (8 bit)
TREFRESH2 : DAC Channel 2 refresh Time (only valid in sample and hold mode)
bits : 16 - 23 (8 bit)
Autonomous mode control register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTOMODE : DAC Autonomous mode
bits : 22 - 22 (1 bit)
DAC channel1 12-bit right-aligned data holding register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 12-bit right-aligned data
bits : 0 - 11 (12 bit)
DACC1DHRB : DAC channel1 12-bit right-aligned data B
bits : 16 - 27 (12 bit)
DAC channel1 12-bit left aligned data holding register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 12-bit left-aligned data
bits : 4 - 15 (12 bit)
DACC1DHRB : DAC channel1 12-bit left-aligned data B
bits : 20 - 31 (12 bit)
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