POWER

RESPCMD (RESPCMDR)

RESP1

RESP2

RESP3

RESP4

DTIMER

DLENR

DCTRL

DCNTR

STAR

ICR

MASKR

CLKCR

ACKTIMER

SDMMC_IDMACTRLR

SDMMC_IDMABSIZER

SDMMC_IDMABASER

SDMMC_IDMALAR

SDMMC_IDMABAR

ARGR

FIFOR0

FIFOR1

FIFOR2

FIFOR3

FIFOR4

FIFOR5

FIFOR6

FIFOR7

FIFOR8

FIFOR9

FIFOR10

FIFOR11

FIFOR12

FIFOR13

FIFOR14

FIFOR15

CMDR

PWRCTRL : SDMMC state control bits
bits : 0 - 1 (2 bit)

VSWITCH : Voltage switch sequence start
bits : 2 - 2 (1 bit)

VSWITCHEN : Voltage switch procedure enable
bits : 3 - 3 (1 bit)

DIRPOL : Data and command direction signals polarity selection
bits : 4 - 4 (1 bit)

RESPCMD : Response command index
bits : 0 - 5 (6 bit)

CARDSTATUS1 : CARDSTATUS1
bits : 0 - 31 (32 bit)

CARDSTATUS2 : CARDSTATUS2
bits : 0 - 31 (32 bit)

CARDSTATUS3 : CARDSTATUS3
bits : 0 - 31 (32 bit)

CARDSTATUS4 : CARDSTATUS4
bits : 0 - 31 (32 bit)

DATATIME : Data and R1b busy timeout period
bits : 0 - 31 (32 bit)

DATALENGTH : Data length value
bits : 0 - 24 (25 bit)

DTEN : DTEN
bits : 0 - 0 (1 bit)

DTDIR : Data transfer direction selection
bits : 1 - 1 (1 bit)

DTMODE : Data transfer mode selection
bits : 2 - 3 (2 bit)

DBLOCKSIZE : Data block size
bits : 4 - 7 (4 bit)

RWSTART : Read wait start
bits : 8 - 8 (1 bit)

RWSTOP : Read wait stop
bits : 9 - 9 (1 bit)

RWMOD : Read wait mode
bits : 10 - 10 (1 bit)

SDIOEN : SD I/O enable functions
bits : 11 - 11 (1 bit)

BOOTACKEN : Enable the reception of the boot acknowledgment
bits : 12 - 12 (1 bit)

FIFORST : FIFO reset, will flush any remaining data
bits : 13 - 13 (1 bit)

DATACOUNT : Data count value
bits : 0 - 24 (25 bit)

CCRCFAIL : Command response received (CRC check failed)
bits : 0 - 0 (1 bit)

DCRCFAIL : Data block sent/received (CRC check failed)
bits : 1 - 1 (1 bit)

CTIMEOUT : Command response timeout
bits : 2 - 2 (1 bit)

DTIMEOUT : Data timeout
bits : 3 - 3 (1 bit)

TXUNDERR : Transmit FIFO underrun error (masked by hardware when IDMA is enabled)
bits : 4 - 4 (1 bit)

RXOVERR : Received FIFO overrun error (masked by hardware when IDMA is enabled)
bits : 5 - 5 (1 bit)

CMDREND : Command response received (CRC check passed, or no CRC)
bits : 6 - 6 (1 bit)

CMDSENT : Command sent (no response required)
bits : 7 - 7 (1 bit)

DATAEND : Data transfer ended correctly
bits : 8 - 8 (1 bit)

DHOLD : Data transfer Hold
bits : 9 - 9 (1 bit)

DBCKEND : Data block sent/received
bits : 10 - 10 (1 bit)

DABORT : Data transfer aborted by CMD12
bits : 11 - 11 (1 bit)

DPSMACT : Data path state machine active, i.e. not in Idle state
bits : 12 - 12 (1 bit)

CPSMACT : Command path state machine active, i.e. not in Idle state
bits : 13 - 13 (1 bit)

TXFIFOHE : Transmit FIFO half empty
bits : 14 - 14 (1 bit)

RXFIFOHF : Receive FIFO half full
bits : 15 - 15 (1 bit)

TXFIFOF : Transmit FIFO full
bits : 16 - 16 (1 bit)

RXFIFOF : Receive FIFO full
bits : 17 - 17 (1 bit)

TXFIFOE : Transmit FIFO empty
bits : 18 - 18 (1 bit)

RXFIFOE : Receive FIFO empty
bits : 19 - 19 (1 bit)

BUSYD0 : Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response
bits : 20 - 20 (1 bit)

BUSYD0END : end of SDMMC_D0 Busy following a CMD response detected
bits : 21 - 21 (1 bit)

SDIOIT : SDIO interrupt received
bits : 22 - 22 (1 bit)

ACKFAIL : Boot acknowledgment received (boot acknowledgment check fail)
bits : 23 - 23 (1 bit)

ACKTIMEOUT : Boot acknowledgment timeout
bits : 24 - 24 (1 bit)

VSWEND : Voltage switch critical timing section completion
bits : 25 - 25 (1 bit)

CKSTOP : SDMMC_CK stopped in Voltage switch procedure
bits : 26 - 26 (1 bit)

IDMATE : IDMA transfer error
bits : 27 - 27 (1 bit)

IDMABTC : IDMA buffer transfer complete
bits : 28 - 28 (1 bit)

CCRCFAILC : CCRCFAIL flag clear bit
bits : 0 - 0 (1 bit)

DCRCFAILC : DCRCFAIL flag clear bit
bits : 1 - 1 (1 bit)

CTIMEOUTC : CTIMEOUT flag clear bit
bits : 2 - 2 (1 bit)

DTIMEOUTC : DTIMEOUT flag clear bit
bits : 3 - 3 (1 bit)

TXUNDERRC : TXUNDERR flag clear bit
bits : 4 - 4 (1 bit)

RXOVERRC : RXOVERR flag clear bit
bits : 5 - 5 (1 bit)

CMDRENDC : CMDREND flag clear bit
bits : 6 - 6 (1 bit)

CMDSENTC : CMDSENT flag clear bit
bits : 7 - 7 (1 bit)

DATAENDC : DATAEND flag clear bit
bits : 8 - 8 (1 bit)

DHOLDC : DHOLD flag clear bit
bits : 9 - 9 (1 bit)

DBCKENDC : DBCKEND flag clear bit
bits : 10 - 10 (1 bit)

DABORTC : DABORT flag clear bit
bits : 11 - 11 (1 bit)

BUSYD0ENDC : BUSYD0END flag clear bit
bits : 21 - 21 (1 bit)

SDIOITC : SDIOIT flag clear bit
bits : 22 - 22 (1 bit)

ACKFAILC : ACKFAIL flag clear bit
bits : 23 - 23 (1 bit)

ACKTIMEOUTC : ACKTIMEOUT flag clear bit
bits : 24 - 24 (1 bit)

VSWENDC : VSWEND flag clear bit
bits : 25 - 25 (1 bit)

CKSTOPC : CKSTOP flag clear bit
bits : 26 - 26 (1 bit)

IDMATEC : IDMA transfer error clear bit
bits : 27 - 27 (1 bit)

IDMABTCC : IDMA buffer transfer complete clear bit
bits : 28 - 28 (1 bit)

CCRCFAILIE : Command CRC fail interrupt enable
bits : 0 - 0 (1 bit)

DCRCFAILIE : Data CRC fail interrupt enable
bits : 1 - 1 (1 bit)

CTIMEOUTIE : Command timeout interrupt enable
bits : 2 - 2 (1 bit)

DTIMEOUTIE : Data timeout interrupt enable
bits : 3 - 3 (1 bit)

TXUNDERRIE : Tx FIFO underrun error interrupt enable
bits : 4 - 4 (1 bit)

RXOVERRIE : Rx FIFO overrun error interrupt enable
bits : 5 - 5 (1 bit)

CMDRENDIE : Command response received interrupt enable
bits : 6 - 6 (1 bit)

CMDSENTIE : Command sent interrupt enable
bits : 7 - 7 (1 bit)

DATAENDIE : Data end interrupt enable
bits : 8 - 8 (1 bit)

DHOLDIE : Data hold interrupt enable
bits : 9 - 9 (1 bit)

DBCKENDIE : Data block end interrupt enable
bits : 10 - 10 (1 bit)

DABORTIE : Data transfer aborted interrupt enable
bits : 11 - 11 (1 bit)

TXFIFOHEIE : Tx FIFO half empty interrupt enable
bits : 14 - 14 (1 bit)

RXFIFOHFIE : Rx FIFO half full interrupt enable
bits : 15 - 15 (1 bit)

RXFIFOFIE : Rx FIFO full interrupt enable
bits : 17 - 17 (1 bit)

TXFIFOEIE : Tx FIFO empty interrupt enable
bits : 18 - 18 (1 bit)

BUSYD0ENDIE : BUSYD0END interrupt enable
bits : 21 - 21 (1 bit)

SDIOITIE : SDIO mode interrupt received interrupt enable
bits : 22 - 22 (1 bit)

ACKFAILIE : Acknowledgment Fail interrupt enable
bits : 23 - 23 (1 bit)

ACKTIMEOUTIE : Acknowledgment timeout interrupt enable
bits : 24 - 24 (1 bit)

VSWENDIE : Voltage switch critical timing section completion interrupt enable
bits : 25 - 25 (1 bit)

CKSTOPIE : Voltage Switch clock stopped interrupt enable
bits : 26 - 26 (1 bit)

IDMABTCIE : IDMA buffer transfer complete interrupt enable
bits : 28 - 28 (1 bit)

CLKDIV : Clock divide factor
bits : 0 - 9 (10 bit)

PWRSAV : Power saving configuration bit
bits : 12 - 12 (1 bit)

WIDBUS : Wide bus mode enable bit
bits : 14 - 15 (2 bit)

NEGEDGE : SDIO_CK dephasing selection bit
bits : 16 - 16 (1 bit)

HWFC_EN : HW Flow Control enable
bits : 17 - 17 (1 bit)

DDR : Data rate signaling selection
bits : 18 - 18 (1 bit)

BUSSPEED : Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50,DDR50, SDR104
bits : 19 - 19 (1 bit)

SELCLKRX : Receive clock selection
bits : 20 - 21 (2 bit)

ACKTIME : Boot acknowledgment timeout period
bits : 0 - 24 (25 bit)

IDMAEN : IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
bits : 0 - 0 (1 bit)

IDMABMODE : Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
bits : 1 - 1 (1 bit)

IDMABNDT : Number of bytes per buffer
bits : 5 - 16 (12 bit)

IDMABASE : Buffer memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only)
bits : 0 - 31 (32 bit)

IDMALA : Acknowledge linked list buffer ready
bits : 2 - 15 (14 bit)

ABR : Acknowledge linked list buffer ready
bits : 29 - 29 (1 bit)

ULS : Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)
bits : 30 - 30 (1 bit)

ULA : Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)
bits : 31 - 31 (1 bit)

IDMABA : Word aligned Linked list memory base address
bits : 2 - 31 (30 bit)

CMDARG : Command argument
bits : 0 - 31 (32 bit)

FIFODATA : Receive and transmit FIFO data
bits : 0 - 31 (32 bit)

FIFODATA : Receive and transmit FIFO data
bits : 0 - 31 (32 bit)

FIFODATA : Receive and transmit FIFO data
bits : 0 - 31 (32 bit)

FIFODATA : Receive and transmit FIFO data
bits : 0 - 31 (32 bit)

FIFODATA : Receive and transmit FIFO data
bits : 0 - 31 (32 bit)

FIFODATA : Receive and transmit FIFO data
bits : 0 - 31 (32 bit)

FIFODATA : Receive and transmit FIFO data
bits : 0 - 31 (32 bit)

FIFODATA : Receive and transmit FIFO data
bits : 0 - 31 (32 bit)

FIFODATA : Receive and transmit FIFO data
bits : 0 - 31 (32 bit)

FIFODATA : Receive and transmit FIFO data
bits : 0 - 31 (32 bit)

FIFODATA : Receive and transmit FIFO data
bits : 0 - 31 (32 bit)

FIFODATA : Receive and transmit FIFO data
bits : 0 - 31 (32 bit)

FIFODATA : Receive and transmit FIFO data
bits : 0 - 31 (32 bit)

FIFODATA : Receive and transmit FIFO data
bits : 0 - 31 (32 bit)

FIFODATA : Receive and transmit FIFO data
bits : 0 - 31 (32 bit)

FIFODATA : Receive and transmit FIFO data
bits : 0 - 31 (32 bit)

CMDINDEX : Command index
bits : 0 - 5 (6 bit)

CMDTRANS : The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM
bits : 6 - 6 (1 bit)

CMDSTOP : The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM
bits : 7 - 7 (1 bit)

WAITRESP : Wait for response bits
bits : 8 - 9 (2 bit)

WAITINT : CPSM waits for interrupt request
bits : 10 - 10 (1 bit)

WAITPEND : CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM
bits : 11 - 11 (1 bit)

CPSMEN : Command path state machine (CPSM) Enable bit
bits : 12 - 12 (1 bit)

DTHOLD : Hold new data block transmission and reception in the DPSM
bits : 13 - 13 (1 bit)

BOOTMODE : Select the boot mode procedure to be used
bits : 14 - 14 (1 bit)

BOOTEN : Enable boot mode procedure
bits : 15 - 15 (1 bit)

CMDSUSPEND : The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end
bits : 16 - 16 (1 bit)