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OTG_FS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x88000 byte (0x0)
mem_usage : registers
protection :

Registers

GOTGCTL

GRSTCTL

HPTXFSIZ

DIEPTXF1

DIEPTXF2

DIEPTXF3

DIEPTXF4

DIEPTXF5

GINTSTS

GINTMSK

GRXSTSR_DEVICE

GRXSTSR_HOST

GRXSTSP__DEVICE (GRXSTSP_DEVICE)

GRXSTSP_HOST

GRXFSIZ

HNPTXFSIZ

HNPTXSTS

GCCFG

CID

GOTGINT

HCFG

HFIR

HFNUM

HPTXSTS

HAINT

HAINTMSK

HPRT

HCCHAR0

HCINT0

HCINTMSK0

HCTSIZ0

HCCHAR1

HCINT1 (HCINT1_DEVICE)

HCINTMSK1

HCTSIZ1

GLPMCFG

HCCHAR2

HCINT2

HCINTMSK2

HCTSIZ2

HCCHAR3

HCINT3

HCINTMSK3

HCTSIZ3

HCCHAR4

HCINT4

HCINTMSK4

HCTSIZ4

HCCHAR5

HCINT5

HCINTMSK5

HCTSIZ5

HCCHAR6

HCINT6

HCINTMSK6

HCTSIZ6

HCCHAR7

HCINT7

HCINTMSK7

HCTSIZ7

HCCHAR8

HCINT8

HCINTMSK8

HCTSIZ8

HCCHAR9

HCINT9

HCINTMSK9

HCTSIZ9

HCCHAR10

HCINT10

HCINTMSK10

HCTSIZ10

HCCHAR11

HCINT11

HCINTMSK11

HCTSIZ11

GAHBCFG

DCFG

DCTL

DSTS

DIEPMSK

DOEPMSK

DAINT

DAINTMSK

DVBUSDIS

DVBUSPULSE

DIEPEMPMSK

DIEPCTL0

DIEPINT0

DIEPTSIZ0

DTXFSTS0

DIEPCTL1

DIEPINT1

DIEPTSIZ1

DIEPDMA1

DTXFSTS1

DIEPCTL2

DIEPINT2

DIEPTSIZ2

DIEPDMA2

DTXFSTS2

DIEPCTL3

DIEPINT3

DIEPTSIZ3

DIEPDMA3

DTXFSTS3

DIEPCTL4

DIEPINT4

DIEPTSIZ4

DIEPDMA4

DTXFSTS4

DIEPCTL5

DIEPINT5

DIEPTSIZ5

DIEPDMA5

DTXFSTS5

DIEPINT6

DIEPTSIZ6

DIEPDMA6

DIEPINT7

DIEPTSIZ7

DIEPDMA7

DIEPINT8

DIEPTSIZ8

DIEPDMA8

DOEPCTL0

DOEPINT0

DOEPTSIZ0

DOEPDMA0

DOEPCTL1

DOEPINT1

DOEPTSIZ1

DOEPDMA1

DOEPCTL2

DOEPINT2

DOEPTSIZ2

DOEPDMA2

DOEPCTL3

DOEPINT3

DOEPTSIZ3

DOEPDMA3

DOEPCTL4

DOEPINT4

DOEPTSIZ4

DOEPDMA4

DOEPCTL5

DOEPINT5

DOEPTSIZ5

DOEPDMA5

DOEPCTL6

DOEPINT6

DOEPTSIZ6

DOEPDMA6

DOEPCTL7

DOEPINT7

DOEPTSIZ7

DOEPDMA7

GUSBCFG

DOEPCTL8

DOEPINT8

DOEPTSIZ8

DOEPDMA8

PCGCCTL


GOTGCTL

The GOTGCTL register controls the behavior and reflects the status of the OTG function of the core.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GOTGCTL GOTGCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRQSCS SRQ VBVALOEN VBVALOVAL AVALOEN AVALOVAL BVALOEN BVALOVAL HNGSCS HNPRQ HSHNPEN DHNPEN EHEN CIDSTS DBCT ASVLD BSVLD OTGVER CURMOD

SRQSCS : SRQSCS
bits : 0 - 0 (1 bit)
access : read-only

SRQ : SRQ
bits : 1 - 1 (1 bit)
access : read-write

VBVALOEN : VBVALOEN
bits : 2 - 2 (1 bit)
access : read-write

VBVALOVAL : VBVALOVAL
bits : 3 - 3 (1 bit)
access : read-write

AVALOEN : AVALOEN
bits : 4 - 4 (1 bit)
access : read-write

AVALOVAL : AVALOVAL
bits : 5 - 5 (1 bit)
access : read-write

BVALOEN : BVALOEN
bits : 6 - 6 (1 bit)
access : read-write

BVALOVAL : BVALOVAL
bits : 7 - 7 (1 bit)
access : read-write

HNGSCS : HNGSCS
bits : 8 - 8 (1 bit)
access : read-only

HNPRQ : HNPRQ
bits : 9 - 9 (1 bit)
access : read-write

HSHNPEN : HSHNPEN
bits : 10 - 10 (1 bit)
access : read-write

DHNPEN : DHNPEN
bits : 11 - 11 (1 bit)
access : read-write

EHEN : EHEN
bits : 12 - 12 (1 bit)
access : read-write

CIDSTS : CIDSTS
bits : 16 - 16 (1 bit)
access : read-only

DBCT : DBCT
bits : 17 - 17 (1 bit)
access : read-only

ASVLD : ASVLD
bits : 18 - 18 (1 bit)
access : read-only

BSVLD : BSVLD
bits : 19 - 19 (1 bit)
access : read-only

OTGVER : OTGVER
bits : 20 - 20 (1 bit)
access : read-write

CURMOD : CURMOD
bits : 21 - 21 (1 bit)
access : read-only


GRSTCTL

The application uses this register to reset various hardware features inside the core.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GRSTCTL GRSTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSRST PSRST FSRST RXFFLSH TXFFLSH TXFNUM AHBIDL

CSRST : CSRST
bits : 0 - 0 (1 bit)
access : read-only

PSRST : PSRST
bits : 1 - 1 (1 bit)
access : read-write

FSRST : FSRST
bits : 2 - 2 (1 bit)
access : read-write

RXFFLSH : RXFFLSH
bits : 4 - 4 (1 bit)
access : read-write

TXFFLSH : TXFFLSH
bits : 5 - 5 (1 bit)
access : read-write

TXFNUM : TXFNUM
bits : 6 - 10 (5 bit)
access : read-write

AHBIDL : AHBIDL
bits : 31 - 31 (1 bit)
access : read-only


HPTXFSIZ

OTG host periodic transmit FIFO size register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HPTXFSIZ HPTXFSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTXSA PTXFSIZ

PTXSA : PTXSA
bits : 0 - 15 (16 bit)

PTXFSIZ : PTXFSIZ
bits : 16 - 31 (16 bit)


DIEPTXF1

OTG device IN endpoint transmit FIFO 1 size register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTXF1 DIEPTXF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTXSA INEPTXFD

INEPTXSA : INEPTXSA
bits : 0 - 15 (16 bit)

INEPTXFD : INEPTXFD
bits : 16 - 31 (16 bit)


DIEPTXF2

OTG device IN endpoint transmit FIFO 2 size register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTXF2 DIEPTXF2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTXSA INEPTXFD

INEPTXSA : INEPTXSA
bits : 0 - 15 (16 bit)

INEPTXFD : INEPTXFD
bits : 16 - 31 (16 bit)


DIEPTXF3

OTG device IN endpoint transmit FIFO 3 size register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTXF3 DIEPTXF3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTXSA INEPTXFD

INEPTXSA : INEPTXSA
bits : 0 - 15 (16 bit)

INEPTXFD : INEPTXFD
bits : 16 - 31 (16 bit)


DIEPTXF4

OTG device IN endpoint transmit FIFO 4 size register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTXF4 DIEPTXF4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTXSA INEPTXFD

INEPTXSA : INEPTXSA
bits : 0 - 15 (16 bit)

INEPTXFD : INEPTXFD
bits : 16 - 31 (16 bit)


DIEPTXF5

OTG device IN endpoint transmit FIFO 5 size register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTXF5 DIEPTXF5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTXSA INEPTXFD

INEPTXSA : INEPTXSA
bits : 0 - 15 (16 bit)

INEPTXFD : INEPTXFD
bits : 16 - 31 (16 bit)


GINTSTS

This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GINTSTS GINTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMOD MMIS OTGINT SOF RXFLVL NPTXFE GINAKEFF GONAKEFF ESUSP USBSUSP USBRST ENUMDNE ISOODRP EOPF IEPINT OEPINT IISOIXFR IPXFR RSTDET HPRTINT HCINT PTXFE LPMINT CIDSCHG DISCINT SRQINT WKUPINT

CMOD : CMOD
bits : 0 - 0 (1 bit)
access : read-only

MMIS : MMIS
bits : 1 - 1 (1 bit)
access : read-write

OTGINT : OTGINT
bits : 2 - 2 (1 bit)
access : read-only

SOF : SOF
bits : 3 - 3 (1 bit)
access : read-write

RXFLVL : RXFLVL
bits : 4 - 4 (1 bit)
access : read-only

NPTXFE : NPTXFE
bits : 5 - 5 (1 bit)
access : read-only

GINAKEFF : GINAKEFF
bits : 6 - 6 (1 bit)
access : read-only

GONAKEFF : GONAKEFF
bits : 7 - 7 (1 bit)
access : read-only

ESUSP : ESUSP
bits : 10 - 10 (1 bit)
access : read-write

USBSUSP : USBSUSP
bits : 11 - 11 (1 bit)
access : read-write

USBRST : USBRST
bits : 12 - 12 (1 bit)
access : read-write

ENUMDNE : ENUMDNE
bits : 13 - 13 (1 bit)
access : read-write

ISOODRP : ISOODRP
bits : 14 - 14 (1 bit)
access : read-write

EOPF : EOPF
bits : 15 - 15 (1 bit)
access : read-write

IEPINT : IEPINT
bits : 18 - 18 (1 bit)
access : read-only

OEPINT : OEPINT
bits : 19 - 19 (1 bit)
access : read-only

IISOIXFR : IISOIXFR
bits : 20 - 20 (1 bit)
access : read-write

IPXFR : IPXFR
bits : 21 - 21 (1 bit)
access : read-write

RSTDET : RSTDET
bits : 23 - 23 (1 bit)
access : read-write

HPRTINT : HPRTINT
bits : 24 - 24 (1 bit)
access : read-only

HCINT : HCINT
bits : 25 - 25 (1 bit)
access : read-only

PTXFE : PTXFE
bits : 26 - 26 (1 bit)
access : read-only

LPMINT : LPMINT
bits : 27 - 27 (1 bit)
access : read-write

CIDSCHG : CIDSCHG
bits : 28 - 28 (1 bit)
access : read-write

DISCINT : DISCINT
bits : 29 - 29 (1 bit)
access : read-write

SRQINT : SRQINT
bits : 30 - 30 (1 bit)
access : read-write

WKUPINT : WKUPINT
bits : 31 - 31 (1 bit)
access : read-write


GINTMSK

This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (GINTSTS) register bit corresponding to that interrupt is still set.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GINTMSK GINTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMISM OTGINT SOFM RXFLVLM NPTXFEM GINAKEFFM GONAKEFFM ESUSPM USBSUSPM USBRST ENUMDNEM ISOODRPM EOPFM IEPINT OEPINT IISOIXFRM IPXFRM RSTDETM PRTIM HCIM PTXFEM LPMINTM CIDSCHGM DISCINT SRQIM WUIM

MMISM : MMISM
bits : 1 - 1 (1 bit)
access : read-write

OTGINT : OTGINT
bits : 2 - 2 (1 bit)
access : read-write

SOFM : SOFM
bits : 3 - 3 (1 bit)
access : read-write

RXFLVLM : RXFLVLM
bits : 4 - 4 (1 bit)
access : read-write

NPTXFEM : NPTXFEM
bits : 5 - 5 (1 bit)
access : read-write

GINAKEFFM : GINAKEFFM
bits : 6 - 6 (1 bit)
access : read-write

GONAKEFFM : GONAKEFFM
bits : 7 - 7 (1 bit)
access : read-write

ESUSPM : ESUSPM
bits : 10 - 10 (1 bit)
access : read-write

USBSUSPM : USBSUSPM
bits : 11 - 11 (1 bit)
access : read-write

USBRST : USBRST
bits : 12 - 12 (1 bit)
access : read-write

ENUMDNEM : ENUMDNEM
bits : 13 - 13 (1 bit)
access : read-write

ISOODRPM : ISOODRPM
bits : 14 - 14 (1 bit)
access : read-write

EOPFM : EOPFM
bits : 15 - 15 (1 bit)
access : read-write

IEPINT : IEPINT
bits : 18 - 18 (1 bit)
access : read-write

OEPINT : OEPINT
bits : 19 - 19 (1 bit)
access : read-write

IISOIXFRM : IISOIXFRM
bits : 20 - 20 (1 bit)
access : read-write

IPXFRM : IPXFRM
bits : 21 - 21 (1 bit)
access : read-write

RSTDETM : RSTDETM
bits : 23 - 23 (1 bit)
access : read-write

PRTIM : PRTIM
bits : 24 - 24 (1 bit)
access : read-write

HCIM : HCIM
bits : 25 - 25 (1 bit)
access : read-write

PTXFEM : PTXFEM
bits : 26 - 26 (1 bit)
access : read-write

LPMINTM : LPMINTM
bits : 27 - 27 (1 bit)
access : read-write

CIDSCHGM : CIDSCHGM
bits : 28 - 28 (1 bit)
access : read-write

DISCINT : DISCINT
bits : 29 - 29 (1 bit)
access : read-write

SRQIM : SRQIM
bits : 30 - 30 (1 bit)
access : read-write

WUIM : WUIM
bits : 31 - 31 (1 bit)
access : read-write


GRXSTSR_DEVICE

This description is for register GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and returns a value of 0x00000000.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GRXSTSR_DEVICE GRXSTSR_DEVICE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPNUM BCNT DPID PKTSTS FRMNUM STSPHST

EPNUM : EPNUM
bits : 0 - 3 (4 bit)

BCNT : BCNT
bits : 4 - 14 (11 bit)

DPID : DPID
bits : 15 - 16 (2 bit)

PKTSTS : PKTSTS
bits : 17 - 20 (4 bit)

FRMNUM : FRMNUM
bits : 21 - 24 (4 bit)

STSPHST : STSPHST
bits : 27 - 27 (1 bit)


GRXSTSR_HOST

This description is for register GRXSTSR in Host mode
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : GRXSTSR_DEVICE
reset_Mask : 0x0

GRXSTSR_HOST GRXSTSR_HOST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNUM BCNT DPID PKTSTS

CHNUM : CHNUM
bits : 0 - 3 (4 bit)

BCNT : BCNT
bits : 4 - 14 (11 bit)

DPID : DPID
bits : 15 - 16 (2 bit)

PKTSTS : PKTSTS
bits : 17 - 20 (4 bit)


GRXSTSP__DEVICE (GRXSTSP_DEVICE)

This description is for register GRXSTSP in Device mode. Similarly to GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO, a read to GRXSTSP (receive status read and pop register) additionally pops the top data entry out of the Rx FIFO. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the receive status FIFO when the receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in GINTSTS) is asserted.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GRXSTSP__DEVICE GRXSTSP__DEVICE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPNUM BCNT DPID PKTSTS FRMNUM STSPHST

EPNUM : EPNUM
bits : 0 - 3 (4 bit)

BCNT : BCNT
bits : 4 - 14 (11 bit)

DPID : DPID
bits : 15 - 16 (2 bit)

PKTSTS : PKTSTS
bits : 17 - 20 (4 bit)

FRMNUM : FRMNUM
bits : 21 - 24 (4 bit)

STSPHST : STSPHST
bits : 27 - 27 (1 bit)


GRXSTSP_HOST

This description is for register GRXSTSP in HOST mode
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : GRXSTSP_DEVICE
reset_Mask : 0x0

GRXSTSP_HOST GRXSTSP_HOST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNUM BCNT DPID PKTSTS

CHNUM : CHNUM
bits : 0 - 3 (4 bit)

BCNT : BCNT
bits : 4 - 14 (11 bit)

DPID : DPID
bits : 15 - 16 (2 bit)

PKTSTS : PKTSTS
bits : 17 - 20 (4 bit)


GRXFSIZ

The application can program the RAM size that must be allocated to the Rx FIFO.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GRXFSIZ GRXFSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFD

RXFD : RXFD
bits : 0 - 15 (16 bit)


HNPTXFSIZ

Host mode
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HNPTXFSIZ HNPTXFSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPTXFSA NPTXFD

NPTXFSA : NPTXFSA
bits : 0 - 15 (16 bit)

NPTXFD : NPTXFD
bits : 16 - 31 (16 bit)


HNPTXSTS

In device mode, this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HNPTXSTS HNPTXSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPTXFSAV NPTQXSAV NPTXQTOP

NPTXFSAV : NPTXFSAV
bits : 0 - 15 (16 bit)

NPTQXSAV : NPTQXSAV
bits : 16 - 23 (8 bit)

NPTXQTOP : NPTXQTOP
bits : 24 - 30 (7 bit)


GCCFG

OTG general core configuration register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCCFG GCCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDET PDET SDET PS2DET PWRDWN BCDEN DCDEN PDEN SDEN VBDEN

DCDET : DCDET
bits : 0 - 0 (1 bit)
access : read-only

PDET : PDET
bits : 1 - 1 (1 bit)
access : read-only

SDET : SDET
bits : 2 - 2 (1 bit)
access : read-only

PS2DET : PS2DET
bits : 3 - 3 (1 bit)
access : read-only

PWRDWN : PWRDWN
bits : 16 - 16 (1 bit)
access : read-write

BCDEN : BCDEN
bits : 17 - 17 (1 bit)
access : read-write

DCDEN : DCDEN
bits : 18 - 18 (1 bit)
access : read-write

PDEN : PDEN
bits : 19 - 19 (1 bit)
access : read-write

SDEN : SDEN
bits : 20 - 20 (1 bit)
access : read-write

VBDEN : VBDEN
bits : 21 - 21 (1 bit)
access : read-write


CID

This is a register containing the Product ID as reset value.
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CID CID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRODUCT_ID

PRODUCT_ID : PRODUCT_ID
bits : 0 - 31 (32 bit)


GOTGINT

The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GOTGINT GOTGINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEDET SRSSCHG HNSSCHG HNGDET ADTOCHG DBCDNE

SEDET : SEDET
bits : 2 - 2 (1 bit)

SRSSCHG : SRSSCHG
bits : 8 - 8 (1 bit)

HNSSCHG : HNSSCHG
bits : 9 - 9 (1 bit)

HNGDET : HNGDET
bits : 17 - 17 (1 bit)

ADTOCHG : ADTOCHG
bits : 18 - 18 (1 bit)

DBCDNE : DBCDNE
bits : 19 - 19 (1 bit)


HCFG

This register configures the core after power-on. Do not make changes to this register after initializing the host.
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCFG HCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSLSPCS FSLSS

FSLSPCS : FSLSPCS
bits : 0 - 1 (2 bit)
access : read-write

FSLSS : FSLSS
bits : 2 - 2 (1 bit)
access : read-only


HFIR

This register stores the frame interval information for the current speed to which the OTG controller has enumerated.
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFIR HFIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRIVL RLDCTRL

FRIVL : FRIVL
bits : 0 - 15 (16 bit)

RLDCTRL : RLDCTRL
bits : 16 - 16 (1 bit)


HFNUM

This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame.
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HFNUM HFNUM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRNUM FTREM

FRNUM : FRNUM
bits : 0 - 15 (16 bit)

FTREM : FTREM
bits : 16 - 31 (16 bit)


HPTXSTS

This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue.
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HPTXSTS HPTXSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTXFSAVL PTXQSAV PTXQTOP

PTXFSAVL : PTXFSAVL
bits : 0 - 15 (16 bit)

PTXQSAV : PTXQSAV
bits : 16 - 23 (8 bit)

PTXQTOP : PTXQTOP
bits : 24 - 31 (8 bit)


HAINT

When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in GINTSTS). This is shown in Figure724. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register.
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HAINT HAINT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAINT

HAINT : HAINT
bits : 0 - 15 (16 bit)


HAINTMSK

The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits.
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HAINTMSK HAINTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAINTM

HAINTM : HAINTM
bits : 0 - 15 (16 bit)


HPRT

This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt.
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HPRT HPRT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCSTS PCDET PENA PENCHNG POCA POCCHNG PRES PSUSP PRST PLSTS PPWR PTCTL PSPD

PCSTS : PCSTS
bits : 0 - 0 (1 bit)
access : read-only

PCDET : PCDET
bits : 1 - 1 (1 bit)
access : read-write

PENA : PENA
bits : 2 - 2 (1 bit)
access : read-write

PENCHNG : PENCHNG
bits : 3 - 3 (1 bit)
access : read-write

POCA : POCA
bits : 4 - 4 (1 bit)
access : read-only

POCCHNG : POCCHNG
bits : 5 - 5 (1 bit)
access : read-write

PRES : PRES
bits : 6 - 6 (1 bit)
access : read-write

PSUSP : PSUSP
bits : 7 - 7 (1 bit)
access : read-write

PRST : PRST
bits : 8 - 8 (1 bit)
access : read-write

PLSTS : PLSTS
bits : 10 - 11 (2 bit)
access : read-only

PPWR : PPWR
bits : 12 - 12 (1 bit)
access : read-write

PTCTL : PTCTL
bits : 13 - 16 (4 bit)
access : read-write

PSPD : PSPD
bits : 17 - 18 (2 bit)
access : read-only


HCCHAR0

OTG host channel 0 characteristics register
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCCHAR0 HCCHAR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MCNT DAD ODDFRM CHDIS CHENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)

EPNUM : EPNUM
bits : 11 - 14 (4 bit)

EPDIR : EPDIR
bits : 15 - 15 (1 bit)

LSDEV : LSDEV
bits : 17 - 17 (1 bit)

EPTYP : EPTYP
bits : 18 - 19 (2 bit)

MCNT : MCNT
bits : 20 - 21 (2 bit)

DAD : DAD
bits : 22 - 28 (7 bit)

ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)

CHDIS : CHDIS
bits : 30 - 30 (1 bit)

CHENA : CHENA
bits : 31 - 31 (1 bit)


HCINT0

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINT0 HCINT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH STALL NAK ACK TXERR BBERR FRMOR DTERR

XFRC : XFRC
bits : 0 - 0 (1 bit)

CHH : CHH
bits : 1 - 1 (1 bit)

STALL : STALL
bits : 3 - 3 (1 bit)

NAK : NAK
bits : 4 - 4 (1 bit)

ACK : ACK
bits : 5 - 5 (1 bit)

TXERR : TXERR
bits : 7 - 7 (1 bit)

BBERR : BBERR
bits : 8 - 8 (1 bit)

FRMOR : FRMOR
bits : 9 - 9 (1 bit)

DTERR : DTERR
bits : 10 - 10 (1 bit)


HCINTMSK0

This register reflects the mask for each channel status described in the previous section.
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINTMSK0 HCINTMSK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM STALLM NAKM ACKM TXERRM BBERRM FRMORM DTERRM

XFRCM : XFRCM
bits : 0 - 0 (1 bit)

CHHM : CHHM
bits : 1 - 1 (1 bit)

STALLM : STALLM
bits : 3 - 3 (1 bit)

NAKM : NAKM
bits : 4 - 4 (1 bit)

ACKM : ACKM
bits : 5 - 5 (1 bit)

TXERRM : TXERRM
bits : 7 - 7 (1 bit)

BBERRM : BBERRM
bits : 8 - 8 (1 bit)

FRMORM : FRMORM
bits : 9 - 9 (1 bit)

DTERRM : DTERRM
bits : 10 - 10 (1 bit)


HCTSIZ0

OTG host channel 0 transfer size register
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCTSIZ0 HCTSIZ0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID DOPNG

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

DPID : DPID
bits : 29 - 30 (2 bit)

DOPNG : DOPNG
bits : 31 - 31 (1 bit)


HCCHAR1

OTG host channel 1 characteristics register
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCCHAR1 HCCHAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MCNT DAD ODDFRM CHDIS CHENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)

EPNUM : EPNUM
bits : 11 - 14 (4 bit)

EPDIR : EPDIR
bits : 15 - 15 (1 bit)

LSDEV : LSDEV
bits : 17 - 17 (1 bit)

EPTYP : EPTYP
bits : 18 - 19 (2 bit)

MCNT : MCNT
bits : 20 - 21 (2 bit)

DAD : DAD
bits : 22 - 28 (7 bit)

ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)

CHDIS : CHDIS
bits : 30 - 30 (1 bit)

CHENA : CHENA
bits : 31 - 31 (1 bit)


HCINT1 (HCINT1_DEVICE)

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINT1 HCINT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH STALL NAK ACK TXERR BBERR FRMOR DTERR

XFRC : XFRC
bits : 0 - 0 (1 bit)

CHH : CHH
bits : 1 - 1 (1 bit)

STALL : STALL
bits : 3 - 3 (1 bit)

NAK : NAK
bits : 4 - 4 (1 bit)

ACK : ACK
bits : 5 - 5 (1 bit)

TXERR : TXERR
bits : 7 - 7 (1 bit)

BBERR : BBERR
bits : 8 - 8 (1 bit)

FRMOR : FRMOR
bits : 9 - 9 (1 bit)

DTERR : DTERR
bits : 10 - 10 (1 bit)


HCINTMSK1

This register reflects the mask for each channel status described in the previous section.
address_offset : 0x52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINTMSK1 HCINTMSK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM STALLM NAKM ACKM TXERRM BBERRM FRMORM DTERRM

XFRCM : XFRCM
bits : 0 - 0 (1 bit)

CHHM : CHHM
bits : 1 - 1 (1 bit)

STALLM : STALLM
bits : 3 - 3 (1 bit)

NAKM : NAKM
bits : 4 - 4 (1 bit)

ACKM : ACKM
bits : 5 - 5 (1 bit)

TXERRM : TXERRM
bits : 7 - 7 (1 bit)

BBERRM : BBERRM
bits : 8 - 8 (1 bit)

FRMORM : FRMORM
bits : 9 - 9 (1 bit)

DTERRM : DTERRM
bits : 10 - 10 (1 bit)


HCTSIZ1

OTG host channel 1 transfer size register
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCTSIZ1 HCTSIZ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID DOPNG

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

DPID : DPID
bits : 29 - 30 (2 bit)

DOPNG : DOPNG
bits : 31 - 31 (1 bit)


GLPMCFG

OTG core LPM configuration register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GLPMCFG GLPMCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPMEN LPMACK BESL REMWAKE L1SSEN BESLTHRS L1DSEN LPMRSP SLPSTS L1RSMOK LPMCHIDX LPMRCNT SNDLPM LPMRCNTSTS ENBESL

LPMEN : LPMEN
bits : 0 - 0 (1 bit)
access : read-write

LPMACK : LPMACK
bits : 1 - 1 (1 bit)
access : read-write

BESL : BESL
bits : 2 - 5 (4 bit)
access : read-write

REMWAKE : REMWAKE
bits : 6 - 6 (1 bit)
access : read-write

L1SSEN : L1SSEN
bits : 7 - 7 (1 bit)
access : read-write

BESLTHRS : BESLTHRS
bits : 8 - 11 (4 bit)
access : read-write

L1DSEN : L1DSEN
bits : 12 - 12 (1 bit)
access : read-write

LPMRSP : LPMRSP
bits : 13 - 14 (2 bit)
access : read-only

SLPSTS : SLPSTS
bits : 15 - 15 (1 bit)
access : read-only

L1RSMOK : L1RSMOK
bits : 16 - 16 (1 bit)
access : read-only

LPMCHIDX : LPMCHIDX
bits : 17 - 20 (4 bit)
access : read-write

LPMRCNT : LPMRCNT
bits : 21 - 23 (3 bit)
access : read-write

SNDLPM : SNDLPM
bits : 24 - 24 (1 bit)
access : read-write

LPMRCNTSTS : LPMRCNTSTS
bits : 25 - 27 (3 bit)
access : read-only

ENBESL : ENBESL
bits : 28 - 28 (1 bit)
access : read-write


HCCHAR2

OTG host channel 2 characteristics register
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCCHAR2 HCCHAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MCNT DAD ODDFRM CHDIS CHENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)

EPNUM : EPNUM
bits : 11 - 14 (4 bit)

EPDIR : EPDIR
bits : 15 - 15 (1 bit)

LSDEV : LSDEV
bits : 17 - 17 (1 bit)

EPTYP : EPTYP
bits : 18 - 19 (2 bit)

MCNT : MCNT
bits : 20 - 21 (2 bit)

DAD : DAD
bits : 22 - 28 (7 bit)

ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)

CHDIS : CHDIS
bits : 30 - 30 (1 bit)

CHENA : CHENA
bits : 31 - 31 (1 bit)


HCINT2

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x548 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINT2 HCINT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH STALL NAK ACK TXERR BBERR FRMOR DTERR

XFRC : XFRC
bits : 0 - 0 (1 bit)

CHH : CHH
bits : 1 - 1 (1 bit)

STALL : STALL
bits : 3 - 3 (1 bit)

NAK : NAK
bits : 4 - 4 (1 bit)

ACK : ACK
bits : 5 - 5 (1 bit)

TXERR : TXERR
bits : 7 - 7 (1 bit)

BBERR : BBERR
bits : 8 - 8 (1 bit)

FRMOR : FRMOR
bits : 9 - 9 (1 bit)

DTERR : DTERR
bits : 10 - 10 (1 bit)


HCINTMSK2

This register reflects the mask for each channel status described in the previous section.
address_offset : 0x54C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINTMSK2 HCINTMSK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM STALLM NAKM ACKM TXERRM BBERRM FRMORM DTERRM

XFRCM : XFRCM
bits : 0 - 0 (1 bit)

CHHM : CHHM
bits : 1 - 1 (1 bit)

STALLM : STALLM
bits : 3 - 3 (1 bit)

NAKM : NAKM
bits : 4 - 4 (1 bit)

ACKM : ACKM
bits : 5 - 5 (1 bit)

TXERRM : TXERRM
bits : 7 - 7 (1 bit)

BBERRM : BBERRM
bits : 8 - 8 (1 bit)

FRMORM : FRMORM
bits : 9 - 9 (1 bit)

DTERRM : DTERRM
bits : 10 - 10 (1 bit)


HCTSIZ2

OTG host channel 2 transfer size register
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCTSIZ2 HCTSIZ2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID DOPNG

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

DPID : DPID
bits : 29 - 30 (2 bit)

DOPNG : DOPNG
bits : 31 - 31 (1 bit)


HCCHAR3

OTG host channel 3 characteristics register
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCCHAR3 HCCHAR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MCNT DAD ODDFRM CHDIS CHENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)

EPNUM : EPNUM
bits : 11 - 14 (4 bit)

EPDIR : EPDIR
bits : 15 - 15 (1 bit)

LSDEV : LSDEV
bits : 17 - 17 (1 bit)

EPTYP : EPTYP
bits : 18 - 19 (2 bit)

MCNT : MCNT
bits : 20 - 21 (2 bit)

DAD : DAD
bits : 22 - 28 (7 bit)

ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)

CHDIS : CHDIS
bits : 30 - 30 (1 bit)

CHENA : CHENA
bits : 31 - 31 (1 bit)


HCINT3

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINT3 HCINT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH STALL NAK ACK TXERR BBERR FRMOR DTERR

XFRC : XFRC
bits : 0 - 0 (1 bit)

CHH : CHH
bits : 1 - 1 (1 bit)

STALL : STALL
bits : 3 - 3 (1 bit)

NAK : NAK
bits : 4 - 4 (1 bit)

ACK : ACK
bits : 5 - 5 (1 bit)

TXERR : TXERR
bits : 7 - 7 (1 bit)

BBERR : BBERR
bits : 8 - 8 (1 bit)

FRMOR : FRMOR
bits : 9 - 9 (1 bit)

DTERR : DTERR
bits : 10 - 10 (1 bit)


HCINTMSK3

This register reflects the mask for each channel status described in the previous section.
address_offset : 0x56C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINTMSK3 HCINTMSK3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM STALLM NAKM ACKM TXERRM BBERRM FRMORM DTERRM

XFRCM : XFRCM
bits : 0 - 0 (1 bit)

CHHM : CHHM
bits : 1 - 1 (1 bit)

STALLM : STALLM
bits : 3 - 3 (1 bit)

NAKM : NAKM
bits : 4 - 4 (1 bit)

ACKM : ACKM
bits : 5 - 5 (1 bit)

TXERRM : TXERRM
bits : 7 - 7 (1 bit)

BBERRM : BBERRM
bits : 8 - 8 (1 bit)

FRMORM : FRMORM
bits : 9 - 9 (1 bit)

DTERRM : DTERRM
bits : 10 - 10 (1 bit)


HCTSIZ3

OTG host channel 3 transfer size register
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCTSIZ3 HCTSIZ3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID DOPNG

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

DPID : DPID
bits : 29 - 30 (2 bit)

DOPNG : DOPNG
bits : 31 - 31 (1 bit)


HCCHAR4

OTG host channel 4 characteristics register
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCCHAR4 HCCHAR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MCNT DAD ODDFRM CHDIS CHENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)

EPNUM : EPNUM
bits : 11 - 14 (4 bit)

EPDIR : EPDIR
bits : 15 - 15 (1 bit)

LSDEV : LSDEV
bits : 17 - 17 (1 bit)

EPTYP : EPTYP
bits : 18 - 19 (2 bit)

MCNT : MCNT
bits : 20 - 21 (2 bit)

DAD : DAD
bits : 22 - 28 (7 bit)

ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)

CHDIS : CHDIS
bits : 30 - 30 (1 bit)

CHENA : CHENA
bits : 31 - 31 (1 bit)


HCINT4

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINT4 HCINT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH STALL NAK ACK TXERR BBERR FRMOR DTERR

XFRC : XFRC
bits : 0 - 0 (1 bit)

CHH : CHH
bits : 1 - 1 (1 bit)

STALL : STALL
bits : 3 - 3 (1 bit)

NAK : NAK
bits : 4 - 4 (1 bit)

ACK : ACK
bits : 5 - 5 (1 bit)

TXERR : TXERR
bits : 7 - 7 (1 bit)

BBERR : BBERR
bits : 8 - 8 (1 bit)

FRMOR : FRMOR
bits : 9 - 9 (1 bit)

DTERR : DTERR
bits : 10 - 10 (1 bit)


HCINTMSK4

This register reflects the mask for each channel status described in the previous section.
address_offset : 0x58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINTMSK4 HCINTMSK4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM STALLM NAKM ACKM TXERRM BBERRM FRMORM DTERRM

XFRCM : XFRCM
bits : 0 - 0 (1 bit)

CHHM : CHHM
bits : 1 - 1 (1 bit)

STALLM : STALLM
bits : 3 - 3 (1 bit)

NAKM : NAKM
bits : 4 - 4 (1 bit)

ACKM : ACKM
bits : 5 - 5 (1 bit)

TXERRM : TXERRM
bits : 7 - 7 (1 bit)

BBERRM : BBERRM
bits : 8 - 8 (1 bit)

FRMORM : FRMORM
bits : 9 - 9 (1 bit)

DTERRM : DTERRM
bits : 10 - 10 (1 bit)


HCTSIZ4

OTG host channel 4 transfer size register
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCTSIZ4 HCTSIZ4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID DOPNG

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

DPID : DPID
bits : 29 - 30 (2 bit)

DOPNG : DOPNG
bits : 31 - 31 (1 bit)


HCCHAR5

OTG host channel 5 characteristics register
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCCHAR5 HCCHAR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MCNT DAD ODDFRM CHDIS CHENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)

EPNUM : EPNUM
bits : 11 - 14 (4 bit)

EPDIR : EPDIR
bits : 15 - 15 (1 bit)

LSDEV : LSDEV
bits : 17 - 17 (1 bit)

EPTYP : EPTYP
bits : 18 - 19 (2 bit)

MCNT : MCNT
bits : 20 - 21 (2 bit)

DAD : DAD
bits : 22 - 28 (7 bit)

ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)

CHDIS : CHDIS
bits : 30 - 30 (1 bit)

CHENA : CHENA
bits : 31 - 31 (1 bit)


HCINT5

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x5A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINT5 HCINT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH STALL NAK ACK TXERR BBERR FRMOR DTERR

XFRC : XFRC
bits : 0 - 0 (1 bit)

CHH : CHH
bits : 1 - 1 (1 bit)

STALL : STALL
bits : 3 - 3 (1 bit)

NAK : NAK
bits : 4 - 4 (1 bit)

ACK : ACK
bits : 5 - 5 (1 bit)

TXERR : TXERR
bits : 7 - 7 (1 bit)

BBERR : BBERR
bits : 8 - 8 (1 bit)

FRMOR : FRMOR
bits : 9 - 9 (1 bit)

DTERR : DTERR
bits : 10 - 10 (1 bit)


HCINTMSK5

This register reflects the mask for each channel status described in the previous section.
address_offset : 0x5AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINTMSK5 HCINTMSK5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM STALLM NAKM ACKM TXERRM BBERRM FRMORM DTERRM

XFRCM : XFRCM
bits : 0 - 0 (1 bit)

CHHM : CHHM
bits : 1 - 1 (1 bit)

STALLM : STALLM
bits : 3 - 3 (1 bit)

NAKM : NAKM
bits : 4 - 4 (1 bit)

ACKM : ACKM
bits : 5 - 5 (1 bit)

TXERRM : TXERRM
bits : 7 - 7 (1 bit)

BBERRM : BBERRM
bits : 8 - 8 (1 bit)

FRMORM : FRMORM
bits : 9 - 9 (1 bit)

DTERRM : DTERRM
bits : 10 - 10 (1 bit)


HCTSIZ5

OTG host channel 5 transfer size register
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCTSIZ5 HCTSIZ5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID DOPNG

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

DPID : DPID
bits : 29 - 30 (2 bit)

DOPNG : DOPNG
bits : 31 - 31 (1 bit)


HCCHAR6

OTG host channel 6 characteristics register
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCCHAR6 HCCHAR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MCNT DAD ODDFRM CHDIS CHENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)

EPNUM : EPNUM
bits : 11 - 14 (4 bit)

EPDIR : EPDIR
bits : 15 - 15 (1 bit)

LSDEV : LSDEV
bits : 17 - 17 (1 bit)

EPTYP : EPTYP
bits : 18 - 19 (2 bit)

MCNT : MCNT
bits : 20 - 21 (2 bit)

DAD : DAD
bits : 22 - 28 (7 bit)

ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)

CHDIS : CHDIS
bits : 30 - 30 (1 bit)

CHENA : CHENA
bits : 31 - 31 (1 bit)


HCINT6

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x5C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINT6 HCINT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH STALL NAK ACK TXERR BBERR FRMOR DTERR

XFRC : XFRC
bits : 0 - 0 (1 bit)

CHH : CHH
bits : 1 - 1 (1 bit)

STALL : STALL
bits : 3 - 3 (1 bit)

NAK : NAK
bits : 4 - 4 (1 bit)

ACK : ACK
bits : 5 - 5 (1 bit)

TXERR : TXERR
bits : 7 - 7 (1 bit)

BBERR : BBERR
bits : 8 - 8 (1 bit)

FRMOR : FRMOR
bits : 9 - 9 (1 bit)

DTERR : DTERR
bits : 10 - 10 (1 bit)


HCINTMSK6

This register reflects the mask for each channel status described in the previous section.
address_offset : 0x5CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINTMSK6 HCINTMSK6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM STALLM NAKM ACKM TXERRM BBERRM FRMORM DTERRM

XFRCM : XFRCM
bits : 0 - 0 (1 bit)

CHHM : CHHM
bits : 1 - 1 (1 bit)

STALLM : STALLM
bits : 3 - 3 (1 bit)

NAKM : NAKM
bits : 4 - 4 (1 bit)

ACKM : ACKM
bits : 5 - 5 (1 bit)

TXERRM : TXERRM
bits : 7 - 7 (1 bit)

BBERRM : BBERRM
bits : 8 - 8 (1 bit)

FRMORM : FRMORM
bits : 9 - 9 (1 bit)

DTERRM : DTERRM
bits : 10 - 10 (1 bit)


HCTSIZ6

OTG host channel 6 transfer size register
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCTSIZ6 HCTSIZ6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID DOPNG

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

DPID : DPID
bits : 29 - 30 (2 bit)

DOPNG : DOPNG
bits : 31 - 31 (1 bit)


HCCHAR7

OTG host channel 7 characteristics register
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCCHAR7 HCCHAR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MCNT DAD ODDFRM CHDIS CHENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)

EPNUM : EPNUM
bits : 11 - 14 (4 bit)

EPDIR : EPDIR
bits : 15 - 15 (1 bit)

LSDEV : LSDEV
bits : 17 - 17 (1 bit)

EPTYP : EPTYP
bits : 18 - 19 (2 bit)

MCNT : MCNT
bits : 20 - 21 (2 bit)

DAD : DAD
bits : 22 - 28 (7 bit)

ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)

CHDIS : CHDIS
bits : 30 - 30 (1 bit)

CHENA : CHENA
bits : 31 - 31 (1 bit)


HCINT7

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x5E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINT7 HCINT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH STALL NAK ACK TXERR BBERR FRMOR DTERR

XFRC : XFRC
bits : 0 - 0 (1 bit)

CHH : CHH
bits : 1 - 1 (1 bit)

STALL : STALL
bits : 3 - 3 (1 bit)

NAK : NAK
bits : 4 - 4 (1 bit)

ACK : ACK
bits : 5 - 5 (1 bit)

TXERR : TXERR
bits : 7 - 7 (1 bit)

BBERR : BBERR
bits : 8 - 8 (1 bit)

FRMOR : FRMOR
bits : 9 - 9 (1 bit)

DTERR : DTERR
bits : 10 - 10 (1 bit)


HCINTMSK7

This register reflects the mask for each channel status described in the previous section.
address_offset : 0x5EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINTMSK7 HCINTMSK7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM STALLM NAKM ACKM TXERRM BBERRM FRMORM DTERRM

XFRCM : XFRCM
bits : 0 - 0 (1 bit)

CHHM : CHHM
bits : 1 - 1 (1 bit)

STALLM : STALLM
bits : 3 - 3 (1 bit)

NAKM : NAKM
bits : 4 - 4 (1 bit)

ACKM : ACKM
bits : 5 - 5 (1 bit)

TXERRM : TXERRM
bits : 7 - 7 (1 bit)

BBERRM : BBERRM
bits : 8 - 8 (1 bit)

FRMORM : FRMORM
bits : 9 - 9 (1 bit)

DTERRM : DTERRM
bits : 10 - 10 (1 bit)


HCTSIZ7

OTG host channel 7 transfer size register
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCTSIZ7 HCTSIZ7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID DOPNG

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

DPID : DPID
bits : 29 - 30 (2 bit)

DOPNG : DOPNG
bits : 31 - 31 (1 bit)


HCCHAR8

OTG host channel 8 characteristics register
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCCHAR8 HCCHAR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MCNT DAD ODDFRM CHDIS CHENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)

EPNUM : EPNUM
bits : 11 - 14 (4 bit)

EPDIR : EPDIR
bits : 15 - 15 (1 bit)

LSDEV : LSDEV
bits : 17 - 17 (1 bit)

EPTYP : EPTYP
bits : 18 - 19 (2 bit)

MCNT : MCNT
bits : 20 - 21 (2 bit)

DAD : DAD
bits : 22 - 28 (7 bit)

ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)

CHDIS : CHDIS
bits : 30 - 30 (1 bit)

CHENA : CHENA
bits : 31 - 31 (1 bit)


HCINT8

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINT8 HCINT8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH STALL NAK ACK TXERR BBERR FRMOR DTERR

XFRC : XFRC
bits : 0 - 0 (1 bit)

CHH : CHH
bits : 1 - 1 (1 bit)

STALL : STALL
bits : 3 - 3 (1 bit)

NAK : NAK
bits : 4 - 4 (1 bit)

ACK : ACK
bits : 5 - 5 (1 bit)

TXERR : TXERR
bits : 7 - 7 (1 bit)

BBERR : BBERR
bits : 8 - 8 (1 bit)

FRMOR : FRMOR
bits : 9 - 9 (1 bit)

DTERR : DTERR
bits : 10 - 10 (1 bit)


HCINTMSK8

This register reflects the mask for each channel status described in the previous section.
address_offset : 0x60C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINTMSK8 HCINTMSK8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM STALLM NAKM ACKM TXERRM BBERRM FRMORM DTERRM

XFRCM : XFRCM
bits : 0 - 0 (1 bit)

CHHM : CHHM
bits : 1 - 1 (1 bit)

STALLM : STALLM
bits : 3 - 3 (1 bit)

NAKM : NAKM
bits : 4 - 4 (1 bit)

ACKM : ACKM
bits : 5 - 5 (1 bit)

TXERRM : TXERRM
bits : 7 - 7 (1 bit)

BBERRM : BBERRM
bits : 8 - 8 (1 bit)

FRMORM : FRMORM
bits : 9 - 9 (1 bit)

DTERRM : DTERRM
bits : 10 - 10 (1 bit)


HCTSIZ8

OTG host channel 8 transfer size register
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCTSIZ8 HCTSIZ8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID DOPNG

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

DPID : DPID
bits : 29 - 30 (2 bit)

DOPNG : DOPNG
bits : 31 - 31 (1 bit)


HCCHAR9

OTG host channel 9 characteristics register
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCCHAR9 HCCHAR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MCNT DAD ODDFRM CHDIS CHENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)

EPNUM : EPNUM
bits : 11 - 14 (4 bit)

EPDIR : EPDIR
bits : 15 - 15 (1 bit)

LSDEV : LSDEV
bits : 17 - 17 (1 bit)

EPTYP : EPTYP
bits : 18 - 19 (2 bit)

MCNT : MCNT
bits : 20 - 21 (2 bit)

DAD : DAD
bits : 22 - 28 (7 bit)

ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)

CHDIS : CHDIS
bits : 30 - 30 (1 bit)

CHENA : CHENA
bits : 31 - 31 (1 bit)


HCINT9

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINT9 HCINT9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH STALL NAK ACK TXERR BBERR FRMOR DTERR

XFRC : XFRC
bits : 0 - 0 (1 bit)

CHH : CHH
bits : 1 - 1 (1 bit)

STALL : STALL
bits : 3 - 3 (1 bit)

NAK : NAK
bits : 4 - 4 (1 bit)

ACK : ACK
bits : 5 - 5 (1 bit)

TXERR : TXERR
bits : 7 - 7 (1 bit)

BBERR : BBERR
bits : 8 - 8 (1 bit)

FRMOR : FRMOR
bits : 9 - 9 (1 bit)

DTERR : DTERR
bits : 10 - 10 (1 bit)


HCINTMSK9

This register reflects the mask for each channel status described in the previous section.
address_offset : 0x62C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINTMSK9 HCINTMSK9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM STALLM NAKM ACKM TXERRM BBERRM FRMORM DTERRM

XFRCM : XFRCM
bits : 0 - 0 (1 bit)

CHHM : CHHM
bits : 1 - 1 (1 bit)

STALLM : STALLM
bits : 3 - 3 (1 bit)

NAKM : NAKM
bits : 4 - 4 (1 bit)

ACKM : ACKM
bits : 5 - 5 (1 bit)

TXERRM : TXERRM
bits : 7 - 7 (1 bit)

BBERRM : BBERRM
bits : 8 - 8 (1 bit)

FRMORM : FRMORM
bits : 9 - 9 (1 bit)

DTERRM : DTERRM
bits : 10 - 10 (1 bit)


HCTSIZ9

OTG host channel 9 transfer size register
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCTSIZ9 HCTSIZ9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID DOPNG

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

DPID : DPID
bits : 29 - 30 (2 bit)

DOPNG : DOPNG
bits : 31 - 31 (1 bit)


HCCHAR10

OTG host channel 10 characteristics register
address_offset : 0x640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCCHAR10 HCCHAR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MCNT DAD ODDFRM CHDIS CHENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)

EPNUM : EPNUM
bits : 11 - 14 (4 bit)

EPDIR : EPDIR
bits : 15 - 15 (1 bit)

LSDEV : LSDEV
bits : 17 - 17 (1 bit)

EPTYP : EPTYP
bits : 18 - 19 (2 bit)

MCNT : MCNT
bits : 20 - 21 (2 bit)

DAD : DAD
bits : 22 - 28 (7 bit)

ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)

CHDIS : CHDIS
bits : 30 - 30 (1 bit)

CHENA : CHENA
bits : 31 - 31 (1 bit)


HCINT10

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x648 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINT10 HCINT10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH STALL NAK ACK TXERR BBERR FRMOR DTERR

XFRC : XFRC
bits : 0 - 0 (1 bit)

CHH : CHH
bits : 1 - 1 (1 bit)

STALL : STALL
bits : 3 - 3 (1 bit)

NAK : NAK
bits : 4 - 4 (1 bit)

ACK : ACK
bits : 5 - 5 (1 bit)

TXERR : TXERR
bits : 7 - 7 (1 bit)

BBERR : BBERR
bits : 8 - 8 (1 bit)

FRMOR : FRMOR
bits : 9 - 9 (1 bit)

DTERR : DTERR
bits : 10 - 10 (1 bit)


HCINTMSK10

This register reflects the mask for each channel status described in the previous section.
address_offset : 0x64C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINTMSK10 HCINTMSK10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM STALLM NAKM ACKM TXERRM BBERRM FRMORM DTERRM

XFRCM : XFRCM
bits : 0 - 0 (1 bit)

CHHM : CHHM
bits : 1 - 1 (1 bit)

STALLM : STALLM
bits : 3 - 3 (1 bit)

NAKM : NAKM
bits : 4 - 4 (1 bit)

ACKM : ACKM
bits : 5 - 5 (1 bit)

TXERRM : TXERRM
bits : 7 - 7 (1 bit)

BBERRM : BBERRM
bits : 8 - 8 (1 bit)

FRMORM : FRMORM
bits : 9 - 9 (1 bit)

DTERRM : DTERRM
bits : 10 - 10 (1 bit)


HCTSIZ10

OTG host channel 10 transfer size register
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCTSIZ10 HCTSIZ10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID DOPNG

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

DPID : DPID
bits : 29 - 30 (2 bit)

DOPNG : DOPNG
bits : 31 - 31 (1 bit)


HCCHAR11

OTG host channel 11 characteristics register
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCCHAR11 HCCHAR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ EPNUM EPDIR LSDEV EPTYP MCNT DAD ODDFRM CHDIS CHENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)

EPNUM : EPNUM
bits : 11 - 14 (4 bit)

EPDIR : EPDIR
bits : 15 - 15 (1 bit)

LSDEV : LSDEV
bits : 17 - 17 (1 bit)

EPTYP : EPTYP
bits : 18 - 19 (2 bit)

MCNT : MCNT
bits : 20 - 21 (2 bit)

DAD : DAD
bits : 22 - 28 (7 bit)

ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)

CHDIS : CHDIS
bits : 30 - 30 (1 bit)

CHENA : CHENA
bits : 31 - 31 (1 bit)


HCINT11

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINT11 HCINT11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC CHH STALL NAK ACK TXERR BBERR FRMOR DTERR

XFRC : XFRC
bits : 0 - 0 (1 bit)

CHH : CHH
bits : 1 - 1 (1 bit)

STALL : STALL
bits : 3 - 3 (1 bit)

NAK : NAK
bits : 4 - 4 (1 bit)

ACK : ACK
bits : 5 - 5 (1 bit)

TXERR : TXERR
bits : 7 - 7 (1 bit)

BBERR : BBERR
bits : 8 - 8 (1 bit)

FRMOR : FRMOR
bits : 9 - 9 (1 bit)

DTERR : DTERR
bits : 10 - 10 (1 bit)


HCINTMSK11

This register reflects the mask for each channel status described in the previous section.
address_offset : 0x66C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINTMSK11 HCINTMSK11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM CHHM STALLM NAKM ACKM TXERRM BBERRM FRMORM DTERRM

XFRCM : XFRCM
bits : 0 - 0 (1 bit)

CHHM : CHHM
bits : 1 - 1 (1 bit)

STALLM : STALLM
bits : 3 - 3 (1 bit)

NAKM : NAKM
bits : 4 - 4 (1 bit)

ACKM : ACKM
bits : 5 - 5 (1 bit)

TXERRM : TXERRM
bits : 7 - 7 (1 bit)

BBERRM : BBERRM
bits : 8 - 8 (1 bit)

FRMORM : FRMORM
bits : 9 - 9 (1 bit)

DTERRM : DTERRM
bits : 10 - 10 (1 bit)


HCTSIZ11

OTG host channel 11 transfer size register
address_offset : 0x670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCTSIZ11 HCTSIZ11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT DPID DOPNG

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

DPID : DPID
bits : 29 - 30 (2 bit)

DOPNG : DOPNG
bits : 31 - 31 (1 bit)


GAHBCFG

This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GAHBCFG GAHBCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GINTMSK TXFELVL PTXFELVL

GINTMSK : GINTMSK
bits : 0 - 0 (1 bit)

TXFELVL : TXFELVL
bits : 7 - 7 (1 bit)

PTXFELVL : PTXFELVL
bits : 8 - 8 (1 bit)


DCFG

This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCFG DCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSPD NZLSOHSK DAD PFIVL ERRATIM

DSPD : DSPD
bits : 0 - 1 (2 bit)

NZLSOHSK : NZLSOHSK
bits : 2 - 2 (1 bit)

DAD : DAD
bits : 4 - 10 (7 bit)

PFIVL : PFIVL
bits : 11 - 12 (2 bit)

ERRATIM : ERRATIM
bits : 15 - 15 (1 bit)


DCTL

OTG device control register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCTL DCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWUSIG SDIS GINSTS GONSTS TCTL SGINAK CGINAK SGONAK CGONAK POPRGDNE DSBESLRJCT

RWUSIG : RWUSIG
bits : 0 - 0 (1 bit)
access : read-write

SDIS : SDIS
bits : 1 - 1 (1 bit)
access : read-write

GINSTS : GINSTS
bits : 2 - 2 (1 bit)
access : read-only

GONSTS : GONSTS
bits : 3 - 3 (1 bit)
access : read-only

TCTL : TCTL
bits : 4 - 6 (3 bit)
access : read-write

SGINAK : SGINAK
bits : 7 - 7 (1 bit)
access : write-only

CGINAK : CGINAK
bits : 8 - 8 (1 bit)
access : write-only

SGONAK : SGONAK
bits : 9 - 9 (1 bit)
access : write-only

CGONAK : CGONAK
bits : 10 - 10 (1 bit)
access : write-only

POPRGDNE : POPRGDNE
bits : 11 - 11 (1 bit)
access : read-write

DSBESLRJCT : DSBESLRJCT
bits : 18 - 18 (1 bit)
access : read-write


DSTS

This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (DAINT) register.
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSTS DSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPSTS ENUMSPD EERR FNSOF DEVLNSTS

SUSPSTS : SUSPSTS
bits : 0 - 0 (1 bit)

ENUMSPD : ENUMSPD
bits : 1 - 2 (2 bit)

EERR : EERR
bits : 3 - 3 (1 bit)

FNSOF : FNSOF
bits : 8 - 21 (14 bit)

DEVLNSTS : DEVLNSTS
bits : 22 - 23 (2 bit)


DIEPMSK

This register works with each of the DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPMSK DIEPMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM EPDM TOM ITTXFEMSK INEPNMM INEPNEM NAKM

XFRCM : XFRCM
bits : 0 - 0 (1 bit)

EPDM : EPDM
bits : 1 - 1 (1 bit)

TOM : TOM
bits : 3 - 3 (1 bit)

ITTXFEMSK : ITTXFEMSK
bits : 4 - 4 (1 bit)

INEPNMM : INEPNMM
bits : 5 - 5 (1 bit)

INEPNEM : INEPNEM
bits : 6 - 6 (1 bit)

NAKM : NAKM
bits : 13 - 13 (1 bit)


DOEPMSK

This register works with each of the DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPMSK DOEPMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRCM EPDM STUPM OTEPDM STSPHSRXM OUTPKTERRM BERRM NAKMSK

XFRCM : XFRCM
bits : 0 - 0 (1 bit)

EPDM : EPDM
bits : 1 - 1 (1 bit)

STUPM : STUPM
bits : 3 - 3 (1 bit)

OTEPDM : OTEPDM
bits : 4 - 4 (1 bit)

STSPHSRXM : STSPHSRXM
bits : 5 - 5 (1 bit)

OUTPKTERRM : OUTPKTERRM
bits : 8 - 8 (1 bit)

BERRM : BERRM
bits : 12 - 12 (1 bit)

NAKMSK : NAKMSK
bits : 13 - 13 (1 bit)


DAINT

When a significant event occurs on an endpoint, a DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the GINTSTS register (OEPINT or IEPINT in GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding device endpoint-x interrupt register (DIEPINTx/DOEPINTx).
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DAINT DAINT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEPINT OEPINT

IEPINT : IEPINT
bits : 0 - 15 (16 bit)

OEPINT : OEPINT
bits : 16 - 31 (16 bit)


DAINTMSK

The DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the DAINT register bit corresponding to that interrupt is still set.
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAINTMSK DAINTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEPM OEPM

IEPM : IEPM
bits : 0 - 15 (16 bit)

OEPM : OEPM
bits : 16 - 31 (16 bit)


DVBUSDIS

This register specifies the VBUS discharge time after VBUS pulsing during SRP.
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DVBUSDIS DVBUSDIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBUSDT

VBUSDT : VBUSDT
bits : 0 - 15 (16 bit)


DVBUSPULSE

This register specifies the VBUS pulsing time during SRP.
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DVBUSPULSE DVBUSPULSE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DVBUSP

DVBUSP : DVBUSP
bits : 0 - 15 (16 bit)


DIEPEMPMSK

This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx).
address_offset : 0x834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPEMPMSK DIEPEMPMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTXFEM

INEPTXFEM : INEPTXFEM
bits : 0 - 15 (16 bit)


DIEPCTL0

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPCTL0 DIEPCTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP NAKSTS EPTYP STALL TXFNUM CNAK SNAK EPDIS EPENA

MPSIZ : MPSIZ
bits : 0 - 1 (2 bit)
access : read-write

USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-only

NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write

STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TXFNUM
bits : 22 - 25 (4 bit)
access : read-write

CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only

EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write

EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write


DIEPINT0

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0x908 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPINT0 DIEPINT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD TOC ITTXFE INEPNM INEPNE TXFE PKTDRPSTS NAK

XFRC : XFRC
bits : 0 - 0 (1 bit)
access : read-write

EPDISD : EPDISD
bits : 1 - 1 (1 bit)
access : read-write

TOC : TOC
bits : 3 - 3 (1 bit)
access : read-write

ITTXFE : ITTXFE
bits : 4 - 4 (1 bit)
access : read-write

INEPNM : INEPNM
bits : 5 - 5 (1 bit)
access : read-write

INEPNE : INEPNE
bits : 6 - 6 (1 bit)
access : read-only

TXFE : TXFE
bits : 7 - 7 (1 bit)
access : read-only

PKTDRPSTS : PKTDRPSTS
bits : 11 - 11 (1 bit)
access : read-write

NAK : NAK
bits : 13 - 13 (1 bit)
access : read-write


DIEPTSIZ0

The application must modify this register before enabling endpoint 0.
address_offset : 0x910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTSIZ0 DIEPTSIZ0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT

XFRSIZ : XFRSIZ
bits : 0 - 6 (7 bit)

PKTCNT : PKTCNT
bits : 19 - 20 (2 bit)


DTXFSTS0

This read-only register contains the free space information for the device IN endpoint Tx FIFO.
address_offset : 0x918 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DTXFSTS0 DTXFSTS0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTFSAV

INEPTFSAV : INEPTFSAV
bits : 0 - 15 (16 bit)


DIEPCTL1

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0x920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPCTL1 DIEPCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPIP NAKSTS EPTYP STALL TXFNUM CNAK SNAK SD0PID_SEVNFRM SODDFRM EPDIS EPENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write

STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TXFNUM
bits : 22 - 25 (4 bit)
access : read-write

CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only

SODDFRM : SODDFRM
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write

EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write


DIEPINT1

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPINT1 DIEPINT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD TOC ITTXFE INEPNM INEPNE TXFE PKTDRPSTS NAK

XFRC : XFRC
bits : 0 - 0 (1 bit)
access : read-write

EPDISD : EPDISD
bits : 1 - 1 (1 bit)
access : read-write

TOC : TOC
bits : 3 - 3 (1 bit)
access : read-write

ITTXFE : ITTXFE
bits : 4 - 4 (1 bit)
access : read-write

INEPNM : INEPNM
bits : 5 - 5 (1 bit)
access : read-write

INEPNE : INEPNE
bits : 6 - 6 (1 bit)
access : read-only

TXFE : TXFE
bits : 7 - 7 (1 bit)
access : read-only

PKTDRPSTS : PKTDRPSTS
bits : 11 - 11 (1 bit)
access : read-write

NAK : NAK
bits : 13 - 13 (1 bit)
access : read-write


DIEPTSIZ1

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0x930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTSIZ1 DIEPTSIZ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT MCNT

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

MCNT : MCNT
bits : 29 - 30 (2 bit)


DIEPDMA1

OTG device IN endpoint 1 DMA address register
address_offset : 0x934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPDMA1 DIEPDMA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)


DTXFSTS1

This read-only register contains the free space information for the device IN endpoint Tx FIFO.
address_offset : 0x938 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DTXFSTS1 DTXFSTS1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTFSAV

INEPTFSAV : INEPTFSAV
bits : 0 - 15 (16 bit)


DIEPCTL2

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0x940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPCTL2 DIEPCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPIP NAKSTS EPTYP STALL TXFNUM CNAK SNAK SD0PID_SEVNFRM SODDFRM EPDIS EPENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write

STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TXFNUM
bits : 22 - 25 (4 bit)
access : read-write

CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only

SODDFRM : SODDFRM
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write

EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write


DIEPINT2

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0x948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPINT2 DIEPINT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD TOC ITTXFE INEPNM INEPNE TXFE PKTDRPSTS NAK

XFRC : XFRC
bits : 0 - 0 (1 bit)
access : read-write

EPDISD : EPDISD
bits : 1 - 1 (1 bit)
access : read-write

TOC : TOC
bits : 3 - 3 (1 bit)
access : read-write

ITTXFE : ITTXFE
bits : 4 - 4 (1 bit)
access : read-write

INEPNM : INEPNM
bits : 5 - 5 (1 bit)
access : read-write

INEPNE : INEPNE
bits : 6 - 6 (1 bit)
access : read-only

TXFE : TXFE
bits : 7 - 7 (1 bit)
access : read-only

PKTDRPSTS : PKTDRPSTS
bits : 11 - 11 (1 bit)
access : read-write

NAK : NAK
bits : 13 - 13 (1 bit)
access : read-write


DIEPTSIZ2

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0x950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTSIZ2 DIEPTSIZ2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT MCNT

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

MCNT : MCNT
bits : 29 - 30 (2 bit)


DIEPDMA2

OTG device IN endpoint 2 DMA address register
address_offset : 0x954 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPDMA2 DIEPDMA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)


DTXFSTS2

This read-only register contains the free space information for the device IN endpoint Tx FIFO.
address_offset : 0x958 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DTXFSTS2 DTXFSTS2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTFSAV

INEPTFSAV : INEPTFSAV
bits : 0 - 15 (16 bit)


DIEPCTL3

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0x960 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPCTL3 DIEPCTL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPIP NAKSTS EPTYP STALL TXFNUM CNAK SNAK SD0PID_SEVNFRM SODDFRM EPDIS EPENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write

STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TXFNUM
bits : 22 - 25 (4 bit)
access : read-write

CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only

SODDFRM : SODDFRM
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write

EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write


DIEPINT3

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0x968 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPINT3 DIEPINT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD TOC ITTXFE INEPNM INEPNE TXFE PKTDRPSTS NAK

XFRC : XFRC
bits : 0 - 0 (1 bit)
access : read-write

EPDISD : EPDISD
bits : 1 - 1 (1 bit)
access : read-write

TOC : TOC
bits : 3 - 3 (1 bit)
access : read-write

ITTXFE : ITTXFE
bits : 4 - 4 (1 bit)
access : read-write

INEPNM : INEPNM
bits : 5 - 5 (1 bit)
access : read-write

INEPNE : INEPNE
bits : 6 - 6 (1 bit)
access : read-only

TXFE : TXFE
bits : 7 - 7 (1 bit)
access : read-only

PKTDRPSTS : PKTDRPSTS
bits : 11 - 11 (1 bit)
access : read-write

NAK : NAK
bits : 13 - 13 (1 bit)
access : read-write


DIEPTSIZ3

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0x970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTSIZ3 DIEPTSIZ3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT MCNT

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

MCNT : MCNT
bits : 29 - 30 (2 bit)


DIEPDMA3

OTG device IN endpoint 3 DMA address register
address_offset : 0x974 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPDMA3 DIEPDMA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)


DTXFSTS3

This read-only register contains the free space information for the device IN endpoint Tx FIFO.
address_offset : 0x978 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DTXFSTS3 DTXFSTS3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTFSAV

INEPTFSAV : INEPTFSAV
bits : 0 - 15 (16 bit)


DIEPCTL4

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0x980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPCTL4 DIEPCTL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPIP NAKSTS EPTYP STALL TXFNUM CNAK SNAK SD0PID_SEVNFRM SODDFRM EPDIS EPENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write

STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TXFNUM
bits : 22 - 25 (4 bit)
access : read-write

CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only

SODDFRM : SODDFRM
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write

EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write


DIEPINT4

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0x988 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPINT4 DIEPINT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD TOC ITTXFE INEPNM INEPNE TXFE PKTDRPSTS NAK

XFRC : XFRC
bits : 0 - 0 (1 bit)
access : read-write

EPDISD : EPDISD
bits : 1 - 1 (1 bit)
access : read-write

TOC : TOC
bits : 3 - 3 (1 bit)
access : read-write

ITTXFE : ITTXFE
bits : 4 - 4 (1 bit)
access : read-write

INEPNM : INEPNM
bits : 5 - 5 (1 bit)
access : read-write

INEPNE : INEPNE
bits : 6 - 6 (1 bit)
access : read-only

TXFE : TXFE
bits : 7 - 7 (1 bit)
access : read-only

PKTDRPSTS : PKTDRPSTS
bits : 11 - 11 (1 bit)
access : read-write

NAK : NAK
bits : 13 - 13 (1 bit)
access : read-write


DIEPTSIZ4

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0x990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTSIZ4 DIEPTSIZ4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT MCNT

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

MCNT : MCNT
bits : 29 - 30 (2 bit)


DIEPDMA4

OTG device IN endpoint 4 DMA address register
address_offset : 0x994 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPDMA4 DIEPDMA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)


DTXFSTS4

This read-only register contains the free space information for the device IN endpoint Tx FIFO.
address_offset : 0x998 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DTXFSTS4 DTXFSTS4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTFSAV

INEPTFSAV : INEPTFSAV
bits : 0 - 15 (16 bit)


DIEPCTL5

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0x9A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPCTL5 DIEPCTL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPIP NAKSTS EPTYP STALL TXFNUM CNAK SNAK SD0PID_SEVNFRM SODDFRM EPDIS EPENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write

STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TXFNUM
bits : 22 - 25 (4 bit)
access : read-write

CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only

SODDFRM : SODDFRM
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write

EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write


DIEPINT5

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0x9A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPINT5 DIEPINT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD TOC ITTXFE INEPNM INEPNE TXFE PKTDRPSTS NAK

XFRC : XFRC
bits : 0 - 0 (1 bit)
access : read-write

EPDISD : EPDISD
bits : 1 - 1 (1 bit)
access : read-write

TOC : TOC
bits : 3 - 3 (1 bit)
access : read-write

ITTXFE : ITTXFE
bits : 4 - 4 (1 bit)
access : read-write

INEPNM : INEPNM
bits : 5 - 5 (1 bit)
access : read-write

INEPNE : INEPNE
bits : 6 - 6 (1 bit)
access : read-only

TXFE : TXFE
bits : 7 - 7 (1 bit)
access : read-only

PKTDRPSTS : PKTDRPSTS
bits : 11 - 11 (1 bit)
access : read-write

NAK : NAK
bits : 13 - 13 (1 bit)
access : read-write


DIEPTSIZ5

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0x9B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTSIZ5 DIEPTSIZ5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT MCNT

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

MCNT : MCNT
bits : 29 - 30 (2 bit)


DIEPDMA5

OTG device IN endpoint 5 DMA address register
address_offset : 0x9B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPDMA5 DIEPDMA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)


DTXFSTS5

This read-only register contains the free space information for the device IN endpoint Tx FIFO.
address_offset : 0x9B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DTXFSTS5 DTXFSTS5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTFSAV

INEPTFSAV : INEPTFSAV
bits : 0 - 15 (16 bit)


DIEPINT6

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0x9C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPINT6 DIEPINT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD AHBERR TOC ITTXFE INEPNM INEPNE TXFE TXFIFOUDRN BNA PKTDRPSTS NAK

XFRC : XFRC
bits : 0 - 0 (1 bit)
access : read-write

EPDISD : EPDISD
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHBERR
bits : 2 - 2 (1 bit)
access : read-write

TOC : TOC
bits : 3 - 3 (1 bit)
access : read-write

ITTXFE : ITTXFE
bits : 4 - 4 (1 bit)
access : read-write

INEPNM : INEPNM
bits : 5 - 5 (1 bit)
access : read-write

INEPNE : INEPNE
bits : 6 - 6 (1 bit)
access : read-only

TXFE : TXFE
bits : 7 - 7 (1 bit)
access : read-only

TXFIFOUDRN : TXFIFOUDRN
bits : 8 - 8 (1 bit)
access : read-write

BNA : BNA
bits : 9 - 9 (1 bit)
access : read-write

PKTDRPSTS : PKTDRPSTS
bits : 11 - 11 (1 bit)
access : read-write

NAK : NAK
bits : 13 - 13 (1 bit)
access : read-write


DIEPTSIZ6

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0x9D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTSIZ6 DIEPTSIZ6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT MCNT

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

MCNT : MCNT
bits : 29 - 30 (2 bit)


DIEPDMA6

OTG device IN endpoint 6 DMA address register
address_offset : 0x9D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPDMA6 DIEPDMA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)


DIEPINT7

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0x9E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPINT7 DIEPINT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD AHBERR TOC ITTXFE INEPNM INEPNE TXFE TXFIFOUDRN BNA PKTDRPSTS NAK

XFRC : XFRC
bits : 0 - 0 (1 bit)
access : read-write

EPDISD : EPDISD
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHBERR
bits : 2 - 2 (1 bit)
access : read-write

TOC : TOC
bits : 3 - 3 (1 bit)
access : read-write

ITTXFE : ITTXFE
bits : 4 - 4 (1 bit)
access : read-write

INEPNM : INEPNM
bits : 5 - 5 (1 bit)
access : read-write

INEPNE : INEPNE
bits : 6 - 6 (1 bit)
access : read-only

TXFE : TXFE
bits : 7 - 7 (1 bit)
access : read-only

TXFIFOUDRN : TXFIFOUDRN
bits : 8 - 8 (1 bit)
access : read-write

BNA : BNA
bits : 9 - 9 (1 bit)
access : read-write

PKTDRPSTS : PKTDRPSTS
bits : 11 - 11 (1 bit)
access : read-write

NAK : NAK
bits : 13 - 13 (1 bit)
access : read-write


DIEPTSIZ7

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0x9F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTSIZ7 DIEPTSIZ7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT MCNT

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

MCNT : MCNT
bits : 29 - 30 (2 bit)


DIEPDMA7

OTG device IN endpoint 7 DMA address register
address_offset : 0x9F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPDMA7 DIEPDMA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)


DIEPINT8

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0xA08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPINT8 DIEPINT8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD AHBERR TOC ITTXFE INEPNM INEPNE TXFE TXFIFOUDRN BNA PKTDRPSTS NAK

XFRC : XFRC
bits : 0 - 0 (1 bit)
access : read-write

EPDISD : EPDISD
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHBERR
bits : 2 - 2 (1 bit)
access : read-write

TOC : TOC
bits : 3 - 3 (1 bit)
access : read-write

ITTXFE : ITTXFE
bits : 4 - 4 (1 bit)
access : read-write

INEPNM : INEPNM
bits : 5 - 5 (1 bit)
access : read-write

INEPNE : INEPNE
bits : 6 - 6 (1 bit)
access : read-only

TXFE : TXFE
bits : 7 - 7 (1 bit)
access : read-only

TXFIFOUDRN : TXFIFOUDRN
bits : 8 - 8 (1 bit)
access : read-write

BNA : BNA
bits : 9 - 9 (1 bit)
access : read-write

PKTDRPSTS : PKTDRPSTS
bits : 11 - 11 (1 bit)
access : read-write

NAK : NAK
bits : 13 - 13 (1 bit)
access : read-write


DIEPTSIZ8

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0xA10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTSIZ8 DIEPTSIZ8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT MCNT

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

MCNT : MCNT
bits : 29 - 30 (2 bit)


DIEPDMA8

OTG device IN endpoint 8 DMA address register
address_offset : 0xA14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPDMA8 DIEPDMA8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)


DOEPCTL0

This section describes the DOEPCTL0 register.
address_offset : 0xB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPCTL0 DOEPCTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP NAKSTS EPTYP SNPM STALL CNAK SNAK EPDIS EPENA

MPSIZ : MPSIZ
bits : 0 - 1 (2 bit)
access : read-only

USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-only

NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-only

SNPM : SNPM
bits : 20 - 20 (1 bit)
access : read-write

STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write

CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only

EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-only

EPENA : EPENA
bits : 31 - 31 (1 bit)
access : write-only


DOEPINT0

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0xB08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPINT0 DOEPINT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD AHBERR STUP OTEPDIS STSPHSRX B2BSTUP OUTPKTERR BNA BERR NAK NYET STPKTRX

XFRC : XFRC
bits : 0 - 0 (1 bit)

EPDISD : EPDISD
bits : 1 - 1 (1 bit)

AHBERR : AHBERR
bits : 2 - 2 (1 bit)

STUP : STUP
bits : 3 - 3 (1 bit)

OTEPDIS : OTEPDIS
bits : 4 - 4 (1 bit)

STSPHSRX : STSPHSRX
bits : 5 - 5 (1 bit)

B2BSTUP : B2BSTUP
bits : 6 - 6 (1 bit)

OUTPKTERR : OUTPKTERR
bits : 8 - 8 (1 bit)

BNA : BNA
bits : 9 - 9 (1 bit)

BERR : BERR
bits : 12 - 12 (1 bit)

NAK : NAK
bits : 13 - 13 (1 bit)

NYET : NYET
bits : 14 - 14 (1 bit)

STPKTRX : STPKTRX
bits : 15 - 15 (1 bit)


DOEPTSIZ0

The application must modify this register before enabling endpoint 0.
address_offset : 0xB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPTSIZ0 DOEPTSIZ0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT STUPCNT

XFRSIZ : XFRSIZ
bits : 0 - 6 (7 bit)

PKTCNT : PKTCNT
bits : 19 - 19 (1 bit)

STUPCNT : STUPCNT
bits : 29 - 30 (2 bit)


DOEPDMA0

OTG device OUT endpoint 0 DMA address register
address_offset : 0xB14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPDMA0 DOEPDMA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)


DOEPCTL1

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPCTL1 DOEPCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPIP NAKSTS EPTYP SNPM STALL CNAK SNAK SD0PID_SEVNFRM SD1PID_SODDFRM EPDIS EPENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write

SNPM : SNPM
bits : 20 - 20 (1 bit)
access : read-write

STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write

CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only

SD1PID_SODDFRM : SD1PID_SODDFRM
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write

EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write


DOEPINT1

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0xB28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPINT1 DOEPINT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD AHBERR STUP OTEPDIS STSPHSRX B2BSTUP OUTPKTERR BNA BERR NAK NYET STPKTRX

XFRC : XFRC
bits : 0 - 0 (1 bit)

EPDISD : EPDISD
bits : 1 - 1 (1 bit)

AHBERR : AHBERR
bits : 2 - 2 (1 bit)

STUP : STUP
bits : 3 - 3 (1 bit)

OTEPDIS : OTEPDIS
bits : 4 - 4 (1 bit)

STSPHSRX : STSPHSRX
bits : 5 - 5 (1 bit)

B2BSTUP : B2BSTUP
bits : 6 - 6 (1 bit)

OUTPKTERR : OUTPKTERR
bits : 8 - 8 (1 bit)

BNA : BNA
bits : 9 - 9 (1 bit)

BERR : BERR
bits : 12 - 12 (1 bit)

NAK : NAK
bits : 13 - 13 (1 bit)

NYET : NYET
bits : 14 - 14 (1 bit)

STPKTRX : STPKTRX
bits : 15 - 15 (1 bit)


DOEPTSIZ1

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0xB30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPTSIZ1 DOEPTSIZ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT RXDPID_STUPCNT

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

RXDPID_STUPCNT : RXDPID_STUPCNT
bits : 29 - 30 (2 bit)


DOEPDMA1

OTG device OUT endpoint 1 DMA address register
address_offset : 0xB34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPDMA1 DOEPDMA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)


DOEPCTL2

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0xB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPCTL2 DOEPCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPIP NAKSTS EPTYP SNPM STALL CNAK SNAK SD0PID_SEVNFRM SD1PID_SODDFRM EPDIS EPENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write

SNPM : SNPM
bits : 20 - 20 (1 bit)
access : read-write

STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write

CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only

SD1PID_SODDFRM : SD1PID_SODDFRM
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write

EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write


DOEPINT2

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0xB48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPINT2 DOEPINT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD AHBERR STUP OTEPDIS STSPHSRX B2BSTUP OUTPKTERR BNA BERR NAK NYET STPKTRX

XFRC : XFRC
bits : 0 - 0 (1 bit)

EPDISD : EPDISD
bits : 1 - 1 (1 bit)

AHBERR : AHBERR
bits : 2 - 2 (1 bit)

STUP : STUP
bits : 3 - 3 (1 bit)

OTEPDIS : OTEPDIS
bits : 4 - 4 (1 bit)

STSPHSRX : STSPHSRX
bits : 5 - 5 (1 bit)

B2BSTUP : B2BSTUP
bits : 6 - 6 (1 bit)

OUTPKTERR : OUTPKTERR
bits : 8 - 8 (1 bit)

BNA : BNA
bits : 9 - 9 (1 bit)

BERR : BERR
bits : 12 - 12 (1 bit)

NAK : NAK
bits : 13 - 13 (1 bit)

NYET : NYET
bits : 14 - 14 (1 bit)

STPKTRX : STPKTRX
bits : 15 - 15 (1 bit)


DOEPTSIZ2

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0xB50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPTSIZ2 DOEPTSIZ2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT RXDPID_STUPCNT

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

RXDPID_STUPCNT : RXDPID_STUPCNT
bits : 29 - 30 (2 bit)


DOEPDMA2

OTG device OUT endpoint 2 DMA address register
address_offset : 0xB54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPDMA2 DOEPDMA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)


DOEPCTL3

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0xB60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPCTL3 DOEPCTL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPIP NAKSTS EPTYP SNPM STALL CNAK SNAK SD0PID_SEVNFRM SD1PID_SODDFRM EPDIS EPENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write

SNPM : SNPM
bits : 20 - 20 (1 bit)
access : read-write

STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write

CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only

SD1PID_SODDFRM : SD1PID_SODDFRM
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write

EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write


DOEPINT3

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0xB68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPINT3 DOEPINT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD AHBERR STUP OTEPDIS STSPHSRX B2BSTUP OUTPKTERR BNA BERR NAK NYET STPKTRX

XFRC : XFRC
bits : 0 - 0 (1 bit)

EPDISD : EPDISD
bits : 1 - 1 (1 bit)

AHBERR : AHBERR
bits : 2 - 2 (1 bit)

STUP : STUP
bits : 3 - 3 (1 bit)

OTEPDIS : OTEPDIS
bits : 4 - 4 (1 bit)

STSPHSRX : STSPHSRX
bits : 5 - 5 (1 bit)

B2BSTUP : B2BSTUP
bits : 6 - 6 (1 bit)

OUTPKTERR : OUTPKTERR
bits : 8 - 8 (1 bit)

BNA : BNA
bits : 9 - 9 (1 bit)

BERR : BERR
bits : 12 - 12 (1 bit)

NAK : NAK
bits : 13 - 13 (1 bit)

NYET : NYET
bits : 14 - 14 (1 bit)

STPKTRX : STPKTRX
bits : 15 - 15 (1 bit)


DOEPTSIZ3

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0xB70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPTSIZ3 DOEPTSIZ3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT RXDPID_STUPCNT

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

RXDPID_STUPCNT : RXDPID_STUPCNT
bits : 29 - 30 (2 bit)


DOEPDMA3

OTG device OUT endpoint 3 DMA address register
address_offset : 0xB74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPDMA3 DOEPDMA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)


DOEPCTL4

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0xB80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPCTL4 DOEPCTL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPIP NAKSTS EPTYP SNPM STALL CNAK SNAK SD0PID_SEVNFRM SD1PID_SODDFRM EPDIS EPENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write

SNPM : SNPM
bits : 20 - 20 (1 bit)
access : read-write

STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write

CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only

SD1PID_SODDFRM : SD1PID_SODDFRM
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write

EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write


DOEPINT4

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0xB88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPINT4 DOEPINT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD AHBERR STUP OTEPDIS STSPHSRX B2BSTUP OUTPKTERR BNA BERR NAK NYET STPKTRX

XFRC : XFRC
bits : 0 - 0 (1 bit)

EPDISD : EPDISD
bits : 1 - 1 (1 bit)

AHBERR : AHBERR
bits : 2 - 2 (1 bit)

STUP : STUP
bits : 3 - 3 (1 bit)

OTEPDIS : OTEPDIS
bits : 4 - 4 (1 bit)

STSPHSRX : STSPHSRX
bits : 5 - 5 (1 bit)

B2BSTUP : B2BSTUP
bits : 6 - 6 (1 bit)

OUTPKTERR : OUTPKTERR
bits : 8 - 8 (1 bit)

BNA : BNA
bits : 9 - 9 (1 bit)

BERR : BERR
bits : 12 - 12 (1 bit)

NAK : NAK
bits : 13 - 13 (1 bit)

NYET : NYET
bits : 14 - 14 (1 bit)

STPKTRX : STPKTRX
bits : 15 - 15 (1 bit)


DOEPTSIZ4

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0xB90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPTSIZ4 DOEPTSIZ4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT RXDPID_STUPCNT

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

RXDPID_STUPCNT : RXDPID_STUPCNT
bits : 29 - 30 (2 bit)


DOEPDMA4

OTG device OUT endpoint 4 DMA address register
address_offset : 0xB94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPDMA4 DOEPDMA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)


DOEPCTL5

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0xBA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPCTL5 DOEPCTL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPIP NAKSTS EPTYP SNPM STALL CNAK SNAK SD0PID_SEVNFRM SD1PID_SODDFRM EPDIS EPENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write

SNPM : SNPM
bits : 20 - 20 (1 bit)
access : read-write

STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write

CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only

SD1PID_SODDFRM : SD1PID_SODDFRM
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write

EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write


DOEPINT5

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0xBA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPINT5 DOEPINT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD AHBERR STUP OTEPDIS STSPHSRX B2BSTUP OUTPKTERR BNA BERR NAK NYET STPKTRX

XFRC : XFRC
bits : 0 - 0 (1 bit)

EPDISD : EPDISD
bits : 1 - 1 (1 bit)

AHBERR : AHBERR
bits : 2 - 2 (1 bit)

STUP : STUP
bits : 3 - 3 (1 bit)

OTEPDIS : OTEPDIS
bits : 4 - 4 (1 bit)

STSPHSRX : STSPHSRX
bits : 5 - 5 (1 bit)

B2BSTUP : B2BSTUP
bits : 6 - 6 (1 bit)

OUTPKTERR : OUTPKTERR
bits : 8 - 8 (1 bit)

BNA : BNA
bits : 9 - 9 (1 bit)

BERR : BERR
bits : 12 - 12 (1 bit)

NAK : NAK
bits : 13 - 13 (1 bit)

NYET : NYET
bits : 14 - 14 (1 bit)

STPKTRX : STPKTRX
bits : 15 - 15 (1 bit)


DOEPTSIZ5

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0xBB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPTSIZ5 DOEPTSIZ5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT RXDPID_STUPCNT

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

RXDPID_STUPCNT : RXDPID_STUPCNT
bits : 29 - 30 (2 bit)


DOEPDMA5

OTG device OUT endpoint 5 DMA address register
address_offset : 0xBB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPDMA5 DOEPDMA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)


DOEPCTL6

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0xBC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPCTL6 DOEPCTL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPIP NAKSTS EPTYP SNPM STALL CNAK SNAK SD0PID_SEVNFRM SD1PID_SODDFRM EPDIS EPENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write

SNPM : SNPM
bits : 20 - 20 (1 bit)
access : read-write

STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write

CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only

SD1PID_SODDFRM : SD1PID_SODDFRM
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write

EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write


DOEPINT6

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0xBC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPINT6 DOEPINT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD AHBERR STUP OTEPDIS STSPHSRX B2BSTUP OUTPKTERR BNA BERR NAK NYET STPKTRX

XFRC : XFRC
bits : 0 - 0 (1 bit)

EPDISD : EPDISD
bits : 1 - 1 (1 bit)

AHBERR : AHBERR
bits : 2 - 2 (1 bit)

STUP : STUP
bits : 3 - 3 (1 bit)

OTEPDIS : OTEPDIS
bits : 4 - 4 (1 bit)

STSPHSRX : STSPHSRX
bits : 5 - 5 (1 bit)

B2BSTUP : B2BSTUP
bits : 6 - 6 (1 bit)

OUTPKTERR : OUTPKTERR
bits : 8 - 8 (1 bit)

BNA : BNA
bits : 9 - 9 (1 bit)

BERR : BERR
bits : 12 - 12 (1 bit)

NAK : NAK
bits : 13 - 13 (1 bit)

NYET : NYET
bits : 14 - 14 (1 bit)

STPKTRX : STPKTRX
bits : 15 - 15 (1 bit)


DOEPTSIZ6

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0xBD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPTSIZ6 DOEPTSIZ6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT RXDPID_STUPCNT

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

RXDPID_STUPCNT : RXDPID_STUPCNT
bits : 29 - 30 (2 bit)


DOEPDMA6

OTG device OUT endpoint 6 DMA address register
address_offset : 0xBD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPDMA6 DOEPDMA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)


DOEPCTL7

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0xBE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPCTL7 DOEPCTL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPIP NAKSTS EPTYP SNPM STALL CNAK SNAK SD0PID_SEVNFRM SD1PID_SODDFRM EPDIS EPENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write

SNPM : SNPM
bits : 20 - 20 (1 bit)
access : read-write

STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write

CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only

SD1PID_SODDFRM : SD1PID_SODDFRM
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write

EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write


DOEPINT7

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0xBE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPINT7 DOEPINT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD AHBERR STUP OTEPDIS STSPHSRX B2BSTUP OUTPKTERR BNA BERR NAK NYET STPKTRX

XFRC : XFRC
bits : 0 - 0 (1 bit)

EPDISD : EPDISD
bits : 1 - 1 (1 bit)

AHBERR : AHBERR
bits : 2 - 2 (1 bit)

STUP : STUP
bits : 3 - 3 (1 bit)

OTEPDIS : OTEPDIS
bits : 4 - 4 (1 bit)

STSPHSRX : STSPHSRX
bits : 5 - 5 (1 bit)

B2BSTUP : B2BSTUP
bits : 6 - 6 (1 bit)

OUTPKTERR : OUTPKTERR
bits : 8 - 8 (1 bit)

BNA : BNA
bits : 9 - 9 (1 bit)

BERR : BERR
bits : 12 - 12 (1 bit)

NAK : NAK
bits : 13 - 13 (1 bit)

NYET : NYET
bits : 14 - 14 (1 bit)

STPKTRX : STPKTRX
bits : 15 - 15 (1 bit)


DOEPTSIZ7

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0xBF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPTSIZ7 DOEPTSIZ7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT RXDPID_STUPCNT

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

RXDPID_STUPCNT : RXDPID_STUPCNT
bits : 29 - 30 (2 bit)


DOEPDMA7

OTG device OUT endpoint 7 DMA address register
address_offset : 0xBF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPDMA7 DOEPDMA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)


GUSBCFG

This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GUSBCFG GUSBCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOCAL PHYSEL SRPCAP HNPCAP TRDT FHMOD FDMOD

TOCAL : TOCAL
bits : 0 - 2 (3 bit)
access : read-write

PHYSEL : PHYSEL
bits : 6 - 6 (1 bit)
access : read-only

SRPCAP : SRPCAP
bits : 8 - 8 (1 bit)
access : read-write

HNPCAP : HNPCAP
bits : 9 - 9 (1 bit)
access : read-write

TRDT : TRDT
bits : 10 - 13 (4 bit)
access : read-write

FHMOD : FHMOD
bits : 29 - 29 (1 bit)
access : read-write

FDMOD : FDMOD
bits : 30 - 30 (1 bit)
access : read-write


DOEPCTL8

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPCTL8 DOEPCTL8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ USBAEP EONUM_DPIP NAKSTS EPTYP SNPM STALL CNAK SNAK SD0PID_SEVNFRM SD1PID_SODDFRM EPDIS EPENA

MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write

USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write

EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only

EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write

SNPM : SNPM
bits : 20 - 20 (1 bit)
access : read-write

STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write

CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only

SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only

SD1PID_SODDFRM : SD1PID_SODDFRM
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write

EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write


DOEPINT8

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0xC08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPINT8 DOEPINT8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRC EPDISD AHBERR STUP OTEPDIS STSPHSRX B2BSTUP OUTPKTERR BNA BERR NAK NYET STPKTRX

XFRC : XFRC
bits : 0 - 0 (1 bit)

EPDISD : EPDISD
bits : 1 - 1 (1 bit)

AHBERR : AHBERR
bits : 2 - 2 (1 bit)

STUP : STUP
bits : 3 - 3 (1 bit)

OTEPDIS : OTEPDIS
bits : 4 - 4 (1 bit)

STSPHSRX : STSPHSRX
bits : 5 - 5 (1 bit)

B2BSTUP : B2BSTUP
bits : 6 - 6 (1 bit)

OUTPKTERR : OUTPKTERR
bits : 8 - 8 (1 bit)

BNA : BNA
bits : 9 - 9 (1 bit)

BERR : BERR
bits : 12 - 12 (1 bit)

NAK : NAK
bits : 13 - 13 (1 bit)

NYET : NYET
bits : 14 - 14 (1 bit)

STPKTRX : STPKTRX
bits : 15 - 15 (1 bit)


DOEPTSIZ8

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0xC10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPTSIZ8 DOEPTSIZ8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ PKTCNT RXDPID_STUPCNT

XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)

PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)

RXDPID_STUPCNT : RXDPID_STUPCNT
bits : 29 - 30 (2 bit)


DOEPDMA8

OTG device OUT endpoint 8 DMA address register
address_offset : 0xC14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPDMA8 DOEPDMA8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)


PCGCCTL

This register is available in host and device modes.
address_offset : 0xE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCGCCTL PCGCCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STPPCLK GATEHCLK PHYSUSP ENL1GTG PHYSLEEP SUSP

STPPCLK : STPPCLK
bits : 0 - 0 (1 bit)
access : read-write

GATEHCLK : GATEHCLK
bits : 1 - 1 (1 bit)
access : read-write

PHYSUSP : PHYSUSP
bits : 4 - 4 (1 bit)
access : read-only

ENL1GTG : ENL1GTG
bits : 5 - 5 (1 bit)
access : read-write

PHYSLEEP : PHYSLEEP
bits : 6 - 6 (1 bit)
access : read-only

SUSP : SUSP
bits : 7 - 7 (1 bit)
access : read-only



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