\n
address_offset : 0x0 Bytes (0x0)
size : 0x88000 byte (0x0)
mem_usage : registers
protection :
The GOTGCTL register controls the behavior and reflects the status of the OTG function of the core.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRQSCS : SRQSCS
bits : 0 - 0 (1 bit)
access : read-only
SRQ : SRQ
bits : 1 - 1 (1 bit)
access : read-write
VBVALOEN : VBVALOEN
bits : 2 - 2 (1 bit)
access : read-write
VBVALOVAL : VBVALOVAL
bits : 3 - 3 (1 bit)
access : read-write
AVALOEN : AVALOEN
bits : 4 - 4 (1 bit)
access : read-write
AVALOVAL : AVALOVAL
bits : 5 - 5 (1 bit)
access : read-write
BVALOEN : BVALOEN
bits : 6 - 6 (1 bit)
access : read-write
BVALOVAL : BVALOVAL
bits : 7 - 7 (1 bit)
access : read-write
HNGSCS : HNGSCS
bits : 8 - 8 (1 bit)
access : read-only
HNPRQ : HNPRQ
bits : 9 - 9 (1 bit)
access : read-write
HSHNPEN : HSHNPEN
bits : 10 - 10 (1 bit)
access : read-write
DHNPEN : DHNPEN
bits : 11 - 11 (1 bit)
access : read-write
EHEN : EHEN
bits : 12 - 12 (1 bit)
access : read-write
CIDSTS : CIDSTS
bits : 16 - 16 (1 bit)
access : read-only
DBCT : DBCT
bits : 17 - 17 (1 bit)
access : read-only
ASVLD : ASVLD
bits : 18 - 18 (1 bit)
access : read-only
BSVLD : BSVLD
bits : 19 - 19 (1 bit)
access : read-only
OTGVER : OTGVER
bits : 20 - 20 (1 bit)
access : read-write
CURMOD : CURMOD
bits : 21 - 21 (1 bit)
access : read-only
The application uses this register to reset various hardware features inside the core.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSRST : CSRST
bits : 0 - 0 (1 bit)
access : read-only
PSRST : PSRST
bits : 1 - 1 (1 bit)
access : read-write
FSRST : FSRST
bits : 2 - 2 (1 bit)
access : read-write
RXFFLSH : RXFFLSH
bits : 4 - 4 (1 bit)
access : read-write
TXFFLSH : TXFFLSH
bits : 5 - 5 (1 bit)
access : read-write
TXFNUM : TXFNUM
bits : 6 - 10 (5 bit)
access : read-write
AHBIDL : AHBIDL
bits : 31 - 31 (1 bit)
access : read-only
OTG host periodic transmit FIFO size register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTXSA : PTXSA
bits : 0 - 15 (16 bit)
PTXFSIZ : PTXFSIZ
bits : 16 - 31 (16 bit)
OTG device IN endpoint transmit FIFO 1 size register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPTXSA : INEPTXSA
bits : 0 - 15 (16 bit)
INEPTXFD : INEPTXFD
bits : 16 - 31 (16 bit)
OTG device IN endpoint transmit FIFO 2 size register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPTXSA : INEPTXSA
bits : 0 - 15 (16 bit)
INEPTXFD : INEPTXFD
bits : 16 - 31 (16 bit)
OTG device IN endpoint transmit FIFO 3 size register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPTXSA : INEPTXSA
bits : 0 - 15 (16 bit)
INEPTXFD : INEPTXFD
bits : 16 - 31 (16 bit)
OTG device IN endpoint transmit FIFO 4 size register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPTXSA : INEPTXSA
bits : 0 - 15 (16 bit)
INEPTXFD : INEPTXFD
bits : 16 - 31 (16 bit)
OTG device IN endpoint transmit FIFO 5 size register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPTXSA : INEPTXSA
bits : 0 - 15 (16 bit)
INEPTXFD : INEPTXFD
bits : 16 - 31 (16 bit)
This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMOD : CMOD
bits : 0 - 0 (1 bit)
access : read-only
MMIS : MMIS
bits : 1 - 1 (1 bit)
access : read-write
OTGINT : OTGINT
bits : 2 - 2 (1 bit)
access : read-only
SOF : SOF
bits : 3 - 3 (1 bit)
access : read-write
RXFLVL : RXFLVL
bits : 4 - 4 (1 bit)
access : read-only
NPTXFE : NPTXFE
bits : 5 - 5 (1 bit)
access : read-only
GINAKEFF : GINAKEFF
bits : 6 - 6 (1 bit)
access : read-only
GONAKEFF : GONAKEFF
bits : 7 - 7 (1 bit)
access : read-only
ESUSP : ESUSP
bits : 10 - 10 (1 bit)
access : read-write
USBSUSP : USBSUSP
bits : 11 - 11 (1 bit)
access : read-write
USBRST : USBRST
bits : 12 - 12 (1 bit)
access : read-write
ENUMDNE : ENUMDNE
bits : 13 - 13 (1 bit)
access : read-write
ISOODRP : ISOODRP
bits : 14 - 14 (1 bit)
access : read-write
EOPF : EOPF
bits : 15 - 15 (1 bit)
access : read-write
IEPINT : IEPINT
bits : 18 - 18 (1 bit)
access : read-only
OEPINT : OEPINT
bits : 19 - 19 (1 bit)
access : read-only
IISOIXFR : IISOIXFR
bits : 20 - 20 (1 bit)
access : read-write
IPXFR : IPXFR
bits : 21 - 21 (1 bit)
access : read-write
RSTDET : RSTDET
bits : 23 - 23 (1 bit)
access : read-write
HPRTINT : HPRTINT
bits : 24 - 24 (1 bit)
access : read-only
HCINT : HCINT
bits : 25 - 25 (1 bit)
access : read-only
PTXFE : PTXFE
bits : 26 - 26 (1 bit)
access : read-only
LPMINT : LPMINT
bits : 27 - 27 (1 bit)
access : read-write
CIDSCHG : CIDSCHG
bits : 28 - 28 (1 bit)
access : read-write
DISCINT : DISCINT
bits : 29 - 29 (1 bit)
access : read-write
SRQINT : SRQINT
bits : 30 - 30 (1 bit)
access : read-write
WKUPINT : WKUPINT
bits : 31 - 31 (1 bit)
access : read-write
This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (GINTSTS) register bit corresponding to that interrupt is still set.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MMISM : MMISM
bits : 1 - 1 (1 bit)
access : read-write
OTGINT : OTGINT
bits : 2 - 2 (1 bit)
access : read-write
SOFM : SOFM
bits : 3 - 3 (1 bit)
access : read-write
RXFLVLM : RXFLVLM
bits : 4 - 4 (1 bit)
access : read-write
NPTXFEM : NPTXFEM
bits : 5 - 5 (1 bit)
access : read-write
GINAKEFFM : GINAKEFFM
bits : 6 - 6 (1 bit)
access : read-write
GONAKEFFM : GONAKEFFM
bits : 7 - 7 (1 bit)
access : read-write
ESUSPM : ESUSPM
bits : 10 - 10 (1 bit)
access : read-write
USBSUSPM : USBSUSPM
bits : 11 - 11 (1 bit)
access : read-write
USBRST : USBRST
bits : 12 - 12 (1 bit)
access : read-write
ENUMDNEM : ENUMDNEM
bits : 13 - 13 (1 bit)
access : read-write
ISOODRPM : ISOODRPM
bits : 14 - 14 (1 bit)
access : read-write
EOPFM : EOPFM
bits : 15 - 15 (1 bit)
access : read-write
IEPINT : IEPINT
bits : 18 - 18 (1 bit)
access : read-write
OEPINT : OEPINT
bits : 19 - 19 (1 bit)
access : read-write
IISOIXFRM : IISOIXFRM
bits : 20 - 20 (1 bit)
access : read-write
IPXFRM : IPXFRM
bits : 21 - 21 (1 bit)
access : read-write
RSTDETM : RSTDETM
bits : 23 - 23 (1 bit)
access : read-write
PRTIM : PRTIM
bits : 24 - 24 (1 bit)
access : read-write
HCIM : HCIM
bits : 25 - 25 (1 bit)
access : read-write
PTXFEM : PTXFEM
bits : 26 - 26 (1 bit)
access : read-write
LPMINTM : LPMINTM
bits : 27 - 27 (1 bit)
access : read-write
CIDSCHGM : CIDSCHGM
bits : 28 - 28 (1 bit)
access : read-write
DISCINT : DISCINT
bits : 29 - 29 (1 bit)
access : read-write
SRQIM : SRQIM
bits : 30 - 30 (1 bit)
access : read-write
WUIM : WUIM
bits : 31 - 31 (1 bit)
access : read-write
This description is for register GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and returns a value of 0x00000000.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPNUM : EPNUM
bits : 0 - 3 (4 bit)
BCNT : BCNT
bits : 4 - 14 (11 bit)
DPID : DPID
bits : 15 - 16 (2 bit)
PKTSTS : PKTSTS
bits : 17 - 20 (4 bit)
FRMNUM : FRMNUM
bits : 21 - 24 (4 bit)
STSPHST : STSPHST
bits : 27 - 27 (1 bit)
This description is for register GRXSTSR in Host mode
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : GRXSTSR_DEVICE
reset_Mask : 0x0
CHNUM : CHNUM
bits : 0 - 3 (4 bit)
BCNT : BCNT
bits : 4 - 14 (11 bit)
DPID : DPID
bits : 15 - 16 (2 bit)
PKTSTS : PKTSTS
bits : 17 - 20 (4 bit)
This description is for register GRXSTSP in Device mode. Similarly to GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO, a read to GRXSTSP (receive status read and pop register) additionally pops the top data entry out of the Rx FIFO. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the receive status FIFO when the receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in GINTSTS) is asserted.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPNUM : EPNUM
bits : 0 - 3 (4 bit)
BCNT : BCNT
bits : 4 - 14 (11 bit)
DPID : DPID
bits : 15 - 16 (2 bit)
PKTSTS : PKTSTS
bits : 17 - 20 (4 bit)
FRMNUM : FRMNUM
bits : 21 - 24 (4 bit)
STSPHST : STSPHST
bits : 27 - 27 (1 bit)
This description is for register GRXSTSP in HOST mode
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : GRXSTSP_DEVICE
reset_Mask : 0x0
CHNUM : CHNUM
bits : 0 - 3 (4 bit)
BCNT : BCNT
bits : 4 - 14 (11 bit)
DPID : DPID
bits : 15 - 16 (2 bit)
PKTSTS : PKTSTS
bits : 17 - 20 (4 bit)
The application can program the RAM size that must be allocated to the Rx FIFO.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXFD : RXFD
bits : 0 - 15 (16 bit)
Host mode
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NPTXFSA : NPTXFSA
bits : 0 - 15 (16 bit)
NPTXFD : NPTXFD
bits : 16 - 31 (16 bit)
In device mode, this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NPTXFSAV : NPTXFSAV
bits : 0 - 15 (16 bit)
NPTQXSAV : NPTQXSAV
bits : 16 - 23 (8 bit)
NPTXQTOP : NPTXQTOP
bits : 24 - 30 (7 bit)
OTG general core configuration register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCDET : DCDET
bits : 0 - 0 (1 bit)
access : read-only
PDET : PDET
bits : 1 - 1 (1 bit)
access : read-only
SDET : SDET
bits : 2 - 2 (1 bit)
access : read-only
PS2DET : PS2DET
bits : 3 - 3 (1 bit)
access : read-only
PWRDWN : PWRDWN
bits : 16 - 16 (1 bit)
access : read-write
BCDEN : BCDEN
bits : 17 - 17 (1 bit)
access : read-write
DCDEN : DCDEN
bits : 18 - 18 (1 bit)
access : read-write
PDEN : PDEN
bits : 19 - 19 (1 bit)
access : read-write
SDEN : SDEN
bits : 20 - 20 (1 bit)
access : read-write
VBDEN : VBDEN
bits : 21 - 21 (1 bit)
access : read-write
This is a register containing the Product ID as reset value.
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRODUCT_ID : PRODUCT_ID
bits : 0 - 31 (32 bit)
The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEDET : SEDET
bits : 2 - 2 (1 bit)
SRSSCHG : SRSSCHG
bits : 8 - 8 (1 bit)
HNSSCHG : HNSSCHG
bits : 9 - 9 (1 bit)
HNGDET : HNGDET
bits : 17 - 17 (1 bit)
ADTOCHG : ADTOCHG
bits : 18 - 18 (1 bit)
DBCDNE : DBCDNE
bits : 19 - 19 (1 bit)
This register configures the core after power-on. Do not make changes to this register after initializing the host.
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSLSPCS : FSLSPCS
bits : 0 - 1 (2 bit)
access : read-write
FSLSS : FSLSS
bits : 2 - 2 (1 bit)
access : read-only
This register stores the frame interval information for the current speed to which the OTG controller has enumerated.
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRIVL : FRIVL
bits : 0 - 15 (16 bit)
RLDCTRL : RLDCTRL
bits : 16 - 16 (1 bit)
This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame.
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRNUM : FRNUM
bits : 0 - 15 (16 bit)
FTREM : FTREM
bits : 16 - 31 (16 bit)
This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue.
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PTXFSAVL : PTXFSAVL
bits : 0 - 15 (16 bit)
PTXQSAV : PTXQSAV
bits : 16 - 23 (8 bit)
PTXQTOP : PTXQTOP
bits : 24 - 31 (8 bit)
When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in GINTSTS). This is shown in Figure724. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register.
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HAINT : HAINT
bits : 0 - 15 (16 bit)
The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits.
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HAINTM : HAINTM
bits : 0 - 15 (16 bit)
This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt.
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCSTS : PCSTS
bits : 0 - 0 (1 bit)
access : read-only
PCDET : PCDET
bits : 1 - 1 (1 bit)
access : read-write
PENA : PENA
bits : 2 - 2 (1 bit)
access : read-write
PENCHNG : PENCHNG
bits : 3 - 3 (1 bit)
access : read-write
POCA : POCA
bits : 4 - 4 (1 bit)
access : read-only
POCCHNG : POCCHNG
bits : 5 - 5 (1 bit)
access : read-write
PRES : PRES
bits : 6 - 6 (1 bit)
access : read-write
PSUSP : PSUSP
bits : 7 - 7 (1 bit)
access : read-write
PRST : PRST
bits : 8 - 8 (1 bit)
access : read-write
PLSTS : PLSTS
bits : 10 - 11 (2 bit)
access : read-only
PPWR : PPWR
bits : 12 - 12 (1 bit)
access : read-write
PTCTL : PTCTL
bits : 13 - 16 (4 bit)
access : read-write
PSPD : PSPD
bits : 17 - 18 (2 bit)
access : read-only
OTG host channel 0 characteristics register
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
EPNUM : EPNUM
bits : 11 - 14 (4 bit)
EPDIR : EPDIR
bits : 15 - 15 (1 bit)
LSDEV : LSDEV
bits : 17 - 17 (1 bit)
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
MCNT : MCNT
bits : 20 - 21 (2 bit)
DAD : DAD
bits : 22 - 28 (7 bit)
ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)
CHDIS : CHDIS
bits : 30 - 30 (1 bit)
CHENA : CHENA
bits : 31 - 31 (1 bit)
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
CHH : CHH
bits : 1 - 1 (1 bit)
STALL : STALL
bits : 3 - 3 (1 bit)
NAK : NAK
bits : 4 - 4 (1 bit)
ACK : ACK
bits : 5 - 5 (1 bit)
TXERR : TXERR
bits : 7 - 7 (1 bit)
BBERR : BBERR
bits : 8 - 8 (1 bit)
FRMOR : FRMOR
bits : 9 - 9 (1 bit)
DTERR : DTERR
bits : 10 - 10 (1 bit)
This register reflects the mask for each channel status described in the previous section.
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : XFRCM
bits : 0 - 0 (1 bit)
CHHM : CHHM
bits : 1 - 1 (1 bit)
STALLM : STALLM
bits : 3 - 3 (1 bit)
NAKM : NAKM
bits : 4 - 4 (1 bit)
ACKM : ACKM
bits : 5 - 5 (1 bit)
TXERRM : TXERRM
bits : 7 - 7 (1 bit)
BBERRM : BBERRM
bits : 8 - 8 (1 bit)
FRMORM : FRMORM
bits : 9 - 9 (1 bit)
DTERRM : DTERRM
bits : 10 - 10 (1 bit)
OTG host channel 0 transfer size register
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
DPID : DPID
bits : 29 - 30 (2 bit)
DOPNG : DOPNG
bits : 31 - 31 (1 bit)
OTG host channel 1 characteristics register
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
EPNUM : EPNUM
bits : 11 - 14 (4 bit)
EPDIR : EPDIR
bits : 15 - 15 (1 bit)
LSDEV : LSDEV
bits : 17 - 17 (1 bit)
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
MCNT : MCNT
bits : 20 - 21 (2 bit)
DAD : DAD
bits : 22 - 28 (7 bit)
ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)
CHDIS : CHDIS
bits : 30 - 30 (1 bit)
CHENA : CHENA
bits : 31 - 31 (1 bit)
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
CHH : CHH
bits : 1 - 1 (1 bit)
STALL : STALL
bits : 3 - 3 (1 bit)
NAK : NAK
bits : 4 - 4 (1 bit)
ACK : ACK
bits : 5 - 5 (1 bit)
TXERR : TXERR
bits : 7 - 7 (1 bit)
BBERR : BBERR
bits : 8 - 8 (1 bit)
FRMOR : FRMOR
bits : 9 - 9 (1 bit)
DTERR : DTERR
bits : 10 - 10 (1 bit)
This register reflects the mask for each channel status described in the previous section.
address_offset : 0x52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : XFRCM
bits : 0 - 0 (1 bit)
CHHM : CHHM
bits : 1 - 1 (1 bit)
STALLM : STALLM
bits : 3 - 3 (1 bit)
NAKM : NAKM
bits : 4 - 4 (1 bit)
ACKM : ACKM
bits : 5 - 5 (1 bit)
TXERRM : TXERRM
bits : 7 - 7 (1 bit)
BBERRM : BBERRM
bits : 8 - 8 (1 bit)
FRMORM : FRMORM
bits : 9 - 9 (1 bit)
DTERRM : DTERRM
bits : 10 - 10 (1 bit)
OTG host channel 1 transfer size register
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
DPID : DPID
bits : 29 - 30 (2 bit)
DOPNG : DOPNG
bits : 31 - 31 (1 bit)
OTG core LPM configuration register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPMEN : LPMEN
bits : 0 - 0 (1 bit)
access : read-write
LPMACK : LPMACK
bits : 1 - 1 (1 bit)
access : read-write
BESL : BESL
bits : 2 - 5 (4 bit)
access : read-write
REMWAKE : REMWAKE
bits : 6 - 6 (1 bit)
access : read-write
L1SSEN : L1SSEN
bits : 7 - 7 (1 bit)
access : read-write
BESLTHRS : BESLTHRS
bits : 8 - 11 (4 bit)
access : read-write
L1DSEN : L1DSEN
bits : 12 - 12 (1 bit)
access : read-write
LPMRSP : LPMRSP
bits : 13 - 14 (2 bit)
access : read-only
SLPSTS : SLPSTS
bits : 15 - 15 (1 bit)
access : read-only
L1RSMOK : L1RSMOK
bits : 16 - 16 (1 bit)
access : read-only
LPMCHIDX : LPMCHIDX
bits : 17 - 20 (4 bit)
access : read-write
LPMRCNT : LPMRCNT
bits : 21 - 23 (3 bit)
access : read-write
SNDLPM : SNDLPM
bits : 24 - 24 (1 bit)
access : read-write
LPMRCNTSTS : LPMRCNTSTS
bits : 25 - 27 (3 bit)
access : read-only
ENBESL : ENBESL
bits : 28 - 28 (1 bit)
access : read-write
OTG host channel 2 characteristics register
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
EPNUM : EPNUM
bits : 11 - 14 (4 bit)
EPDIR : EPDIR
bits : 15 - 15 (1 bit)
LSDEV : LSDEV
bits : 17 - 17 (1 bit)
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
MCNT : MCNT
bits : 20 - 21 (2 bit)
DAD : DAD
bits : 22 - 28 (7 bit)
ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)
CHDIS : CHDIS
bits : 30 - 30 (1 bit)
CHENA : CHENA
bits : 31 - 31 (1 bit)
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x548 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
CHH : CHH
bits : 1 - 1 (1 bit)
STALL : STALL
bits : 3 - 3 (1 bit)
NAK : NAK
bits : 4 - 4 (1 bit)
ACK : ACK
bits : 5 - 5 (1 bit)
TXERR : TXERR
bits : 7 - 7 (1 bit)
BBERR : BBERR
bits : 8 - 8 (1 bit)
FRMOR : FRMOR
bits : 9 - 9 (1 bit)
DTERR : DTERR
bits : 10 - 10 (1 bit)
This register reflects the mask for each channel status described in the previous section.
address_offset : 0x54C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : XFRCM
bits : 0 - 0 (1 bit)
CHHM : CHHM
bits : 1 - 1 (1 bit)
STALLM : STALLM
bits : 3 - 3 (1 bit)
NAKM : NAKM
bits : 4 - 4 (1 bit)
ACKM : ACKM
bits : 5 - 5 (1 bit)
TXERRM : TXERRM
bits : 7 - 7 (1 bit)
BBERRM : BBERRM
bits : 8 - 8 (1 bit)
FRMORM : FRMORM
bits : 9 - 9 (1 bit)
DTERRM : DTERRM
bits : 10 - 10 (1 bit)
OTG host channel 2 transfer size register
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
DPID : DPID
bits : 29 - 30 (2 bit)
DOPNG : DOPNG
bits : 31 - 31 (1 bit)
OTG host channel 3 characteristics register
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
EPNUM : EPNUM
bits : 11 - 14 (4 bit)
EPDIR : EPDIR
bits : 15 - 15 (1 bit)
LSDEV : LSDEV
bits : 17 - 17 (1 bit)
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
MCNT : MCNT
bits : 20 - 21 (2 bit)
DAD : DAD
bits : 22 - 28 (7 bit)
ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)
CHDIS : CHDIS
bits : 30 - 30 (1 bit)
CHENA : CHENA
bits : 31 - 31 (1 bit)
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
CHH : CHH
bits : 1 - 1 (1 bit)
STALL : STALL
bits : 3 - 3 (1 bit)
NAK : NAK
bits : 4 - 4 (1 bit)
ACK : ACK
bits : 5 - 5 (1 bit)
TXERR : TXERR
bits : 7 - 7 (1 bit)
BBERR : BBERR
bits : 8 - 8 (1 bit)
FRMOR : FRMOR
bits : 9 - 9 (1 bit)
DTERR : DTERR
bits : 10 - 10 (1 bit)
This register reflects the mask for each channel status described in the previous section.
address_offset : 0x56C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : XFRCM
bits : 0 - 0 (1 bit)
CHHM : CHHM
bits : 1 - 1 (1 bit)
STALLM : STALLM
bits : 3 - 3 (1 bit)
NAKM : NAKM
bits : 4 - 4 (1 bit)
ACKM : ACKM
bits : 5 - 5 (1 bit)
TXERRM : TXERRM
bits : 7 - 7 (1 bit)
BBERRM : BBERRM
bits : 8 - 8 (1 bit)
FRMORM : FRMORM
bits : 9 - 9 (1 bit)
DTERRM : DTERRM
bits : 10 - 10 (1 bit)
OTG host channel 3 transfer size register
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
DPID : DPID
bits : 29 - 30 (2 bit)
DOPNG : DOPNG
bits : 31 - 31 (1 bit)
OTG host channel 4 characteristics register
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
EPNUM : EPNUM
bits : 11 - 14 (4 bit)
EPDIR : EPDIR
bits : 15 - 15 (1 bit)
LSDEV : LSDEV
bits : 17 - 17 (1 bit)
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
MCNT : MCNT
bits : 20 - 21 (2 bit)
DAD : DAD
bits : 22 - 28 (7 bit)
ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)
CHDIS : CHDIS
bits : 30 - 30 (1 bit)
CHENA : CHENA
bits : 31 - 31 (1 bit)
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
CHH : CHH
bits : 1 - 1 (1 bit)
STALL : STALL
bits : 3 - 3 (1 bit)
NAK : NAK
bits : 4 - 4 (1 bit)
ACK : ACK
bits : 5 - 5 (1 bit)
TXERR : TXERR
bits : 7 - 7 (1 bit)
BBERR : BBERR
bits : 8 - 8 (1 bit)
FRMOR : FRMOR
bits : 9 - 9 (1 bit)
DTERR : DTERR
bits : 10 - 10 (1 bit)
This register reflects the mask for each channel status described in the previous section.
address_offset : 0x58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : XFRCM
bits : 0 - 0 (1 bit)
CHHM : CHHM
bits : 1 - 1 (1 bit)
STALLM : STALLM
bits : 3 - 3 (1 bit)
NAKM : NAKM
bits : 4 - 4 (1 bit)
ACKM : ACKM
bits : 5 - 5 (1 bit)
TXERRM : TXERRM
bits : 7 - 7 (1 bit)
BBERRM : BBERRM
bits : 8 - 8 (1 bit)
FRMORM : FRMORM
bits : 9 - 9 (1 bit)
DTERRM : DTERRM
bits : 10 - 10 (1 bit)
OTG host channel 4 transfer size register
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
DPID : DPID
bits : 29 - 30 (2 bit)
DOPNG : DOPNG
bits : 31 - 31 (1 bit)
OTG host channel 5 characteristics register
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
EPNUM : EPNUM
bits : 11 - 14 (4 bit)
EPDIR : EPDIR
bits : 15 - 15 (1 bit)
LSDEV : LSDEV
bits : 17 - 17 (1 bit)
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
MCNT : MCNT
bits : 20 - 21 (2 bit)
DAD : DAD
bits : 22 - 28 (7 bit)
ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)
CHDIS : CHDIS
bits : 30 - 30 (1 bit)
CHENA : CHENA
bits : 31 - 31 (1 bit)
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x5A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
CHH : CHH
bits : 1 - 1 (1 bit)
STALL : STALL
bits : 3 - 3 (1 bit)
NAK : NAK
bits : 4 - 4 (1 bit)
ACK : ACK
bits : 5 - 5 (1 bit)
TXERR : TXERR
bits : 7 - 7 (1 bit)
BBERR : BBERR
bits : 8 - 8 (1 bit)
FRMOR : FRMOR
bits : 9 - 9 (1 bit)
DTERR : DTERR
bits : 10 - 10 (1 bit)
This register reflects the mask for each channel status described in the previous section.
address_offset : 0x5AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : XFRCM
bits : 0 - 0 (1 bit)
CHHM : CHHM
bits : 1 - 1 (1 bit)
STALLM : STALLM
bits : 3 - 3 (1 bit)
NAKM : NAKM
bits : 4 - 4 (1 bit)
ACKM : ACKM
bits : 5 - 5 (1 bit)
TXERRM : TXERRM
bits : 7 - 7 (1 bit)
BBERRM : BBERRM
bits : 8 - 8 (1 bit)
FRMORM : FRMORM
bits : 9 - 9 (1 bit)
DTERRM : DTERRM
bits : 10 - 10 (1 bit)
OTG host channel 5 transfer size register
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
DPID : DPID
bits : 29 - 30 (2 bit)
DOPNG : DOPNG
bits : 31 - 31 (1 bit)
OTG host channel 6 characteristics register
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
EPNUM : EPNUM
bits : 11 - 14 (4 bit)
EPDIR : EPDIR
bits : 15 - 15 (1 bit)
LSDEV : LSDEV
bits : 17 - 17 (1 bit)
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
MCNT : MCNT
bits : 20 - 21 (2 bit)
DAD : DAD
bits : 22 - 28 (7 bit)
ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)
CHDIS : CHDIS
bits : 30 - 30 (1 bit)
CHENA : CHENA
bits : 31 - 31 (1 bit)
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x5C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
CHH : CHH
bits : 1 - 1 (1 bit)
STALL : STALL
bits : 3 - 3 (1 bit)
NAK : NAK
bits : 4 - 4 (1 bit)
ACK : ACK
bits : 5 - 5 (1 bit)
TXERR : TXERR
bits : 7 - 7 (1 bit)
BBERR : BBERR
bits : 8 - 8 (1 bit)
FRMOR : FRMOR
bits : 9 - 9 (1 bit)
DTERR : DTERR
bits : 10 - 10 (1 bit)
This register reflects the mask for each channel status described in the previous section.
address_offset : 0x5CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : XFRCM
bits : 0 - 0 (1 bit)
CHHM : CHHM
bits : 1 - 1 (1 bit)
STALLM : STALLM
bits : 3 - 3 (1 bit)
NAKM : NAKM
bits : 4 - 4 (1 bit)
ACKM : ACKM
bits : 5 - 5 (1 bit)
TXERRM : TXERRM
bits : 7 - 7 (1 bit)
BBERRM : BBERRM
bits : 8 - 8 (1 bit)
FRMORM : FRMORM
bits : 9 - 9 (1 bit)
DTERRM : DTERRM
bits : 10 - 10 (1 bit)
OTG host channel 6 transfer size register
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
DPID : DPID
bits : 29 - 30 (2 bit)
DOPNG : DOPNG
bits : 31 - 31 (1 bit)
OTG host channel 7 characteristics register
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
EPNUM : EPNUM
bits : 11 - 14 (4 bit)
EPDIR : EPDIR
bits : 15 - 15 (1 bit)
LSDEV : LSDEV
bits : 17 - 17 (1 bit)
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
MCNT : MCNT
bits : 20 - 21 (2 bit)
DAD : DAD
bits : 22 - 28 (7 bit)
ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)
CHDIS : CHDIS
bits : 30 - 30 (1 bit)
CHENA : CHENA
bits : 31 - 31 (1 bit)
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x5E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
CHH : CHH
bits : 1 - 1 (1 bit)
STALL : STALL
bits : 3 - 3 (1 bit)
NAK : NAK
bits : 4 - 4 (1 bit)
ACK : ACK
bits : 5 - 5 (1 bit)
TXERR : TXERR
bits : 7 - 7 (1 bit)
BBERR : BBERR
bits : 8 - 8 (1 bit)
FRMOR : FRMOR
bits : 9 - 9 (1 bit)
DTERR : DTERR
bits : 10 - 10 (1 bit)
This register reflects the mask for each channel status described in the previous section.
address_offset : 0x5EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : XFRCM
bits : 0 - 0 (1 bit)
CHHM : CHHM
bits : 1 - 1 (1 bit)
STALLM : STALLM
bits : 3 - 3 (1 bit)
NAKM : NAKM
bits : 4 - 4 (1 bit)
ACKM : ACKM
bits : 5 - 5 (1 bit)
TXERRM : TXERRM
bits : 7 - 7 (1 bit)
BBERRM : BBERRM
bits : 8 - 8 (1 bit)
FRMORM : FRMORM
bits : 9 - 9 (1 bit)
DTERRM : DTERRM
bits : 10 - 10 (1 bit)
OTG host channel 7 transfer size register
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
DPID : DPID
bits : 29 - 30 (2 bit)
DOPNG : DOPNG
bits : 31 - 31 (1 bit)
OTG host channel 8 characteristics register
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
EPNUM : EPNUM
bits : 11 - 14 (4 bit)
EPDIR : EPDIR
bits : 15 - 15 (1 bit)
LSDEV : LSDEV
bits : 17 - 17 (1 bit)
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
MCNT : MCNT
bits : 20 - 21 (2 bit)
DAD : DAD
bits : 22 - 28 (7 bit)
ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)
CHDIS : CHDIS
bits : 30 - 30 (1 bit)
CHENA : CHENA
bits : 31 - 31 (1 bit)
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
CHH : CHH
bits : 1 - 1 (1 bit)
STALL : STALL
bits : 3 - 3 (1 bit)
NAK : NAK
bits : 4 - 4 (1 bit)
ACK : ACK
bits : 5 - 5 (1 bit)
TXERR : TXERR
bits : 7 - 7 (1 bit)
BBERR : BBERR
bits : 8 - 8 (1 bit)
FRMOR : FRMOR
bits : 9 - 9 (1 bit)
DTERR : DTERR
bits : 10 - 10 (1 bit)
This register reflects the mask for each channel status described in the previous section.
address_offset : 0x60C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : XFRCM
bits : 0 - 0 (1 bit)
CHHM : CHHM
bits : 1 - 1 (1 bit)
STALLM : STALLM
bits : 3 - 3 (1 bit)
NAKM : NAKM
bits : 4 - 4 (1 bit)
ACKM : ACKM
bits : 5 - 5 (1 bit)
TXERRM : TXERRM
bits : 7 - 7 (1 bit)
BBERRM : BBERRM
bits : 8 - 8 (1 bit)
FRMORM : FRMORM
bits : 9 - 9 (1 bit)
DTERRM : DTERRM
bits : 10 - 10 (1 bit)
OTG host channel 8 transfer size register
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
DPID : DPID
bits : 29 - 30 (2 bit)
DOPNG : DOPNG
bits : 31 - 31 (1 bit)
OTG host channel 9 characteristics register
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
EPNUM : EPNUM
bits : 11 - 14 (4 bit)
EPDIR : EPDIR
bits : 15 - 15 (1 bit)
LSDEV : LSDEV
bits : 17 - 17 (1 bit)
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
MCNT : MCNT
bits : 20 - 21 (2 bit)
DAD : DAD
bits : 22 - 28 (7 bit)
ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)
CHDIS : CHDIS
bits : 30 - 30 (1 bit)
CHENA : CHENA
bits : 31 - 31 (1 bit)
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
CHH : CHH
bits : 1 - 1 (1 bit)
STALL : STALL
bits : 3 - 3 (1 bit)
NAK : NAK
bits : 4 - 4 (1 bit)
ACK : ACK
bits : 5 - 5 (1 bit)
TXERR : TXERR
bits : 7 - 7 (1 bit)
BBERR : BBERR
bits : 8 - 8 (1 bit)
FRMOR : FRMOR
bits : 9 - 9 (1 bit)
DTERR : DTERR
bits : 10 - 10 (1 bit)
This register reflects the mask for each channel status described in the previous section.
address_offset : 0x62C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : XFRCM
bits : 0 - 0 (1 bit)
CHHM : CHHM
bits : 1 - 1 (1 bit)
STALLM : STALLM
bits : 3 - 3 (1 bit)
NAKM : NAKM
bits : 4 - 4 (1 bit)
ACKM : ACKM
bits : 5 - 5 (1 bit)
TXERRM : TXERRM
bits : 7 - 7 (1 bit)
BBERRM : BBERRM
bits : 8 - 8 (1 bit)
FRMORM : FRMORM
bits : 9 - 9 (1 bit)
DTERRM : DTERRM
bits : 10 - 10 (1 bit)
OTG host channel 9 transfer size register
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
DPID : DPID
bits : 29 - 30 (2 bit)
DOPNG : DOPNG
bits : 31 - 31 (1 bit)
OTG host channel 10 characteristics register
address_offset : 0x640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
EPNUM : EPNUM
bits : 11 - 14 (4 bit)
EPDIR : EPDIR
bits : 15 - 15 (1 bit)
LSDEV : LSDEV
bits : 17 - 17 (1 bit)
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
MCNT : MCNT
bits : 20 - 21 (2 bit)
DAD : DAD
bits : 22 - 28 (7 bit)
ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)
CHDIS : CHDIS
bits : 30 - 30 (1 bit)
CHENA : CHENA
bits : 31 - 31 (1 bit)
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x648 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
CHH : CHH
bits : 1 - 1 (1 bit)
STALL : STALL
bits : 3 - 3 (1 bit)
NAK : NAK
bits : 4 - 4 (1 bit)
ACK : ACK
bits : 5 - 5 (1 bit)
TXERR : TXERR
bits : 7 - 7 (1 bit)
BBERR : BBERR
bits : 8 - 8 (1 bit)
FRMOR : FRMOR
bits : 9 - 9 (1 bit)
DTERR : DTERR
bits : 10 - 10 (1 bit)
This register reflects the mask for each channel status described in the previous section.
address_offset : 0x64C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : XFRCM
bits : 0 - 0 (1 bit)
CHHM : CHHM
bits : 1 - 1 (1 bit)
STALLM : STALLM
bits : 3 - 3 (1 bit)
NAKM : NAKM
bits : 4 - 4 (1 bit)
ACKM : ACKM
bits : 5 - 5 (1 bit)
TXERRM : TXERRM
bits : 7 - 7 (1 bit)
BBERRM : BBERRM
bits : 8 - 8 (1 bit)
FRMORM : FRMORM
bits : 9 - 9 (1 bit)
DTERRM : DTERRM
bits : 10 - 10 (1 bit)
OTG host channel 10 transfer size register
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
DPID : DPID
bits : 29 - 30 (2 bit)
DOPNG : DOPNG
bits : 31 - 31 (1 bit)
OTG host channel 11 characteristics register
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
EPNUM : EPNUM
bits : 11 - 14 (4 bit)
EPDIR : EPDIR
bits : 15 - 15 (1 bit)
LSDEV : LSDEV
bits : 17 - 17 (1 bit)
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
MCNT : MCNT
bits : 20 - 21 (2 bit)
DAD : DAD
bits : 22 - 28 (7 bit)
ODDFRM : ODDFRM
bits : 29 - 29 (1 bit)
CHDIS : CHDIS
bits : 30 - 30 (1 bit)
CHENA : CHENA
bits : 31 - 31 (1 bit)
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
address_offset : 0x668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
CHH : CHH
bits : 1 - 1 (1 bit)
STALL : STALL
bits : 3 - 3 (1 bit)
NAK : NAK
bits : 4 - 4 (1 bit)
ACK : ACK
bits : 5 - 5 (1 bit)
TXERR : TXERR
bits : 7 - 7 (1 bit)
BBERR : BBERR
bits : 8 - 8 (1 bit)
FRMOR : FRMOR
bits : 9 - 9 (1 bit)
DTERR : DTERR
bits : 10 - 10 (1 bit)
This register reflects the mask for each channel status described in the previous section.
address_offset : 0x66C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : XFRCM
bits : 0 - 0 (1 bit)
CHHM : CHHM
bits : 1 - 1 (1 bit)
STALLM : STALLM
bits : 3 - 3 (1 bit)
NAKM : NAKM
bits : 4 - 4 (1 bit)
ACKM : ACKM
bits : 5 - 5 (1 bit)
TXERRM : TXERRM
bits : 7 - 7 (1 bit)
BBERRM : BBERRM
bits : 8 - 8 (1 bit)
FRMORM : FRMORM
bits : 9 - 9 (1 bit)
DTERRM : DTERRM
bits : 10 - 10 (1 bit)
OTG host channel 11 transfer size register
address_offset : 0x670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
DPID : DPID
bits : 29 - 30 (2 bit)
DOPNG : DOPNG
bits : 31 - 31 (1 bit)
This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GINTMSK : GINTMSK
bits : 0 - 0 (1 bit)
TXFELVL : TXFELVL
bits : 7 - 7 (1 bit)
PTXFELVL : PTXFELVL
bits : 8 - 8 (1 bit)
This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSPD : DSPD
bits : 0 - 1 (2 bit)
NZLSOHSK : NZLSOHSK
bits : 2 - 2 (1 bit)
DAD : DAD
bits : 4 - 10 (7 bit)
PFIVL : PFIVL
bits : 11 - 12 (2 bit)
ERRATIM : ERRATIM
bits : 15 - 15 (1 bit)
OTG device control register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RWUSIG : RWUSIG
bits : 0 - 0 (1 bit)
access : read-write
SDIS : SDIS
bits : 1 - 1 (1 bit)
access : read-write
GINSTS : GINSTS
bits : 2 - 2 (1 bit)
access : read-only
GONSTS : GONSTS
bits : 3 - 3 (1 bit)
access : read-only
TCTL : TCTL
bits : 4 - 6 (3 bit)
access : read-write
SGINAK : SGINAK
bits : 7 - 7 (1 bit)
access : write-only
CGINAK : CGINAK
bits : 8 - 8 (1 bit)
access : write-only
SGONAK : SGONAK
bits : 9 - 9 (1 bit)
access : write-only
CGONAK : CGONAK
bits : 10 - 10 (1 bit)
access : write-only
POPRGDNE : POPRGDNE
bits : 11 - 11 (1 bit)
access : read-write
DSBESLRJCT : DSBESLRJCT
bits : 18 - 18 (1 bit)
access : read-write
This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (DAINT) register.
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUSPSTS : SUSPSTS
bits : 0 - 0 (1 bit)
ENUMSPD : ENUMSPD
bits : 1 - 2 (2 bit)
EERR : EERR
bits : 3 - 3 (1 bit)
FNSOF : FNSOF
bits : 8 - 21 (14 bit)
DEVLNSTS : DEVLNSTS
bits : 22 - 23 (2 bit)
This register works with each of the DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : XFRCM
bits : 0 - 0 (1 bit)
EPDM : EPDM
bits : 1 - 1 (1 bit)
TOM : TOM
bits : 3 - 3 (1 bit)
ITTXFEMSK : ITTXFEMSK
bits : 4 - 4 (1 bit)
INEPNMM : INEPNMM
bits : 5 - 5 (1 bit)
INEPNEM : INEPNEM
bits : 6 - 6 (1 bit)
NAKM : NAKM
bits : 13 - 13 (1 bit)
This register works with each of the DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : XFRCM
bits : 0 - 0 (1 bit)
EPDM : EPDM
bits : 1 - 1 (1 bit)
STUPM : STUPM
bits : 3 - 3 (1 bit)
OTEPDM : OTEPDM
bits : 4 - 4 (1 bit)
STSPHSRXM : STSPHSRXM
bits : 5 - 5 (1 bit)
OUTPKTERRM : OUTPKTERRM
bits : 8 - 8 (1 bit)
BERRM : BERRM
bits : 12 - 12 (1 bit)
NAKMSK : NAKMSK
bits : 13 - 13 (1 bit)
When a significant event occurs on an endpoint, a DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the GINTSTS register (OEPINT or IEPINT in GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding device endpoint-x interrupt register (DIEPINTx/DOEPINTx).
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IEPINT : IEPINT
bits : 0 - 15 (16 bit)
OEPINT : OEPINT
bits : 16 - 31 (16 bit)
The DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the DAINT register bit corresponding to that interrupt is still set.
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IEPM : IEPM
bits : 0 - 15 (16 bit)
OEPM : OEPM
bits : 16 - 31 (16 bit)
This register specifies the VBUS discharge time after VBUS pulsing during SRP.
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBUSDT : VBUSDT
bits : 0 - 15 (16 bit)
This register specifies the VBUS pulsing time during SRP.
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DVBUSP : DVBUSP
bits : 0 - 15 (16 bit)
This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx).
address_offset : 0x834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPTXFEM : INEPTXFEM
bits : 0 - 15 (16 bit)
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 1 (2 bit)
access : read-write
USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-only
NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write
STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write
TXFNUM : TXFNUM
bits : 22 - 25 (4 bit)
access : read-write
CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only
EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write
EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0x908 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
access : read-write
EPDISD : EPDISD
bits : 1 - 1 (1 bit)
access : read-write
TOC : TOC
bits : 3 - 3 (1 bit)
access : read-write
ITTXFE : ITTXFE
bits : 4 - 4 (1 bit)
access : read-write
INEPNM : INEPNM
bits : 5 - 5 (1 bit)
access : read-write
INEPNE : INEPNE
bits : 6 - 6 (1 bit)
access : read-only
TXFE : TXFE
bits : 7 - 7 (1 bit)
access : read-only
PKTDRPSTS : PKTDRPSTS
bits : 11 - 11 (1 bit)
access : read-write
NAK : NAK
bits : 13 - 13 (1 bit)
access : read-write
The application must modify this register before enabling endpoint 0.
address_offset : 0x910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 6 (7 bit)
PKTCNT : PKTCNT
bits : 19 - 20 (2 bit)
This read-only register contains the free space information for the device IN endpoint Tx FIFO.
address_offset : 0x918 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INEPTFSAV : INEPTFSAV
bits : 0 - 15 (16 bit)
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0x920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write
USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write
EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write
STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write
TXFNUM : TXFNUM
bits : 22 - 25 (4 bit)
access : read-write
CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only
SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only
SODDFRM : SODDFRM
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write
EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
access : read-write
EPDISD : EPDISD
bits : 1 - 1 (1 bit)
access : read-write
TOC : TOC
bits : 3 - 3 (1 bit)
access : read-write
ITTXFE : ITTXFE
bits : 4 - 4 (1 bit)
access : read-write
INEPNM : INEPNM
bits : 5 - 5 (1 bit)
access : read-write
INEPNE : INEPNE
bits : 6 - 6 (1 bit)
access : read-only
TXFE : TXFE
bits : 7 - 7 (1 bit)
access : read-only
PKTDRPSTS : PKTDRPSTS
bits : 11 - 11 (1 bit)
access : read-write
NAK : NAK
bits : 13 - 13 (1 bit)
access : read-write
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0x930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
MCNT : MCNT
bits : 29 - 30 (2 bit)
OTG device IN endpoint 1 DMA address register
address_offset : 0x934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)
This read-only register contains the free space information for the device IN endpoint Tx FIFO.
address_offset : 0x938 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INEPTFSAV : INEPTFSAV
bits : 0 - 15 (16 bit)
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0x940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write
USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write
EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write
STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write
TXFNUM : TXFNUM
bits : 22 - 25 (4 bit)
access : read-write
CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only
SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only
SODDFRM : SODDFRM
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write
EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0x948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
access : read-write
EPDISD : EPDISD
bits : 1 - 1 (1 bit)
access : read-write
TOC : TOC
bits : 3 - 3 (1 bit)
access : read-write
ITTXFE : ITTXFE
bits : 4 - 4 (1 bit)
access : read-write
INEPNM : INEPNM
bits : 5 - 5 (1 bit)
access : read-write
INEPNE : INEPNE
bits : 6 - 6 (1 bit)
access : read-only
TXFE : TXFE
bits : 7 - 7 (1 bit)
access : read-only
PKTDRPSTS : PKTDRPSTS
bits : 11 - 11 (1 bit)
access : read-write
NAK : NAK
bits : 13 - 13 (1 bit)
access : read-write
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0x950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
MCNT : MCNT
bits : 29 - 30 (2 bit)
OTG device IN endpoint 2 DMA address register
address_offset : 0x954 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)
This read-only register contains the free space information for the device IN endpoint Tx FIFO.
address_offset : 0x958 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INEPTFSAV : INEPTFSAV
bits : 0 - 15 (16 bit)
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0x960 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write
USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write
EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write
STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write
TXFNUM : TXFNUM
bits : 22 - 25 (4 bit)
access : read-write
CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only
SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only
SODDFRM : SODDFRM
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write
EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0x968 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
access : read-write
EPDISD : EPDISD
bits : 1 - 1 (1 bit)
access : read-write
TOC : TOC
bits : 3 - 3 (1 bit)
access : read-write
ITTXFE : ITTXFE
bits : 4 - 4 (1 bit)
access : read-write
INEPNM : INEPNM
bits : 5 - 5 (1 bit)
access : read-write
INEPNE : INEPNE
bits : 6 - 6 (1 bit)
access : read-only
TXFE : TXFE
bits : 7 - 7 (1 bit)
access : read-only
PKTDRPSTS : PKTDRPSTS
bits : 11 - 11 (1 bit)
access : read-write
NAK : NAK
bits : 13 - 13 (1 bit)
access : read-write
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0x970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
MCNT : MCNT
bits : 29 - 30 (2 bit)
OTG device IN endpoint 3 DMA address register
address_offset : 0x974 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)
This read-only register contains the free space information for the device IN endpoint Tx FIFO.
address_offset : 0x978 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INEPTFSAV : INEPTFSAV
bits : 0 - 15 (16 bit)
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0x980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write
USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write
EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write
STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write
TXFNUM : TXFNUM
bits : 22 - 25 (4 bit)
access : read-write
CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only
SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only
SODDFRM : SODDFRM
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write
EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0x988 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
access : read-write
EPDISD : EPDISD
bits : 1 - 1 (1 bit)
access : read-write
TOC : TOC
bits : 3 - 3 (1 bit)
access : read-write
ITTXFE : ITTXFE
bits : 4 - 4 (1 bit)
access : read-write
INEPNM : INEPNM
bits : 5 - 5 (1 bit)
access : read-write
INEPNE : INEPNE
bits : 6 - 6 (1 bit)
access : read-only
TXFE : TXFE
bits : 7 - 7 (1 bit)
access : read-only
PKTDRPSTS : PKTDRPSTS
bits : 11 - 11 (1 bit)
access : read-write
NAK : NAK
bits : 13 - 13 (1 bit)
access : read-write
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0x990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
MCNT : MCNT
bits : 29 - 30 (2 bit)
OTG device IN endpoint 4 DMA address register
address_offset : 0x994 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)
This read-only register contains the free space information for the device IN endpoint Tx FIFO.
address_offset : 0x998 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INEPTFSAV : INEPTFSAV
bits : 0 - 15 (16 bit)
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0x9A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write
USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write
EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write
STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write
TXFNUM : TXFNUM
bits : 22 - 25 (4 bit)
access : read-write
CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only
SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only
SODDFRM : SODDFRM
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write
EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0x9A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
access : read-write
EPDISD : EPDISD
bits : 1 - 1 (1 bit)
access : read-write
TOC : TOC
bits : 3 - 3 (1 bit)
access : read-write
ITTXFE : ITTXFE
bits : 4 - 4 (1 bit)
access : read-write
INEPNM : INEPNM
bits : 5 - 5 (1 bit)
access : read-write
INEPNE : INEPNE
bits : 6 - 6 (1 bit)
access : read-only
TXFE : TXFE
bits : 7 - 7 (1 bit)
access : read-only
PKTDRPSTS : PKTDRPSTS
bits : 11 - 11 (1 bit)
access : read-write
NAK : NAK
bits : 13 - 13 (1 bit)
access : read-write
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0x9B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
MCNT : MCNT
bits : 29 - 30 (2 bit)
OTG device IN endpoint 5 DMA address register
address_offset : 0x9B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)
This read-only register contains the free space information for the device IN endpoint Tx FIFO.
address_offset : 0x9B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INEPTFSAV : INEPTFSAV
bits : 0 - 15 (16 bit)
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0x9C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
access : read-write
EPDISD : EPDISD
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHBERR
bits : 2 - 2 (1 bit)
access : read-write
TOC : TOC
bits : 3 - 3 (1 bit)
access : read-write
ITTXFE : ITTXFE
bits : 4 - 4 (1 bit)
access : read-write
INEPNM : INEPNM
bits : 5 - 5 (1 bit)
access : read-write
INEPNE : INEPNE
bits : 6 - 6 (1 bit)
access : read-only
TXFE : TXFE
bits : 7 - 7 (1 bit)
access : read-only
TXFIFOUDRN : TXFIFOUDRN
bits : 8 - 8 (1 bit)
access : read-write
BNA : BNA
bits : 9 - 9 (1 bit)
access : read-write
PKTDRPSTS : PKTDRPSTS
bits : 11 - 11 (1 bit)
access : read-write
NAK : NAK
bits : 13 - 13 (1 bit)
access : read-write
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0x9D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
MCNT : MCNT
bits : 29 - 30 (2 bit)
OTG device IN endpoint 6 DMA address register
address_offset : 0x9D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0x9E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
access : read-write
EPDISD : EPDISD
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHBERR
bits : 2 - 2 (1 bit)
access : read-write
TOC : TOC
bits : 3 - 3 (1 bit)
access : read-write
ITTXFE : ITTXFE
bits : 4 - 4 (1 bit)
access : read-write
INEPNM : INEPNM
bits : 5 - 5 (1 bit)
access : read-write
INEPNE : INEPNE
bits : 6 - 6 (1 bit)
access : read-only
TXFE : TXFE
bits : 7 - 7 (1 bit)
access : read-only
TXFIFOUDRN : TXFIFOUDRN
bits : 8 - 8 (1 bit)
access : read-write
BNA : BNA
bits : 9 - 9 (1 bit)
access : read-write
PKTDRPSTS : PKTDRPSTS
bits : 11 - 11 (1 bit)
access : read-write
NAK : NAK
bits : 13 - 13 (1 bit)
access : read-write
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0x9F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
MCNT : MCNT
bits : 29 - 30 (2 bit)
OTG device IN endpoint 7 DMA address register
address_offset : 0x9F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0xA08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
access : read-write
EPDISD : EPDISD
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHBERR
bits : 2 - 2 (1 bit)
access : read-write
TOC : TOC
bits : 3 - 3 (1 bit)
access : read-write
ITTXFE : ITTXFE
bits : 4 - 4 (1 bit)
access : read-write
INEPNM : INEPNM
bits : 5 - 5 (1 bit)
access : read-write
INEPNE : INEPNE
bits : 6 - 6 (1 bit)
access : read-only
TXFE : TXFE
bits : 7 - 7 (1 bit)
access : read-only
TXFIFOUDRN : TXFIFOUDRN
bits : 8 - 8 (1 bit)
access : read-write
BNA : BNA
bits : 9 - 9 (1 bit)
access : read-write
PKTDRPSTS : PKTDRPSTS
bits : 11 - 11 (1 bit)
access : read-write
NAK : NAK
bits : 13 - 13 (1 bit)
access : read-write
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0xA10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
MCNT : MCNT
bits : 29 - 30 (2 bit)
OTG device IN endpoint 8 DMA address register
address_offset : 0xA14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)
This section describes the DOEPCTL0 register.
address_offset : 0xB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 1 (2 bit)
access : read-only
USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-only
NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-only
SNPM : SNPM
bits : 20 - 20 (1 bit)
access : read-write
STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write
CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only
EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-only
EPENA : EPENA
bits : 31 - 31 (1 bit)
access : write-only
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0xB08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
EPDISD : EPDISD
bits : 1 - 1 (1 bit)
AHBERR : AHBERR
bits : 2 - 2 (1 bit)
STUP : STUP
bits : 3 - 3 (1 bit)
OTEPDIS : OTEPDIS
bits : 4 - 4 (1 bit)
STSPHSRX : STSPHSRX
bits : 5 - 5 (1 bit)
B2BSTUP : B2BSTUP
bits : 6 - 6 (1 bit)
OUTPKTERR : OUTPKTERR
bits : 8 - 8 (1 bit)
BNA : BNA
bits : 9 - 9 (1 bit)
BERR : BERR
bits : 12 - 12 (1 bit)
NAK : NAK
bits : 13 - 13 (1 bit)
NYET : NYET
bits : 14 - 14 (1 bit)
STPKTRX : STPKTRX
bits : 15 - 15 (1 bit)
The application must modify this register before enabling endpoint 0.
address_offset : 0xB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 6 (7 bit)
PKTCNT : PKTCNT
bits : 19 - 19 (1 bit)
STUPCNT : STUPCNT
bits : 29 - 30 (2 bit)
OTG device OUT endpoint 0 DMA address register
address_offset : 0xB14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write
USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write
EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write
SNPM : SNPM
bits : 20 - 20 (1 bit)
access : read-write
STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write
CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only
SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only
SD1PID_SODDFRM : SD1PID_SODDFRM
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write
EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0xB28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
EPDISD : EPDISD
bits : 1 - 1 (1 bit)
AHBERR : AHBERR
bits : 2 - 2 (1 bit)
STUP : STUP
bits : 3 - 3 (1 bit)
OTEPDIS : OTEPDIS
bits : 4 - 4 (1 bit)
STSPHSRX : STSPHSRX
bits : 5 - 5 (1 bit)
B2BSTUP : B2BSTUP
bits : 6 - 6 (1 bit)
OUTPKTERR : OUTPKTERR
bits : 8 - 8 (1 bit)
BNA : BNA
bits : 9 - 9 (1 bit)
BERR : BERR
bits : 12 - 12 (1 bit)
NAK : NAK
bits : 13 - 13 (1 bit)
NYET : NYET
bits : 14 - 14 (1 bit)
STPKTRX : STPKTRX
bits : 15 - 15 (1 bit)
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0xB30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
RXDPID_STUPCNT : RXDPID_STUPCNT
bits : 29 - 30 (2 bit)
OTG device OUT endpoint 1 DMA address register
address_offset : 0xB34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0xB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write
USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write
EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write
SNPM : SNPM
bits : 20 - 20 (1 bit)
access : read-write
STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write
CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only
SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only
SD1PID_SODDFRM : SD1PID_SODDFRM
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write
EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0xB48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
EPDISD : EPDISD
bits : 1 - 1 (1 bit)
AHBERR : AHBERR
bits : 2 - 2 (1 bit)
STUP : STUP
bits : 3 - 3 (1 bit)
OTEPDIS : OTEPDIS
bits : 4 - 4 (1 bit)
STSPHSRX : STSPHSRX
bits : 5 - 5 (1 bit)
B2BSTUP : B2BSTUP
bits : 6 - 6 (1 bit)
OUTPKTERR : OUTPKTERR
bits : 8 - 8 (1 bit)
BNA : BNA
bits : 9 - 9 (1 bit)
BERR : BERR
bits : 12 - 12 (1 bit)
NAK : NAK
bits : 13 - 13 (1 bit)
NYET : NYET
bits : 14 - 14 (1 bit)
STPKTRX : STPKTRX
bits : 15 - 15 (1 bit)
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0xB50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
RXDPID_STUPCNT : RXDPID_STUPCNT
bits : 29 - 30 (2 bit)
OTG device OUT endpoint 2 DMA address register
address_offset : 0xB54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0xB60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write
USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write
EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write
SNPM : SNPM
bits : 20 - 20 (1 bit)
access : read-write
STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write
CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only
SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only
SD1PID_SODDFRM : SD1PID_SODDFRM
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write
EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0xB68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
EPDISD : EPDISD
bits : 1 - 1 (1 bit)
AHBERR : AHBERR
bits : 2 - 2 (1 bit)
STUP : STUP
bits : 3 - 3 (1 bit)
OTEPDIS : OTEPDIS
bits : 4 - 4 (1 bit)
STSPHSRX : STSPHSRX
bits : 5 - 5 (1 bit)
B2BSTUP : B2BSTUP
bits : 6 - 6 (1 bit)
OUTPKTERR : OUTPKTERR
bits : 8 - 8 (1 bit)
BNA : BNA
bits : 9 - 9 (1 bit)
BERR : BERR
bits : 12 - 12 (1 bit)
NAK : NAK
bits : 13 - 13 (1 bit)
NYET : NYET
bits : 14 - 14 (1 bit)
STPKTRX : STPKTRX
bits : 15 - 15 (1 bit)
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0xB70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
RXDPID_STUPCNT : RXDPID_STUPCNT
bits : 29 - 30 (2 bit)
OTG device OUT endpoint 3 DMA address register
address_offset : 0xB74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0xB80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write
USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write
EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write
SNPM : SNPM
bits : 20 - 20 (1 bit)
access : read-write
STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write
CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only
SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only
SD1PID_SODDFRM : SD1PID_SODDFRM
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write
EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0xB88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
EPDISD : EPDISD
bits : 1 - 1 (1 bit)
AHBERR : AHBERR
bits : 2 - 2 (1 bit)
STUP : STUP
bits : 3 - 3 (1 bit)
OTEPDIS : OTEPDIS
bits : 4 - 4 (1 bit)
STSPHSRX : STSPHSRX
bits : 5 - 5 (1 bit)
B2BSTUP : B2BSTUP
bits : 6 - 6 (1 bit)
OUTPKTERR : OUTPKTERR
bits : 8 - 8 (1 bit)
BNA : BNA
bits : 9 - 9 (1 bit)
BERR : BERR
bits : 12 - 12 (1 bit)
NAK : NAK
bits : 13 - 13 (1 bit)
NYET : NYET
bits : 14 - 14 (1 bit)
STPKTRX : STPKTRX
bits : 15 - 15 (1 bit)
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0xB90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
RXDPID_STUPCNT : RXDPID_STUPCNT
bits : 29 - 30 (2 bit)
OTG device OUT endpoint 4 DMA address register
address_offset : 0xB94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0xBA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write
USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write
EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write
SNPM : SNPM
bits : 20 - 20 (1 bit)
access : read-write
STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write
CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only
SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only
SD1PID_SODDFRM : SD1PID_SODDFRM
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write
EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0xBA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
EPDISD : EPDISD
bits : 1 - 1 (1 bit)
AHBERR : AHBERR
bits : 2 - 2 (1 bit)
STUP : STUP
bits : 3 - 3 (1 bit)
OTEPDIS : OTEPDIS
bits : 4 - 4 (1 bit)
STSPHSRX : STSPHSRX
bits : 5 - 5 (1 bit)
B2BSTUP : B2BSTUP
bits : 6 - 6 (1 bit)
OUTPKTERR : OUTPKTERR
bits : 8 - 8 (1 bit)
BNA : BNA
bits : 9 - 9 (1 bit)
BERR : BERR
bits : 12 - 12 (1 bit)
NAK : NAK
bits : 13 - 13 (1 bit)
NYET : NYET
bits : 14 - 14 (1 bit)
STPKTRX : STPKTRX
bits : 15 - 15 (1 bit)
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0xBB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
RXDPID_STUPCNT : RXDPID_STUPCNT
bits : 29 - 30 (2 bit)
OTG device OUT endpoint 5 DMA address register
address_offset : 0xBB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0xBC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write
USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write
EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write
SNPM : SNPM
bits : 20 - 20 (1 bit)
access : read-write
STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write
CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only
SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only
SD1PID_SODDFRM : SD1PID_SODDFRM
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write
EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0xBC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
EPDISD : EPDISD
bits : 1 - 1 (1 bit)
AHBERR : AHBERR
bits : 2 - 2 (1 bit)
STUP : STUP
bits : 3 - 3 (1 bit)
OTEPDIS : OTEPDIS
bits : 4 - 4 (1 bit)
STSPHSRX : STSPHSRX
bits : 5 - 5 (1 bit)
B2BSTUP : B2BSTUP
bits : 6 - 6 (1 bit)
OUTPKTERR : OUTPKTERR
bits : 8 - 8 (1 bit)
BNA : BNA
bits : 9 - 9 (1 bit)
BERR : BERR
bits : 12 - 12 (1 bit)
NAK : NAK
bits : 13 - 13 (1 bit)
NYET : NYET
bits : 14 - 14 (1 bit)
STPKTRX : STPKTRX
bits : 15 - 15 (1 bit)
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0xBD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
RXDPID_STUPCNT : RXDPID_STUPCNT
bits : 29 - 30 (2 bit)
OTG device OUT endpoint 6 DMA address register
address_offset : 0xBD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0xBE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write
USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write
EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write
SNPM : SNPM
bits : 20 - 20 (1 bit)
access : read-write
STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write
CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only
SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only
SD1PID_SODDFRM : SD1PID_SODDFRM
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write
EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0xBE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
EPDISD : EPDISD
bits : 1 - 1 (1 bit)
AHBERR : AHBERR
bits : 2 - 2 (1 bit)
STUP : STUP
bits : 3 - 3 (1 bit)
OTEPDIS : OTEPDIS
bits : 4 - 4 (1 bit)
STSPHSRX : STSPHSRX
bits : 5 - 5 (1 bit)
B2BSTUP : B2BSTUP
bits : 6 - 6 (1 bit)
OUTPKTERR : OUTPKTERR
bits : 8 - 8 (1 bit)
BNA : BNA
bits : 9 - 9 (1 bit)
BERR : BERR
bits : 12 - 12 (1 bit)
NAK : NAK
bits : 13 - 13 (1 bit)
NYET : NYET
bits : 14 - 14 (1 bit)
STPKTRX : STPKTRX
bits : 15 - 15 (1 bit)
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0xBF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
RXDPID_STUPCNT : RXDPID_STUPCNT
bits : 29 - 30 (2 bit)
OTG device OUT endpoint 7 DMA address register
address_offset : 0xBF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)
This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOCAL : TOCAL
bits : 0 - 2 (3 bit)
access : read-write
PHYSEL : PHYSEL
bits : 6 - 6 (1 bit)
access : read-only
SRPCAP : SRPCAP
bits : 8 - 8 (1 bit)
access : read-write
HNPCAP : HNPCAP
bits : 9 - 9 (1 bit)
access : read-write
TRDT : TRDT
bits : 10 - 13 (4 bit)
access : read-write
FHMOD : FHMOD
bits : 29 - 29 (1 bit)
access : read-write
FDMOD : FDMOD
bits : 30 - 30 (1 bit)
access : read-write
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : MPSIZ
bits : 0 - 10 (11 bit)
access : read-write
USBAEP : USBAEP
bits : 15 - 15 (1 bit)
access : read-write
EONUM_DPIP : EONUM_DPIP
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAKSTS
bits : 17 - 17 (1 bit)
access : read-only
EPTYP : EPTYP
bits : 18 - 19 (2 bit)
access : read-write
SNPM : SNPM
bits : 20 - 20 (1 bit)
access : read-write
STALL : STALL
bits : 21 - 21 (1 bit)
access : read-write
CNAK : CNAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : SNAK
bits : 27 - 27 (1 bit)
access : write-only
SD0PID_SEVNFRM : SD0PID_SEVNFRM
bits : 28 - 28 (1 bit)
access : write-only
SD1PID_SODDFRM : SD1PID_SODDFRM
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : EPDIS
bits : 30 - 30 (1 bit)
access : read-write
EPENA : EPENA
bits : 31 - 31 (1 bit)
access : read-write
This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
address_offset : 0xC08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : XFRC
bits : 0 - 0 (1 bit)
EPDISD : EPDISD
bits : 1 - 1 (1 bit)
AHBERR : AHBERR
bits : 2 - 2 (1 bit)
STUP : STUP
bits : 3 - 3 (1 bit)
OTEPDIS : OTEPDIS
bits : 4 - 4 (1 bit)
STSPHSRX : STSPHSRX
bits : 5 - 5 (1 bit)
B2BSTUP : B2BSTUP
bits : 6 - 6 (1 bit)
OUTPKTERR : OUTPKTERR
bits : 8 - 8 (1 bit)
BNA : BNA
bits : 9 - 9 (1 bit)
BERR : BERR
bits : 12 - 12 (1 bit)
NAK : NAK
bits : 13 - 13 (1 bit)
NYET : NYET
bits : 14 - 14 (1 bit)
STPKTRX : STPKTRX
bits : 15 - 15 (1 bit)
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
address_offset : 0xC10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : XFRSIZ
bits : 0 - 18 (19 bit)
PKTCNT : PKTCNT
bits : 19 - 28 (10 bit)
RXDPID_STUPCNT : RXDPID_STUPCNT
bits : 29 - 30 (2 bit)
OTG device OUT endpoint 8 DMA address register
address_offset : 0xC14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMAADDR
bits : 0 - 31 (32 bit)
This register is available in host and device modes.
address_offset : 0xE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STPPCLK : STPPCLK
bits : 0 - 0 (1 bit)
access : read-write
GATEHCLK : GATEHCLK
bits : 1 - 1 (1 bit)
access : read-write
PHYSUSP : PHYSUSP
bits : 4 - 4 (1 bit)
access : read-only
ENL1GTG : ENL1GTG
bits : 5 - 5 (1 bit)
access : read-write
PHYSLEEP : PHYSLEEP
bits : 6 - 6 (1 bit)
access : read-only
SUSP : SUSP
bits : 7 - 7 (1 bit)
access : read-only
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