CR

MIS

ICR

DR

SR

RIS

IER

CKPOL : Parallel data clock polarity This bit configures the capture edge of the parallel clock or the edge used for driving outputs, depending on OUTEN.
bits : 5 - 5 (1 bit)

DEPOL : Data enable (PSSI_DE) polarity This bit indicates the level on the PSSI_DE pin when the data are not valid on the parallel interface.
bits : 6 - 6 (1 bit)

RDYPOL : Ready (PSSI_RDY) polarity This bit indicates the level on the PSSI_RDY pin when the data are not valid on the parallel interface.
bits : 8 - 8 (1 bit)

EDM : Extended data mode
bits : 10 - 11 (2 bit)

ENABLE : PSSI enable The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE=1, the content of PSSI_CR must not be changed, except for the ENABLE bit itself. All configuration bits can change as soon as ENABLE changes from 0 to 1. The DMA controller and all PSSI configuration registers must be programmed correctly before setting the ENABLE bit to 1. The ENABLE bit and the DCMI ENABLE bit (bit 15 of DCMI_CR) must not be set to 1 at the same time.
bits : 14 - 14 (1 bit)

DERDYCFG : Data enable and ready configuration When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or 111), it is still the RDYPOL bit which determines its polarity. Similarly, when the PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still the DEPOL bit which determines its polarity.
bits : 18 - 20 (3 bit)

DMAEN : DMA enable bit
bits : 30 - 30 (1 bit)

OUTEN : Data direction selection bit
bits : 31 - 31 (1 bit)

OVR_MIS : OVR_MIS
bits : 1 - 1 (1 bit)

OVR_ISC : OVR_ISC
bits : 1 - 1 (1 bit)

BYTE0 : Data byte 0
bits : 0 - 7 (8 bit)

BYTE1 : Data byte 1
bits : 8 - 15 (8 bit)

BYTE2 : Data byte 2
bits : 16 - 23 (8 bit)

BYTE3 : Data byte 3
bits : 24 - 31 (8 bit)

RTT4B : RTT4B
bits : 2 - 2 (1 bit)

RTT1B : RTT1B
bits : 3 - 3 (1 bit)

OVR_RIS : OVR_RIS
bits : 1 - 1 (1 bit)

OVR_IE : OVR_IE
bits : 1 - 1 (1 bit)