\n

RAMCFG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

RAM1CR

RAM5CR

RAM5IER

RAM5ISR

RAM5SEAR

RAM5DEAR

RAM5ICR

RAM1ERKEYR

RAM2CR

RAM2IER

RAM2ISR

RAM2SEAR

RAM2DEAR

RAM2ICR

RAM2WPR1

RAM2WPR2

RAM2ECCKEYR

RAM2ERKEYR

RAM1ISR

RAM3CR

RAM3IER

RAM3ISR

RAM3SEAR

RAM3DEAR

RAM3ICR

RAM3ECCKEYR

RAM3ERKEYR

RAM4CR

RAM4ISR

RAM4ERKEYR


RAM1CR

RAMCFG SRAM x control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAM1CR RAM1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCE ALE SRAMER WSC

ECCE : ECCE
bits : 0 - 0 (1 bit)

ALE : ALE
bits : 4 - 4 (1 bit)

SRAMER : SRAMER
bits : 8 - 8 (1 bit)

WSC : WSC
bits : 16 - 18 (3 bit)


RAM5CR

RAMCFG SRAM x control register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAM5CR RAM5CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCE ALE SRAMER WSC

ECCE : ECCE
bits : 0 - 0 (1 bit)

ALE : ALE
bits : 4 - 4 (1 bit)

SRAMER : SRAMER
bits : 8 - 8 (1 bit)

WSC : WSC
bits : 16 - 18 (3 bit)


RAM5IER

RAMCFG SRAM x interrupt enable register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAM5IER RAM5IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEIE DEIE ECCNMI

SEIE : SEIE
bits : 0 - 0 (1 bit)

DEIE : DEIE
bits : 1 - 1 (1 bit)

ECCNMI : ECCNMI
bits : 3 - 3 (1 bit)


RAM5ISR

RAMCFG RAMx interrupt status register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAM5ISR RAM5ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEDC DED SRAMBUSY

SEDC : SEDC
bits : 0 - 0 (1 bit)

DED : DED
bits : 1 - 1 (1 bit)

SRAMBUSY : SRAMBUSY
bits : 8 - 8 (1 bit)


RAM5SEAR

RAMCFG RAM x ECC single error address register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAM5SEAR RAM5SEAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ESEA

ESEA : ESEA
bits : 0 - 31 (32 bit)


RAM5DEAR

RAMCFG RAM x ECC double error address register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAM5DEAR RAM5DEAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EDEA

EDEA : EDEA
bits : 0 - 31 (32 bit)


RAM5ICR

RAMCFG RAM x interrupt clear register x
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAM5ICR RAM5ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSEDC CDED

CSEDC : CSEDC
bits : 0 - 0 (1 bit)

CDED : CDED
bits : 1 - 1 (1 bit)


RAM1ERKEYR

RAMCFG SRAM x erase key register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RAM1ERKEYR RAM1ERKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASEKEY

ERASEKEY : ERASEKEY
bits : 0 - 7 (8 bit)


RAM2CR

RAMCFG SRAM x control register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAM2CR RAM2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCE ALE SRAMER WSC

ECCE : ECCE
bits : 0 - 0 (1 bit)

ALE : ALE
bits : 4 - 4 (1 bit)

SRAMER : SRAMER
bits : 8 - 8 (1 bit)

WSC : WSC
bits : 16 - 18 (3 bit)


RAM2IER

RAMCFG SRAM x interrupt enable register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAM2IER RAM2IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEIE DEIE ECCNMI

SEIE : SEIE
bits : 0 - 0 (1 bit)

DEIE : DEIE
bits : 1 - 1 (1 bit)

ECCNMI : ECCNMI
bits : 3 - 3 (1 bit)


RAM2ISR

RAMCFG RAMx interrupt status register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAM2ISR RAM2ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEDC DED SRAMBUSY

SEDC : SEDC
bits : 0 - 0 (1 bit)

DED : DED
bits : 1 - 1 (1 bit)

SRAMBUSY : SRAMBUSY
bits : 8 - 8 (1 bit)


RAM2SEAR

RAMCFG RAM x ECC single error address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAM2SEAR RAM2SEAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ESEA

ESEA : ESEA
bits : 0 - 31 (32 bit)


RAM2DEAR

RAMCFG RAM x ECC double error address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAM2DEAR RAM2DEAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EDEA

EDEA : EDEA
bits : 0 - 31 (32 bit)


RAM2ICR

RAMCFG RAM x interrupt clear register x
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAM2ICR RAM2ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSEDC CDED

CSEDC : CSEDC
bits : 0 - 0 (1 bit)

CDED : CDED
bits : 1 - 1 (1 bit)


RAM2WPR1

RAMCFG SRAM2 write protection register 1
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAM2WPR1 RAM2WPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0WP P1WP P2WP P3WP P4WP P5WP P6WP P7WP P8WP P9WP P10WP P11WP P12WP P13WP P14WP P15WP P16WP P17WP P18WP P19WP P20WP P21WP P22WP P23WP P24WP P25WP P26WP P27WP P28WP P29WP P30WP P31WP

P0WP : P0WP
bits : 0 - 0 (1 bit)

P1WP : P1WP
bits : 1 - 1 (1 bit)

P2WP : P2WP
bits : 2 - 2 (1 bit)

P3WP : P3WP
bits : 3 - 3 (1 bit)

P4WP : P4WP
bits : 4 - 4 (1 bit)

P5WP : P5WP
bits : 5 - 5 (1 bit)

P6WP : P6WP
bits : 6 - 6 (1 bit)

P7WP : P7WP
bits : 7 - 7 (1 bit)

P8WP : P8WP
bits : 8 - 8 (1 bit)

P9WP : P9WP
bits : 9 - 9 (1 bit)

P10WP : P10WP
bits : 10 - 10 (1 bit)

P11WP : P11WP
bits : 11 - 11 (1 bit)

P12WP : P12WP
bits : 12 - 12 (1 bit)

P13WP : P13WP
bits : 13 - 13 (1 bit)

P14WP : P14WP
bits : 14 - 14 (1 bit)

P15WP : P15WP
bits : 15 - 15 (1 bit)

P16WP : P16WP
bits : 16 - 16 (1 bit)

P17WP : P17WP
bits : 17 - 17 (1 bit)

P18WP : P18WP
bits : 18 - 18 (1 bit)

P19WP : P19WP
bits : 19 - 19 (1 bit)

P20WP : P20WP
bits : 20 - 20 (1 bit)

P21WP : P21WP
bits : 21 - 21 (1 bit)

P22WP : P22WP
bits : 22 - 22 (1 bit)

P23WP : P23WP
bits : 23 - 23 (1 bit)

P24WP : P24WP
bits : 24 - 24 (1 bit)

P25WP : P25WP
bits : 25 - 25 (1 bit)

P26WP : P26WP
bits : 26 - 26 (1 bit)

P27WP : P27WP
bits : 27 - 27 (1 bit)

P28WP : P28WP
bits : 28 - 28 (1 bit)

P29WP : P29WP
bits : 29 - 29 (1 bit)

P30WP : P30WP
bits : 30 - 30 (1 bit)

P31WP : P31WP
bits : 31 - 31 (1 bit)


RAM2WPR2

RAMCFG SRAM2 write protection register 2
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAM2WPR2 RAM2WPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P32WP P33WP P34WP P35WP P36WP P37WP P38WP P39WP P40WP P41WP P42WP P43WP P44WP P45WP P46WP P47WP P48WP P49WP P50WP P51WP P52WP P53WP P54WP P55WP P56WP P57WP P58WP P59WP P60WP P61WP P62WP P63WP

P32WP : P32WP
bits : 0 - 0 (1 bit)

P33WP : P33WP
bits : 1 - 1 (1 bit)

P34WP : P34WP
bits : 2 - 2 (1 bit)

P35WP : P35WP
bits : 3 - 3 (1 bit)

P36WP : P36WP
bits : 4 - 4 (1 bit)

P37WP : P37WP
bits : 5 - 5 (1 bit)

P38WP : P38WP
bits : 6 - 6 (1 bit)

P39WP : P39WP
bits : 7 - 7 (1 bit)

P40WP : P40WP
bits : 8 - 8 (1 bit)

P41WP : P41WP
bits : 9 - 9 (1 bit)

P42WP : P42WP
bits : 10 - 10 (1 bit)

P43WP : P43WP
bits : 11 - 11 (1 bit)

P44WP : P44WP
bits : 12 - 12 (1 bit)

P45WP : P45WP
bits : 13 - 13 (1 bit)

P46WP : P46WP
bits : 14 - 14 (1 bit)

P47WP : P47WP
bits : 15 - 15 (1 bit)

P48WP : P48WP
bits : 16 - 16 (1 bit)

P49WP : P49WP
bits : 17 - 17 (1 bit)

P50WP : P50WP
bits : 18 - 18 (1 bit)

P51WP : P51WP
bits : 19 - 19 (1 bit)

P52WP : P52WP
bits : 20 - 20 (1 bit)

P53WP : P53WP
bits : 21 - 21 (1 bit)

P54WP : P54WP
bits : 22 - 22 (1 bit)

P55WP : P55WP
bits : 23 - 23 (1 bit)

P56WP : P56WP
bits : 24 - 24 (1 bit)

P57WP : P57WP
bits : 25 - 25 (1 bit)

P58WP : P58WP
bits : 26 - 26 (1 bit)

P59WP : P59WP
bits : 27 - 27 (1 bit)

P60WP : P60WP
bits : 28 - 28 (1 bit)

P61WP : P61WP
bits : 29 - 29 (1 bit)

P62WP : P62WP
bits : 30 - 30 (1 bit)

P63WP : P63WP
bits : 31 - 31 (1 bit)


RAM2ECCKEYR

RAMCFG SRAM x ECC key register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RAM2ECCKEYR RAM2ECCKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCKEY

ECCKEY : ECCKEY
bits : 0 - 7 (8 bit)


RAM2ERKEYR

RAMCFG SRAM x erase key register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RAM2ERKEYR RAM2ERKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASEKEY

ERASEKEY : ERASEKEY
bits : 0 - 7 (8 bit)


RAM1ISR

RAMCFG RAMx interrupt status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAM1ISR RAM1ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEDC DED SRAMBUSY

SEDC : SEDC
bits : 0 - 0 (1 bit)

DED : DED
bits : 1 - 1 (1 bit)

SRAMBUSY : SRAMBUSY
bits : 8 - 8 (1 bit)


RAM3CR

RAMCFG SRAM x control register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAM3CR RAM3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCE ALE SRAMER WSC

ECCE : ECCE
bits : 0 - 0 (1 bit)

ALE : ALE
bits : 4 - 4 (1 bit)

SRAMER : SRAMER
bits : 8 - 8 (1 bit)

WSC : WSC
bits : 16 - 18 (3 bit)


RAM3IER

RAMCFG SRAM x interrupt enable register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAM3IER RAM3IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEIE DEIE ECCNMI

SEIE : SEIE
bits : 0 - 0 (1 bit)

DEIE : DEIE
bits : 1 - 1 (1 bit)

ECCNMI : ECCNMI
bits : 3 - 3 (1 bit)


RAM3ISR

RAMCFG RAMx interrupt status register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAM3ISR RAM3ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEDC DED SRAMBUSY

SEDC : SEDC
bits : 0 - 0 (1 bit)

DED : DED
bits : 1 - 1 (1 bit)

SRAMBUSY : SRAMBUSY
bits : 8 - 8 (1 bit)


RAM3SEAR

RAMCFG RAM x ECC single error address register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAM3SEAR RAM3SEAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ESEA

ESEA : ESEA
bits : 0 - 31 (32 bit)


RAM3DEAR

RAMCFG RAM x ECC double error address register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAM3DEAR RAM3DEAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EDEA

EDEA : EDEA
bits : 0 - 31 (32 bit)


RAM3ICR

RAMCFG RAM x interrupt clear register x
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAM3ICR RAM3ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSEDC CDED

CSEDC : CSEDC
bits : 0 - 0 (1 bit)

CDED : CDED
bits : 1 - 1 (1 bit)


RAM3ECCKEYR

RAMCFG SRAM x ECC key register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RAM3ECCKEYR RAM3ECCKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCKEY

ECCKEY : ECCKEY
bits : 0 - 7 (8 bit)


RAM3ERKEYR

RAMCFG SRAM x erase key register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RAM3ERKEYR RAM3ERKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASEKEY

ERASEKEY : ERASEKEY
bits : 0 - 7 (8 bit)


RAM4CR

RAMCFG SRAM x control register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAM4CR RAM4CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCE ALE SRAMER WSC

ECCE : ECCE
bits : 0 - 0 (1 bit)

ALE : ALE
bits : 4 - 4 (1 bit)

SRAMER : SRAMER
bits : 8 - 8 (1 bit)

WSC : WSC
bits : 16 - 18 (3 bit)


RAM4ISR

RAMCFG RAMx interrupt status register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAM4ISR RAM4ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEDC DED SRAMBUSY

SEDC : SEDC
bits : 0 - 0 (1 bit)

DED : DED
bits : 1 - 1 (1 bit)

SRAMBUSY : SRAMBUSY
bits : 8 - 8 (1 bit)


RAM4ERKEYR

RAMCFG SRAM x erase key register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RAM4ERKEYR RAM4ERKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASEKEY

ERASEKEY : ERASEKEY
bits : 0 - 7 (8 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.