\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
rising trigger selection register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RT : Rising trigger event configuration bit of Configurable Event input
bits : 0 - 20 (21 bit)
rising trigger selection register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RT33 : Rising trigger event configuration bit of Configurable Event input
bits : 1 - 1 (1 bit)
RT40 : Rising trigger event configuration bit of Configurable Event input 40
bits : 8 - 8 (1 bit)
RT41 : Rising trigger event configuration bit of Configurable Event input 41
bits : 9 - 9 (1 bit)
falling trigger selection register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FT33 : Falling trigger event configuration bit of Configurable Event input
bits : 1 - 1 (1 bit)
FT40 : Falling trigger event configuration bit of configurable event input 40
bits : 8 - 8 (1 bit)
FT41 : Falling trigger event configuration bit of configurable event input 41
bits : 9 - 9 (1 bit)
software interrupt event register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWI33 : Software interrupt on event
bits : 1 - 1 (1 bit)
SWI40 : Software interrupt on event
bits : 8 - 8 (1 bit)
SWI41 : Software interrupt on event
bits : 9 - 9 (1 bit)
pending register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIF33 : Configurable event inputs x+32 Pending bit.
bits : 1 - 1 (1 bit)
PIF40 : Configurable event inputs x+32 Pending bit.
bits : 8 - 8 (1 bit)
PIF41 : Configurable event inputs x+32 Pending bit.
bits : 9 - 9 (1 bit)
falling trigger selection register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FT : Falling trigger event configuration bit of Configurable Event input
bits : 0 - 20 (21 bit)
software interrupt event register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWI : Software interrupt on event
bits : 0 - 20 (21 bit)
CPUm wakeup with interrupt mask register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM : CPU(m) wakeup with interrupt Mask on Event input
bits : 0 - 31 (32 bit)
CPUm wakeup with event mask register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM0_15 : CPU(m) Wakeup with event generation Mask on Event input
bits : 0 - 15 (16 bit)
EM17_20 : CPU(m) Wakeup with event generation Mask on Event input
bits : 17 - 20 (4 bit)
CPUm wakeup with interrupt mask register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM : CPUm Wakeup with interrupt Mask on Event input
bits : 1 - 17 (17 bit)
CPUm wakeup with event mask register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM : CPU(m) Wakeup with event generation Mask on Event input
bits : 8 - 9 (2 bit)
EXTI pending register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIF : Configurable event inputs Pending bit
bits : 0 - 20 (21 bit)
CPUm wakeup with interrupt mask register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM : CPU(m) wakeup with interrupt Mask on Event input
bits : 0 - 31 (32 bit)
CPUm wakeup with event mask register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM0_15 : CPU(m) Wakeup with event generation Mask on Event input
bits : 0 - 15 (16 bit)
EM17_20 : CPU(m) Wakeup with event generation Mask on Event input
bits : 17 - 20 (4 bit)
CPUm wakeup with interrupt mask register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM : CPUm Wakeup with interrupt Mask on Event input
bits : 1 - 17 (17 bit)
CPUm wakeup with event mask register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM : CPU(m) Wakeup with event generation Mask on Event input
bits : 8 - 9 (2 bit)
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