\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
MCU Device ID Code Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEV_ID : Device Identifier
bits : 0 - 11 (12 bit)
REV_ID : Revision Identifier
bits : 16 - 31 (16 bit)
APB1 Low Freeze Register CPU1
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_TIMER2_STOP : Debug Timer 2 stopped when Core is halted
bits : 0 - 0 (1 bit)
DBG_RTC_STOP : RTC counter stopped when core is halted
bits : 10 - 10 (1 bit)
DBG_WWDG_STOP : WWDG counter stopped when core is halted
bits : 11 - 11 (1 bit)
DBG_IWDG_STOP : IWDG counter stopped when core is halted
bits : 12 - 12 (1 bit)
DBG_I2C1_STOP : Debug I2C1 SMBUS timeout stopped when Core is halted
bits : 21 - 21 (1 bit)
DBG_I2C3_STOP : Debug I2C3 SMBUS timeout stopped when core is halted
bits : 23 - 23 (1 bit)
DBG_LPTIM1_STOP : Debug LPTIM1 stopped when Core is halted
bits : 31 - 31 (1 bit)
Debug MCU Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_SLEEP : Debug Sleep Mode
bits : 0 - 0 (1 bit)
DBG_STOP : Debug Stop Mode
bits : 1 - 1 (1 bit)
DBG_STANDBY : Debug Standby Mode
bits : 2 - 2 (1 bit)
TRACE_IOEN : Trace port and clock enable
bits : 5 - 5 (1 bit)
TRGOEN : External trigger output enable
bits : 28 - 28 (1 bit)
APB1 Low Freeze Register CPU2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_LPTIM2_STOP : LPTIM2 counter stopped when core is halted
bits : 0 - 0 (1 bit)
DBG_RTC_STOP : RTC counter stopped when core is halted
bits : 10 - 10 (1 bit)
DBG_IWDG_STOP : IWDG stopped when core is halted
bits : 12 - 12 (1 bit)
DBG_I2C1_STOP : I2C1 SMBUS timeout stopped when core is halted
bits : 21 - 21 (1 bit)
DBG_I2C3_STOP : I2C3 SMBUS timeout stopped when core is halted
bits : 23 - 23 (1 bit)
DBG_LPTIM1_STOP : LPTIM1 counter stopped when core is halted
bits : 31 - 31 (1 bit)
APB1 High Freeze Register CPU1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_LPTIM2_STOP : LPTIM2 counter stopped when core is halted
bits : 5 - 5 (1 bit)
APB1 High Freeze Register CPU2
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_LPTIM2_STOP : LPTIM2 counter stopped when core is halted
bits : 5 - 5 (1 bit)
APB2 Freeze Register CPU2
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : C2APB1FZR2
reset_Mask : 0x0
DBG_TIM1_STOP : TIM1 counter stopped when core is halted
bits : 11 - 11 (1 bit)
DBG_TIM16_STOP : TIM16 counter stopped when core is halted
bits : 17 - 17 (1 bit)
DBG_TIM17_STOP : TIM17 counter stopped when core is halted
bits : 18 - 18 (1 bit)
APB2 Freeze Register CPU1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_TIM1_STOP : TIM1 counter stopped when core is halted
bits : 11 - 11 (1 bit)
DBG_TIM16_STOP : TIM16 counter stopped when core is halted
bits : 17 - 17 (1 bit)
DBG_TIM17_STOP : TIM17 counter stopped when core is halted
bits : 18 - 18 (1 bit)
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