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PWR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CR1

SR1

SR2

SCR

CR5

PUCRA

PDCRA

PUCRB

PDCRB

PUCRC

PDCRC

PUCRD

PDCRD

CR2

PUCRE

PDCRE

PUCRH

PDCRH

CR3

C2CR1

C2CR3

EXTSCR

CR4


CR1

Power control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPMS FPDR FPDS DBP VOS LPR

LPMS : Low-power mode selection for CPU1
bits : 0 - 2 (3 bit)

FPDR : Flash power down mode during LPRun for CPU1
bits : 4 - 4 (1 bit)

FPDS : Flash power down mode during LPsSleep for CPU1
bits : 5 - 5 (1 bit)

DBP : Disable backup domain write protection
bits : 8 - 8 (1 bit)

VOS : Voltage scaling range selection
bits : 9 - 10 (2 bit)

LPR : Low-power run
bits : 14 - 14 (1 bit)


SR1

Power status register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR1 SR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CWUF1 CWUF2 CWUF3 CWUF4 CWUF5 SDFBF BORHF BLEWUF WUF802 CRPEF BLEAF AF802 C2HF WUFI

CWUF1 : Wakeup flag 1
bits : 0 - 0 (1 bit)

CWUF2 : Wakeup flag 2
bits : 1 - 1 (1 bit)

CWUF3 : Wakeup flag 3
bits : 2 - 2 (1 bit)

CWUF4 : Wakeup flag 4
bits : 3 - 3 (1 bit)

CWUF5 : Wakeup flag 5
bits : 4 - 4 (1 bit)

SDFBF : Step Down converter forced in Bypass interrupt flag
bits : 7 - 7 (1 bit)

BORHF : BORH interrupt flag
bits : 8 - 8 (1 bit)

BLEWUF : BLE wakeup interrupt flag
bits : 9 - 9 (1 bit)

WUF802 : 802.15.4 wakeup interrupt flag
bits : 10 - 10 (1 bit)

CRPEF : Enable critical radio phase end of activity interrupt flag
bits : 11 - 11 (1 bit)

BLEAF : BLE end of activity interrupt flag
bits : 12 - 12 (1 bit)

AF802 : 802.15.4 end of activity interrupt flag
bits : 13 - 13 (1 bit)

C2HF : CPU2 Hold interrupt flag
bits : 14 - 14 (1 bit)

WUFI : Internal Wakeup interrupt flag
bits : 15 - 15 (1 bit)


SR2

Power status register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR2 SR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDBF SDSMPSF REGLPS REGLPF VOSF PVDO PVMO1 PVMO3

SDBF : Step Down converter Bypass mode flag
bits : 0 - 0 (1 bit)

SDSMPSF : Step Down converter SMPS mode flag
bits : 1 - 1 (1 bit)

REGLPS : Low-power regulator started
bits : 8 - 8 (1 bit)

REGLPF : Low-power regulator flag
bits : 9 - 9 (1 bit)

VOSF : Voltage scaling flag
bits : 10 - 10 (1 bit)

PVDO : Power voltage detector output
bits : 11 - 11 (1 bit)

PVMO1 : Peripheral voltage monitoring output: VDDUSB vs. 1.2 V
bits : 12 - 12 (1 bit)

PVMO3 : Peripheral voltage monitoring output: VDDA vs. 1.62 V
bits : 14 - 14 (1 bit)


SCR

Power status clear register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SCR SCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CWUF1 CWUF2 CWUF3 CWUF4 CWUF5 CSMPSFBF CBORHF CBLEWUF C802WUF CCRPEF CBLEAF C802AF CC2HF

CWUF1 : Clear wakeup flag 1
bits : 0 - 0 (1 bit)

CWUF2 : Clear wakeup flag 2
bits : 1 - 1 (1 bit)

CWUF3 : Clear wakeup flag 3
bits : 2 - 2 (1 bit)

CWUF4 : Clear wakeup flag 4
bits : 3 - 3 (1 bit)

CWUF5 : Clear wakeup flag 5
bits : 4 - 4 (1 bit)

CSMPSFBF : Clear SMPS Step Down converter forced in Bypass interrupt flag
bits : 7 - 7 (1 bit)

CBORHF : Clear BORH interrupt flag
bits : 8 - 8 (1 bit)

CBLEWUF : Clear BLE wakeup interrupt flag
bits : 9 - 9 (1 bit)

C802WUF : Clear 802.15.4 wakeup interrupt flag
bits : 10 - 10 (1 bit)

CCRPEF : Clear critical radio phase end of activity interrupt flag
bits : 11 - 11 (1 bit)

CBLEAF : Clear BLE end of activity interrupt flag
bits : 12 - 12 (1 bit)

C802AF : Clear 802.15.4 end of activity interrupt flag
bits : 13 - 13 (1 bit)

CC2HF : Clear CPU2 Hold interrupt flag
bits : 14 - 14 (1 bit)


CR5

Power control register 5
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR5 CR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDVOS SDSC BORHC SMPSCFG SDBEN SDEB

SDVOS : Step Down converter voltage output scaling
bits : 0 - 3 (4 bit)

SDSC : Step Down converter supplt startup current selection
bits : 4 - 6 (3 bit)

BORHC : BORH configuration selection
bits : 8 - 8 (1 bit)

SMPSCFG : VOS configuration selection (non user)
bits : 9 - 9 (1 bit)

SDBEN : Enable Step Down converter Bypass mode enabled
bits : 14 - 14 (1 bit)

SDEB : Enable Step Down converter SMPS mode enabled
bits : 15 - 15 (1 bit)


PUCRA

Power Port A pull-up control register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUCRA PUCRA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0 PU1 PU2 PU3 PU4 PU5 PU6 PU7 PU8 PU9 PU10 PU11 PU12 PU13 PU15

PU0 : Port A pull-up bit y (y=0..15)
bits : 0 - 0 (1 bit)

PU1 : Port A pull-up bit y (y=0..15)
bits : 1 - 1 (1 bit)

PU2 : Port A pull-up bit y (y=0..15)
bits : 2 - 2 (1 bit)

PU3 : Port A pull-up bit y (y=0..15)
bits : 3 - 3 (1 bit)

PU4 : Port A pull-up bit y (y=0..15)
bits : 4 - 4 (1 bit)

PU5 : Port A pull-up bit y (y=0..15)
bits : 5 - 5 (1 bit)

PU6 : Port A pull-up bit y (y=0..15)
bits : 6 - 6 (1 bit)

PU7 : Port A pull-up bit y (y=0..15)
bits : 7 - 7 (1 bit)

PU8 : Port A pull-up bit y (y=0..15)
bits : 8 - 8 (1 bit)

PU9 : Port A pull-up bit y (y=0..15)
bits : 9 - 9 (1 bit)

PU10 : Port A pull-up bit y (y=0..15)
bits : 10 - 10 (1 bit)

PU11 : Port A pull-up bit y (y=0..15)
bits : 11 - 11 (1 bit)

PU12 : Port A pull-up bit y (y=0..15)
bits : 12 - 12 (1 bit)

PU13 : Port A pull-up bit y (y=0..15)
bits : 13 - 13 (1 bit)

PU15 : Port A pull-up bit y (y=0..15)
bits : 15 - 15 (1 bit)


PDCRA

Power Port A pull-down control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDCRA PDCRA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD14

PD0 : Port A pull-down bit y (y=0..15)
bits : 0 - 0 (1 bit)

PD1 : Port A pull-down bit y (y=0..15)
bits : 1 - 1 (1 bit)

PD2 : Port A pull-down bit y (y=0..15)
bits : 2 - 2 (1 bit)

PD3 : Port A pull-down bit y (y=0..15)
bits : 3 - 3 (1 bit)

PD4 : Port A pull-down bit y (y=0..15)
bits : 4 - 4 (1 bit)

PD5 : Port A pull-down bit y (y=0..15)
bits : 5 - 5 (1 bit)

PD6 : Port A pull-down bit y (y=0..15)
bits : 6 - 6 (1 bit)

PD7 : Port A pull-down bit y (y=0..15)
bits : 7 - 7 (1 bit)

PD8 : Port A pull-down bit y (y=0..15)
bits : 8 - 8 (1 bit)

PD9 : Port A pull-down bit y (y=0..15)
bits : 9 - 9 (1 bit)

PD10 : Port A pull-down bit y (y=0..15)
bits : 10 - 10 (1 bit)

PD11 : Port A pull-down bit y (y=0..15)
bits : 11 - 11 (1 bit)

PD12 : Port A pull-down bit y (y=0..15)
bits : 12 - 12 (1 bit)

PD14 : Port A pull-down bit y (y=0..15)
bits : 14 - 14 (1 bit)


PUCRB

Power Port B pull-up control register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUCRB PUCRB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0 PU1 PU2 PU3 PU4 PU5 PU6 PU7 PU8 PU9 PU10 PU11 PU12 PU13 PU14 PU15

PU0 : Port B pull-up bit y (y=0..15)
bits : 0 - 0 (1 bit)

PU1 : Port B pull-up bit y (y=0..15)
bits : 1 - 1 (1 bit)

PU2 : Port B pull-up bit y (y=0..15)
bits : 2 - 2 (1 bit)

PU3 : Port B pull-up bit y (y=0..15)
bits : 3 - 3 (1 bit)

PU4 : Port B pull-up bit y (y=0..15)
bits : 4 - 4 (1 bit)

PU5 : Port B pull-up bit y (y=0..15)
bits : 5 - 5 (1 bit)

PU6 : Port B pull-up bit y (y=0..15)
bits : 6 - 6 (1 bit)

PU7 : Port B pull-up bit y (y=0..15)
bits : 7 - 7 (1 bit)

PU8 : Port B pull-up bit y (y=0..15)
bits : 8 - 8 (1 bit)

PU9 : Port B pull-up bit y (y=0..15)
bits : 9 - 9 (1 bit)

PU10 : Port B pull-up bit y (y=0..15)
bits : 10 - 10 (1 bit)

PU11 : Port B pull-up bit y (y=0..15)
bits : 11 - 11 (1 bit)

PU12 : Port B pull-up bit y (y=0..15)
bits : 12 - 12 (1 bit)

PU13 : Port B pull-up bit y (y=0..15)
bits : 13 - 13 (1 bit)

PU14 : Port B pull-up bit y (y=0..15)
bits : 14 - 14 (1 bit)

PU15 : Port B pull-up bit y (y=0..15)
bits : 15 - 15 (1 bit)


PDCRB

Power Port B pull-down control register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDCRB PDCRB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD0 PD1 PD2 PD3 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15

PD0 : Port B pull-down bit y (y=0..15)
bits : 0 - 0 (1 bit)

PD1 : Port B pull-down bit y (y=0..15)
bits : 1 - 1 (1 bit)

PD2 : Port B pull-down bit y (y=0..15)
bits : 2 - 2 (1 bit)

PD3 : Port B pull-down bit y (y=0..15)
bits : 3 - 3 (1 bit)

PD5 : Port B pull-down bit y (y=0..15)
bits : 5 - 5 (1 bit)

PD6 : Port B pull-down bit y (y=0..15)
bits : 6 - 6 (1 bit)

PD7 : Port B pull-down bit y (y=0..15)
bits : 7 - 7 (1 bit)

PD8 : Port B pull-down bit y (y=0..15)
bits : 8 - 8 (1 bit)

PD9 : Port B pull-down bit y (y=0..15)
bits : 9 - 9 (1 bit)

PD10 : Port B pull-down bit y (y=0..15)
bits : 10 - 10 (1 bit)

PD11 : Port B pull-down bit y (y=0..15)
bits : 11 - 11 (1 bit)

PD12 : Port B pull-down bit y (y=0..15)
bits : 12 - 12 (1 bit)

PD13 : Port B pull-down bit y (y=0..15)
bits : 13 - 13 (1 bit)

PD14 : Port B pull-down bit y (y=0..15)
bits : 14 - 14 (1 bit)

PD15 : Port B pull-down bit y (y=0..15)
bits : 15 - 15 (1 bit)


PUCRC

Power Port C pull-up control register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUCRC PUCRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0 PU1 PU2 PU3 PU4 PU5 PU6 PU7 PU8 PU9 PU10 PU11 PU12 PU13 PU14 PU15

PU0 : Port C pull-up bit y (y=0..15)
bits : 0 - 0 (1 bit)

PU1 : Port C pull-up bit y (y=0..15)
bits : 1 - 1 (1 bit)

PU2 : Port C pull-up bit y (y=0..15)
bits : 2 - 2 (1 bit)

PU3 : Port C pull-up bit y (y=0..15)
bits : 3 - 3 (1 bit)

PU4 : Port C pull-up bit y (y=0..15)
bits : 4 - 4 (1 bit)

PU5 : Port C pull-up bit y (y=0..15)
bits : 5 - 5 (1 bit)

PU6 : Port C pull-up bit y (y=0..15)
bits : 6 - 6 (1 bit)

PU7 : Port C pull-up bit y (y=0..15)
bits : 7 - 7 (1 bit)

PU8 : Port C pull-up bit y (y=0..15)
bits : 8 - 8 (1 bit)

PU9 : Port C pull-up bit y (y=0..15)
bits : 9 - 9 (1 bit)

PU10 : Port C pull-up bit y (y=0..15)
bits : 10 - 10 (1 bit)

PU11 : Port C pull-up bit y (y=0..15)
bits : 11 - 11 (1 bit)

PU12 : Port C pull-up bit y (y=0..15)
bits : 12 - 12 (1 bit)

PU13 : Port C pull-up bit y (y=0..15)
bits : 13 - 13 (1 bit)

PU14 : Port C pull-up bit y (y=0..15)
bits : 14 - 14 (1 bit)

PU15 : Port C pull-up bit y (y=0..15)
bits : 15 - 15 (1 bit)


PDCRC

Power Port C pull-down control register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDCRC PDCRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15

PD0 : Port C pull-down bit y (y=0..15)
bits : 0 - 0 (1 bit)

PD1 : Port C pull-down bit y (y=0..15)
bits : 1 - 1 (1 bit)

PD2 : Port C pull-down bit y (y=0..15)
bits : 2 - 2 (1 bit)

PD3 : Port C pull-down bit y (y=0..15)
bits : 3 - 3 (1 bit)

PD4 : Port C pull-down bit y (y=0..15)
bits : 4 - 4 (1 bit)

PD5 : Port C pull-down bit y (y=0..15)
bits : 5 - 5 (1 bit)

PD6 : Port C pull-down bit y (y=0..15)
bits : 6 - 6 (1 bit)

PD7 : Port C pull-down bit y (y=0..15)
bits : 7 - 7 (1 bit)

PD8 : Port C pull-down bit y (y=0..15)
bits : 8 - 8 (1 bit)

PD9 : Port C pull-down bit y (y=0..15)
bits : 9 - 9 (1 bit)

PD10 : Port C pull-down bit y (y=0..15)
bits : 10 - 10 (1 bit)

PD11 : Port C pull-down bit y (y=0..15)
bits : 11 - 11 (1 bit)

PD12 : Port C pull-down bit y (y=0..15)
bits : 12 - 12 (1 bit)

PD13 : Port C pull-down bit y (y=0..15)
bits : 13 - 13 (1 bit)

PD14 : Port C pull-down bit y (y=0..15)
bits : 14 - 14 (1 bit)

PD15 : Port C pull-down bit y (y=0..15)
bits : 15 - 15 (1 bit)


PUCRD

Power Port D pull-up control register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUCRD PUCRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0 PU1 PU2 PU3 PU4 PU5 PU6 PU7 PU8 PU9 PU10 PU11 PU12 PU13 PU14 PU15

PU0 : Port D pull-up bit y (y=0..15)
bits : 0 - 0 (1 bit)

PU1 : Port D pull-up bit y (y=0..15)
bits : 1 - 1 (1 bit)

PU2 : Port D pull-up bit y (y=0..15)
bits : 2 - 2 (1 bit)

PU3 : Port D pull-up bit y (y=0..15)
bits : 3 - 3 (1 bit)

PU4 : Port D pull-up bit y (y=0..15)
bits : 4 - 4 (1 bit)

PU5 : Port D pull-up bit y (y=0..15)
bits : 5 - 5 (1 bit)

PU6 : Port D pull-up bit y (y=0..15)
bits : 6 - 6 (1 bit)

PU7 : Port D pull-up bit y (y=0..15)
bits : 7 - 7 (1 bit)

PU8 : Port D pull-up bit y (y=0..15)
bits : 8 - 8 (1 bit)

PU9 : Port D pull-up bit y (y=0..15)
bits : 9 - 9 (1 bit)

PU10 : Port D pull-up bit y (y=0..15)
bits : 10 - 10 (1 bit)

PU11 : Port D pull-up bit y (y=0..15)
bits : 11 - 11 (1 bit)

PU12 : Port D pull-up bit y (y=0..15)
bits : 12 - 12 (1 bit)

PU13 : Port D pull-up bit y (y=0..15)
bits : 13 - 13 (1 bit)

PU14 : Port D pull-up bit y (y=0..15)
bits : 14 - 14 (1 bit)

PU15 : Port D pull-up bit y (y=0..15)
bits : 15 - 15 (1 bit)


PDCRD

Power Port D pull-down control register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDCRD PDCRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15

PD0 : Port D pull-down bit y (y=0..15)
bits : 0 - 0 (1 bit)

PD1 : Port D pull-down bit y (y=0..15)
bits : 1 - 1 (1 bit)

PD2 : Port D pull-down bit y (y=0..15)
bits : 2 - 2 (1 bit)

PD3 : Port D pull-down bit y (y=0..15)
bits : 3 - 3 (1 bit)

PD4 : Port D pull-down bit y (y=0..15)
bits : 4 - 4 (1 bit)

PD5 : Port D pull-down bit y (y=0..15)
bits : 5 - 5 (1 bit)

PD6 : Port D pull-down bit y (y=0..15)
bits : 6 - 6 (1 bit)

PD7 : Port D pull-down bit y (y=0..15)
bits : 7 - 7 (1 bit)

PD8 : Port D pull-down bit y (y=0..15)
bits : 8 - 8 (1 bit)

PD9 : Port D pull-down bit y (y=0..15)
bits : 9 - 9 (1 bit)

PD10 : Port D pull-down bit y (y=0..15)
bits : 10 - 10 (1 bit)

PD11 : Port D pull-down bit y (y=0..15)
bits : 11 - 11 (1 bit)

PD12 : Port D pull-down bit y (y=0..15)
bits : 12 - 12 (1 bit)

PD13 : Port D pull-down bit y (y=0..15)
bits : 13 - 13 (1 bit)

PD14 : Port D pull-down bit y (y=0..15)
bits : 14 - 14 (1 bit)

PD15 : Port D pull-down bit y (y=0..15)
bits : 15 - 15 (1 bit)


CR2

Power control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PVDE PLS PVME1 PVME3 USV

PVDE : Power voltage detector enable
bits : 0 - 0 (1 bit)

PLS : Power voltage detector level selection
bits : 1 - 3 (3 bit)

PVME1 : Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V
bits : 4 - 4 (1 bit)

PVME3 : Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V
bits : 6 - 6 (1 bit)

USV : VDDUSB USB supply valid
bits : 10 - 10 (1 bit)


PUCRE

Power Port E pull-up control register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUCRE PUCRE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0 PU1 PU2 PU3 PU4

PU0 : Port E pull-up bit y (y=0..15)
bits : 0 - 0 (1 bit)

PU1 : Port E pull-up bit y (y=0..15)
bits : 1 - 1 (1 bit)

PU2 : Port E pull-up bit y (y=0..15)
bits : 2 - 2 (1 bit)

PU3 : Port E pull-up bit y (y=0..15)
bits : 3 - 3 (1 bit)

PU4 : Port E pull-up bit y (y=0..15)
bits : 4 - 4 (1 bit)


PDCRE

Power Port E pull-down control register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDCRE PDCRE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD0 PD1 PD2 PD3 PD4

PD0 : Port E pull-down bit y (y=0..15)
bits : 0 - 0 (1 bit)

PD1 : Port E pull-down bit y (y=0..15)
bits : 1 - 1 (1 bit)

PD2 : Port E pull-down bit y (y=0..15)
bits : 2 - 2 (1 bit)

PD3 : Port E pull-down bit y (y=0..15)
bits : 3 - 3 (1 bit)

PD4 : Port E pull-down bit y (y=0..15)
bits : 4 - 4 (1 bit)


PUCRH

Power Port H pull-up control register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUCRH PUCRH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU0 PU1 PU3

PU0 : Port H pull-up bit y (y=0..1)
bits : 0 - 0 (1 bit)

PU1 : Port H pull-up bit y (y=0..1)
bits : 1 - 1 (1 bit)

PU3 : Port H pull-up bit y (y=0..1)
bits : 3 - 3 (1 bit)


PDCRH

Power Port H pull-down control register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDCRH PDCRH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD0 PD1 PD3

PD0 : Port H pull-down bit y (y=0..1)
bits : 0 - 0 (1 bit)

PD1 : Port H pull-down bit y (y=0..1)
bits : 1 - 1 (1 bit)

PD3 : Port H pull-down bit y (y=0..1)
bits : 3 - 3 (1 bit)


CR3

Power control register 3
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR3 CR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EWUP1 EWUP2 EWUP3 EWUP4 EWUP5 EBORHSDFB RRS APC EBLEA ECRPE E802A EC2H EIWUL

EWUP1 : Enable Wakeup pin WKUP1
bits : 0 - 0 (1 bit)

EWUP2 : Enable Wakeup pin WKUP2
bits : 1 - 1 (1 bit)

EWUP3 : Enable Wakeup pin WKUP3
bits : 2 - 2 (1 bit)

EWUP4 : Enable Wakeup pin WKUP4
bits : 3 - 3 (1 bit)

EWUP5 : Enable Wakeup pin WKUP5
bits : 4 - 4 (1 bit)

EBORHSDFB : Enable BORH and Step Down counverter forced in Bypass interrups for CPU1
bits : 8 - 8 (1 bit)

RRS : SRAM2a retention in Standby mode
bits : 9 - 9 (1 bit)

APC : Apply pull-up and pull-down configuration
bits : 10 - 10 (1 bit)

EBLEA : Enable BLE end of activity interrupt for CPU1
bits : 11 - 11 (1 bit)

ECRPE : Enable critical radio phase end of activity interrupt for CPU1
bits : 12 - 12 (1 bit)

E802A : Enable end of activity interrupt for CPU1
bits : 13 - 13 (1 bit)

EC2H : Enable CPU2 Hold interrupt for CPU1
bits : 14 - 14 (1 bit)

EIWUL : Enable internal wakeup line for CPU1
bits : 15 - 15 (1 bit)


C2CR1

CPU2 Power control register 1
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2CR1 C2CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPMS FPDR FPDS BLEEWKUP EWKUP802

LPMS : Low-power mode selection for CPU2
bits : 0 - 2 (3 bit)

FPDR : Flash power down mode during LPRun for CPU2
bits : 4 - 4 (1 bit)

FPDS : Flash power down mode during LPSleep for CPU2
bits : 5 - 5 (1 bit)

BLEEWKUP : BLE external wakeup signal
bits : 14 - 14 (1 bit)

EWKUP802 : 802.15.4 external wakeup signal
bits : 15 - 15 (1 bit)


C2CR3

CPU2 Power control register 3
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2CR3 C2CR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EWUP1 EWUP2 EWUP3 EWUP4 EWUP5 EBLEWUP E802WUP APC EIWUL

EWUP1 : Enable Wakeup pin WKUP1 for CPU2
bits : 0 - 0 (1 bit)

EWUP2 : Enable Wakeup pin WKUP2 for CPU2
bits : 1 - 1 (1 bit)

EWUP3 : Enable Wakeup pin WKUP3 for CPU2
bits : 2 - 2 (1 bit)

EWUP4 : Enable Wakeup pin WKUP4 for CPU2
bits : 3 - 3 (1 bit)

EWUP5 : Enable Wakeup pin WKUP5 for CPU2
bits : 4 - 4 (1 bit)

EBLEWUP : Enable BLE host wakeup interrupt for CPU2
bits : 9 - 9 (1 bit)

E802WUP : Enable 802.15.4 host wakeup interrupt for CPU2
bits : 10 - 10 (1 bit)

APC : Apply pull-up and pull-down configuration for CPU2
bits : 12 - 12 (1 bit)

EIWUL : Enable internal wakeup line for CPU2
bits : 15 - 15 (1 bit)


EXTSCR

Power status clear register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTSCR EXTSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C1CSSF C2CSSF CCRPF C1SBF C1STOPF C2SBF C2STOPF CRPF C1DS C2DS

C1CSSF : Clear CPU1 Stop Standby flags
bits : 0 - 0 (1 bit)
access : write-only

C2CSSF : Clear CPU2 Stop Standby flags
bits : 1 - 1 (1 bit)
access : write-only

CCRPF : Clear Critical Radio system phase
bits : 2 - 2 (1 bit)
access : write-only

C1SBF : System Standby flag for CPU1
bits : 8 - 8 (1 bit)
access : read-only

C1STOPF : System Stop flag for CPU1
bits : 9 - 9 (1 bit)
access : read-only

C2SBF : System Standby flag for CPU2
bits : 10 - 10 (1 bit)
access : read-only

C2STOPF : System Stop flag for CPU2
bits : 11 - 11 (1 bit)
access : read-only

CRPF : Critical Radio system phase
bits : 13 - 13 (1 bit)
access : read-only

C1DS : CPU1 deepsleep mode
bits : 14 - 14 (1 bit)
access : read-only

C2DS : CPU2 deepsleep mode
bits : 15 - 15 (1 bit)
access : read-only


CR4

Power control register 4
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR4 CR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WP1 WP2 WP3 WP4 WP5 VBE VBRS C2BOOT

WP1 : Wakeup pin WKUP1 polarity
bits : 0 - 0 (1 bit)

WP2 : Wakeup pin WKUP2 polarity
bits : 1 - 1 (1 bit)

WP3 : Wakeup pin WKUP3 polarity
bits : 2 - 2 (1 bit)

WP4 : Wakeup pin WKUP4 polarity
bits : 3 - 3 (1 bit)

WP5 : Wakeup pin WKUP5 polarity
bits : 4 - 4 (1 bit)

VBE : VBAT battery charging enable
bits : 8 - 8 (1 bit)

VBRS : VBAT battery charging resistor selection
bits : 9 - 9 (1 bit)

C2BOOT : BOOT CPU2 after reset or wakeup from Stop or Standby modes
bits : 15 - 15 (1 bit)



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