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SYSCFG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

Registers

MEMRMP

EXTICR3

IMR1

IMR2

C2IMR1

C2IMR2

SIPCR

EXTICR4

SCSR

CFGR2

SWPR

SKR

SWPR2

CFGR1

EXTICR1

EXTICR2


MEMRMP

memory remap register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMRMP MEMRMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEM_MODE

MEM_MODE : Memory mapping selection
bits : 0 - 2 (3 bit)


EXTICR3

external interrupt configuration register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR3 EXTICR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI8 EXTI9 EXTI10 EXTI11

EXTI8 : EXTI 8 configuration bits
bits : 0 - 2 (3 bit)

EXTI9 : EXTI 9 configuration bits
bits : 4 - 6 (3 bit)

EXTI10 : EXTI 10 configuration bits
bits : 8 - 10 (3 bit)

EXTI11 : EXTI 11 configuration bits
bits : 12 - 14 (3 bit)


IMR1

CPU1 interrupt mask register 1
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMR1 IMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1IM TIM16IM TIM17IM EXIT5IM EXIT6IM EXIT7IM EXIT8IM EXIT9IM EXIT10IM EXIT11IM EXIT12IM EXIT13IM EXIT14IM EXIT15IM

TIM1IM : Peripheral TIM1 interrupt mask to CPU1
bits : 13 - 13 (1 bit)

TIM16IM : Peripheral TIM16 interrupt mask to CPU1
bits : 14 - 14 (1 bit)

TIM17IM : Peripheral TIM17 interrupt mask to CPU1
bits : 15 - 15 (1 bit)

EXIT5IM : Peripheral EXIT5 interrupt mask to CPU1
bits : 21 - 21 (1 bit)

EXIT6IM : Peripheral EXIT6 interrupt mask to CPU1
bits : 22 - 22 (1 bit)

EXIT7IM : Peripheral EXIT7 interrupt mask to CPU1
bits : 23 - 23 (1 bit)

EXIT8IM : Peripheral EXIT8 interrupt mask to CPU1
bits : 24 - 24 (1 bit)

EXIT9IM : Peripheral EXIT9 interrupt mask to CPU1
bits : 25 - 25 (1 bit)

EXIT10IM : Peripheral EXIT10 interrupt mask to CPU1
bits : 26 - 26 (1 bit)

EXIT11IM : Peripheral EXIT11 interrupt mask to CPU1
bits : 27 - 27 (1 bit)

EXIT12IM : Peripheral EXIT12 interrupt mask to CPU1
bits : 28 - 28 (1 bit)

EXIT13IM : Peripheral EXIT13 interrupt mask to CPU1
bits : 29 - 29 (1 bit)

EXIT14IM : Peripheral EXIT14 interrupt mask to CPU1
bits : 30 - 30 (1 bit)

EXIT15IM : Peripheral EXIT15 interrupt mask to CPU1
bits : 31 - 31 (1 bit)


IMR2

CPU1 interrupt mask register 2
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMR2 IMR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PVM1IM PVM3IM PVDIM

PVM1IM : Peripheral PVM1 interrupt mask to CPU1
bits : 16 - 16 (1 bit)

PVM3IM : Peripheral PVM3 interrupt mask to CPU1
bits : 18 - 18 (1 bit)

PVDIM : Peripheral PVD interrupt mask to CPU1
bits : 20 - 20 (1 bit)


C2IMR1

CPU2 interrupt mask register 1
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2IMR1 C2IMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTCSTAMP RTCWKUP RTCALARM RCC FLASH PKA RNG AES1 COMP ADC

RTCSTAMP : Peripheral RTCSTAMP interrupt mask to CPU2
bits : 0 - 0 (1 bit)

RTCWKUP : Peripheral RTCWKUP interrupt mask to CPU2
bits : 3 - 3 (1 bit)

RTCALARM : Peripheral RTCALARM interrupt mask to CPU2
bits : 4 - 4 (1 bit)

RCC : Peripheral RCC interrupt mask to CPU2
bits : 5 - 5 (1 bit)

FLASH : Peripheral FLASH interrupt mask to CPU2
bits : 6 - 6 (1 bit)

PKA : Peripheral PKA interrupt mask to CPU2
bits : 8 - 8 (1 bit)

RNG : Peripheral RNG interrupt mask to CPU2
bits : 9 - 9 (1 bit)

AES1 : Peripheral AES1 interrupt mask to CPU2
bits : 10 - 10 (1 bit)

COMP : Peripheral COMP interrupt mask to CPU2
bits : 11 - 11 (1 bit)

ADC : Peripheral ADC interrupt mask to CPU2
bits : 12 - 12 (1 bit)


C2IMR2

CPU2 interrupt mask register 1
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2IMR2 C2IMR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1_CH1_IM DMA1_CH2_IM DMA1_CH3_IM DMA1_CH4_IM DMA1_CH5_IM DMA1_CH6_IM DMA1_CH7_IM DMA2_CH1_IM DMA2_CH2_IM DMA2_CH3_IM DMA2_CH4_IM DMA2_CH5_IM DMA2_CH6_IM DMA2_CH7_IM DMAM_UX1_IM PVM1IM PVM3IM PVDIM TSCIM LCDIM

DMA1_CH1_IM : Peripheral DMA1 CH1 interrupt mask to CPU2
bits : 0 - 0 (1 bit)

DMA1_CH2_IM : Peripheral DMA1 CH2 interrupt mask to CPU2
bits : 1 - 1 (1 bit)

DMA1_CH3_IM : Peripheral DMA1 CH3 interrupt mask to CPU2
bits : 2 - 2 (1 bit)

DMA1_CH4_IM : Peripheral DMA1 CH4 interrupt mask to CPU2
bits : 3 - 3 (1 bit)

DMA1_CH5_IM : Peripheral DMA1 CH5 interrupt mask to CPU2
bits : 4 - 4 (1 bit)

DMA1_CH6_IM : Peripheral DMA1 CH6 interrupt mask to CPU2
bits : 5 - 5 (1 bit)

DMA1_CH7_IM : Peripheral DMA1 CH7 interrupt mask to CPU2
bits : 6 - 6 (1 bit)

DMA2_CH1_IM : Peripheral DMA2 CH1 interrupt mask to CPU1
bits : 8 - 8 (1 bit)

DMA2_CH2_IM : Peripheral DMA2 CH2 interrupt mask to CPU1
bits : 9 - 9 (1 bit)

DMA2_CH3_IM : Peripheral DMA2 CH3 interrupt mask to CPU1
bits : 10 - 10 (1 bit)

DMA2_CH4_IM : Peripheral DMA2 CH4 interrupt mask to CPU1
bits : 11 - 11 (1 bit)

DMA2_CH5_IM : Peripheral DMA2 CH5 interrupt mask to CPU1
bits : 12 - 12 (1 bit)

DMA2_CH6_IM : Peripheral DMA2 CH6 interrupt mask to CPU1
bits : 13 - 13 (1 bit)

DMA2_CH7_IM : Peripheral DMA2 CH7 interrupt mask to CPU1
bits : 14 - 14 (1 bit)

DMAM_UX1_IM : Peripheral DMAM UX1 interrupt mask to CPU1
bits : 15 - 15 (1 bit)

PVM1IM : Peripheral PVM1IM interrupt mask to CPU1
bits : 16 - 16 (1 bit)

PVM3IM : Peripheral PVM3IM interrupt mask to CPU1
bits : 18 - 18 (1 bit)

PVDIM : Peripheral PVDIM interrupt mask to CPU1
bits : 20 - 20 (1 bit)

TSCIM : Peripheral TSCIM interrupt mask to CPU1
bits : 21 - 21 (1 bit)

LCDIM : Peripheral LCDIM interrupt mask to CPU1
bits : 22 - 22 (1 bit)


SIPCR

secure IP control register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIPCR SIPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAES1 SAES2 SPKA SRNG

SAES1 : Enable AES1 KEY[7:0] security.
bits : 0 - 0 (1 bit)

SAES2 : Enable AES2 security.
bits : 1 - 1 (1 bit)

SPKA : Enable PKA security
bits : 2 - 2 (1 bit)

SRNG : Enable True RNG security
bits : 3 - 3 (1 bit)


EXTICR4

external interrupt configuration register 4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR4 EXTICR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI12 EXTI13 EXTI14 EXTI15

EXTI12 : EXTI12 configuration bits
bits : 0 - 2 (3 bit)

EXTI13 : EXTI13 configuration bits
bits : 4 - 6 (3 bit)

EXTI14 : EXTI14 configuration bits
bits : 8 - 10 (3 bit)

EXTI15 : EXTI15 configuration bits
bits : 12 - 14 (3 bit)


SCSR

SCSR
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCSR SCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRAM2ER SRAM2BSY C2RFD

SRAM2ER : SRAM2 Erase
bits : 0 - 0 (1 bit)
access : read-write

SRAM2BSY : SRAM2 busy by erase operation
bits : 1 - 1 (1 bit)
access : read-only

C2RFD : CPU2 SRAM fetch (execution) disable.
bits : 31 - 31 (1 bit)
access : read-write


CFGR2

CFGR2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR2 CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLL SPL PVDL ECCL SPF

CLL : Cortex-M4 LOCKUP (Hardfault) output enable bit
bits : 0 - 0 (1 bit)
access : write-only

SPL : SRAM2 parity lock bit
bits : 1 - 1 (1 bit)
access : write-only

PVDL : PVD lock enable bit
bits : 2 - 2 (1 bit)
access : write-only

ECCL : ECC Lock
bits : 3 - 3 (1 bit)
access : write-only

SPF : SRAM2 parity error flag
bits : 8 - 8 (1 bit)
access : read-write


SWPR

SRAM2 write protection register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWPR SWPR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0WP P1WP P2WP P3WP P4WP P5WP P6WP P7WP P8WP P9WP P10WP P11WP P12WP P13WP P14WP P15WP P16WP P17WP P18WP P19WP P20WP P21WP P22WP P23WP P24WP P25WP P26WP P27WP P28WP P29WP P30WP P31WP

P0WP : P0WP
bits : 0 - 0 (1 bit)

P1WP : P1WP
bits : 1 - 1 (1 bit)

P2WP : P2WP
bits : 2 - 2 (1 bit)

P3WP : P3WP
bits : 3 - 3 (1 bit)

P4WP : P4WP
bits : 4 - 4 (1 bit)

P5WP : P5WP
bits : 5 - 5 (1 bit)

P6WP : P6WP
bits : 6 - 6 (1 bit)

P7WP : P7WP
bits : 7 - 7 (1 bit)

P8WP : P8WP
bits : 8 - 8 (1 bit)

P9WP : P9WP
bits : 9 - 9 (1 bit)

P10WP : P10WP
bits : 10 - 10 (1 bit)

P11WP : P11WP
bits : 11 - 11 (1 bit)

P12WP : P12WP
bits : 12 - 12 (1 bit)

P13WP : P13WP
bits : 13 - 13 (1 bit)

P14WP : P14WP
bits : 14 - 14 (1 bit)

P15WP : P15WP
bits : 15 - 15 (1 bit)

P16WP : P16WP
bits : 16 - 16 (1 bit)

P17WP : P17WP
bits : 17 - 17 (1 bit)

P18WP : P18WP
bits : 18 - 18 (1 bit)

P19WP : P19WP
bits : 19 - 19 (1 bit)

P20WP : P20WP
bits : 20 - 20 (1 bit)

P21WP : P21WP
bits : 21 - 21 (1 bit)

P22WP : P22WP
bits : 22 - 22 (1 bit)

P23WP : P23WP
bits : 23 - 23 (1 bit)

P24WP : P24WP
bits : 24 - 24 (1 bit)

P25WP : P25WP
bits : 25 - 25 (1 bit)

P26WP : P26WP
bits : 26 - 26 (1 bit)

P27WP : P27WP
bits : 27 - 27 (1 bit)

P28WP : P28WP
bits : 28 - 28 (1 bit)

P29WP : P29WP
bits : 29 - 29 (1 bit)

P30WP : P30WP
bits : 30 - 30 (1 bit)

P31WP : SRAM2 page 31 write protection
bits : 31 - 31 (1 bit)


SKR

SKR
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SKR SKR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : SRAM2 write protection key for software erase
bits : 0 - 7 (8 bit)


SWPR2

SRAM2 write protection register 2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWPR2 SWPR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P32WP P33WP P34WP P35WP P36WP P37WP P38WP P39WP P40WP P41WP P42WP P43WP P44WP P45WP P46WP P47WP P48WP P49WP P50WP P51WP P52WP P53WP P54WP P55WP P56WP P57WP P58WP P59WP P60WP P61WP P62WP P63WP

P32WP : P32WP
bits : 0 - 0 (1 bit)

P33WP : P33WP
bits : 1 - 1 (1 bit)

P34WP : P34WP
bits : 2 - 2 (1 bit)

P35WP : P35WP
bits : 3 - 3 (1 bit)

P36WP : P36WP
bits : 4 - 4 (1 bit)

P37WP : P37WP
bits : 5 - 5 (1 bit)

P38WP : P38WP
bits : 6 - 6 (1 bit)

P39WP : P39WP
bits : 7 - 7 (1 bit)

P40WP : P40WP
bits : 8 - 8 (1 bit)

P41WP : P41WP
bits : 9 - 9 (1 bit)

P42WP : P42WP
bits : 10 - 10 (1 bit)

P43WP : P43WP
bits : 11 - 11 (1 bit)

P44WP : P44WP
bits : 12 - 12 (1 bit)

P45WP : P45WP
bits : 13 - 13 (1 bit)

P46WP : P46WP
bits : 14 - 14 (1 bit)

P47WP : P47WP
bits : 15 - 15 (1 bit)

P48WP : P48WP
bits : 16 - 16 (1 bit)

P49WP : P49WP
bits : 17 - 17 (1 bit)

P50WP : P50WP
bits : 18 - 18 (1 bit)

P51WP : P51WP
bits : 19 - 19 (1 bit)

P52WP : P52WP
bits : 20 - 20 (1 bit)

P53WP : P53WP
bits : 21 - 21 (1 bit)

P54WP : P54WP
bits : 22 - 22 (1 bit)

P55WP : P55WP
bits : 23 - 23 (1 bit)

P56WP : P56WP
bits : 24 - 24 (1 bit)

P57WP : P57WP
bits : 25 - 25 (1 bit)

P58WP : P58WP
bits : 26 - 26 (1 bit)

P59WP : P59WP
bits : 27 - 27 (1 bit)

P60WP : P60WP
bits : 28 - 28 (1 bit)

P61WP : P61WP
bits : 29 - 29 (1 bit)

P62WP : P62WP
bits : 30 - 30 (1 bit)

P63WP : SRAM2 page 63 write protection
bits : 31 - 31 (1 bit)


CFGR1

configuration register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR1 CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOOSTEN I2C_PB6_FMP I2C_PB7_FMP I2C_PB8_FMP I2C_PB9_FMP I2C1_FMP I2C3_FMP FPU_IE

BOOSTEN : I/O analog switch voltage booster enable
bits : 8 - 8 (1 bit)

I2C_PB6_FMP : Fast-mode Plus (Fm+) driving capability activation on PB6
bits : 16 - 16 (1 bit)

I2C_PB7_FMP : Fast-mode Plus (Fm+) driving capability activation on PB7
bits : 17 - 17 (1 bit)

I2C_PB8_FMP : Fast-mode Plus (Fm+) driving capability activation on PB8
bits : 18 - 18 (1 bit)

I2C_PB9_FMP : Fast-mode Plus (Fm+) driving capability activation on PB9
bits : 19 - 19 (1 bit)

I2C1_FMP : I2C1 Fast-mode Plus driving capability activation
bits : 20 - 20 (1 bit)

I2C3_FMP : I2C3 Fast-mode Plus driving capability activation
bits : 22 - 22 (1 bit)

FPU_IE : Floating Point Unit interrupts enable bits
bits : 26 - 31 (6 bit)


EXTICR1

external interrupt configuration register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR1 EXTICR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0 EXTI1 EXTI2 EXTI3

EXTI0 : EXTI 0 configuration bits
bits : 0 - 2 (3 bit)

EXTI1 : EXTI 1 configuration bits
bits : 4 - 6 (3 bit)

EXTI2 : EXTI 2 configuration bits
bits : 8 - 10 (3 bit)

EXTI3 : EXTI 3 configuration bits
bits : 12 - 14 (3 bit)


EXTICR2

external interrupt configuration register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR2 EXTICR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI4 EXTI5 EXTI6 EXTI7

EXTI4 : EXTI 4 configuration bits
bits : 0 - 2 (3 bit)

EXTI5 : EXTI 5 configuration bits
bits : 4 - 6 (3 bit)

EXTI6 : EXTI 6 configuration bits
bits : 8 - 10 (3 bit)

EXTI7 : EXTI 7 configuration bits
bits : 12 - 14 (3 bit)



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