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Flash

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x90 byte (0x0)
mem_usage : registers
protection :

Registers

ACR

SR

CR

ECCR

OPTR

PCROP1ASR

PCROP1AER

WRP1AR

WRP1BR

PCROP1BSR

PCROP1BER

IPCCBR

C2ACR

C2SR

C2CR

KEYR

SFR

SRRVR

OPTKEYR


ACR

Access control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACR ACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LATENCY PRFTEN ICEN DCEN ICRST DCRST PES EMPTY

LATENCY : Latency
bits : 0 - 2 (3 bit)

PRFTEN : Prefetch enable
bits : 8 - 8 (1 bit)

ICEN : Instruction cache enable
bits : 9 - 9 (1 bit)

DCEN : Data cache enable
bits : 10 - 10 (1 bit)

ICRST : Instruction cache reset
bits : 11 - 11 (1 bit)

DCRST : Data cache reset
bits : 12 - 12 (1 bit)

PES : CPU1 CortexM4 program erase suspend request
bits : 15 - 15 (1 bit)

EMPTY : Flash User area empty
bits : 16 - 16 (1 bit)


SR

Status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOP OPERR PROGERR WRPERR PGAERR SIZERR PGSERR MISERR FASTERR OPTNV RDERR OPTVERR BSY CFGBSY PESD

EOP : End of operation
bits : 0 - 0 (1 bit)
access : read-write

OPERR : Operation error
bits : 1 - 1 (1 bit)
access : read-write

PROGERR : Programming error
bits : 3 - 3 (1 bit)
access : read-write

WRPERR : Write protected error
bits : 4 - 4 (1 bit)
access : read-write

PGAERR : Programming alignment error
bits : 5 - 5 (1 bit)
access : read-write

SIZERR : Size error
bits : 6 - 6 (1 bit)
access : read-write

PGSERR : Programming sequence error
bits : 7 - 7 (1 bit)
access : read-write

MISERR : Fast programming data miss error
bits : 8 - 8 (1 bit)
access : read-write

FASTERR : Fast programming error
bits : 9 - 9 (1 bit)
access : read-write

OPTNV : User Option OPTVAL indication
bits : 13 - 13 (1 bit)
access : read-only

RDERR : PCROP read error
bits : 14 - 14 (1 bit)
access : read-write

OPTVERR : Option validity error
bits : 15 - 15 (1 bit)
access : read-write

BSY : Busy
bits : 16 - 16 (1 bit)
access : read-only

CFGBSY : Programming or erase configuration busy
bits : 18 - 18 (1 bit)
access : read-only

PESD : Programming or erase operation suspended
bits : 19 - 19 (1 bit)
access : read-only


CR

Flash control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PG PER MER PNB STRT OPTSTRT FSTPG EOPIE ERRIE RDERRIE OBL_LAUNCH OPTLOCK LOCK

PG : Programming
bits : 0 - 0 (1 bit)

PER : Page erase
bits : 1 - 1 (1 bit)

MER : This bit triggers the mass erase (all user pages) when set
bits : 2 - 2 (1 bit)

PNB : Page number selection
bits : 3 - 10 (8 bit)

STRT : Start
bits : 16 - 16 (1 bit)

OPTSTRT : Options modification start
bits : 17 - 17 (1 bit)

FSTPG : Fast programming
bits : 18 - 18 (1 bit)

EOPIE : End of operation interrupt enable
bits : 24 - 24 (1 bit)

ERRIE : Error interrupt enable
bits : 25 - 25 (1 bit)

RDERRIE : PCROP read error interrupt enable
bits : 26 - 26 (1 bit)

OBL_LAUNCH : Force the option byte loading
bits : 27 - 27 (1 bit)

OPTLOCK : Options Lock
bits : 30 - 30 (1 bit)

LOCK : FLASH_CR Lock
bits : 31 - 31 (1 bit)


ECCR

Flash ECC register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECCR ECCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR_ECC SYSF_ECC ECCCIE CPUID ECCC ECCD

ADDR_ECC : ECC fail address
bits : 0 - 16 (17 bit)
access : read-only

SYSF_ECC : System Flash ECC fail
bits : 20 - 20 (1 bit)
access : read-only

ECCCIE : ECC correction interrupt enable
bits : 24 - 24 (1 bit)
access : read-write

CPUID : CPU identification
bits : 26 - 28 (3 bit)
access : read-only

ECCC : ECC correction
bits : 30 - 30 (1 bit)
access : read-write

ECCD : ECC detection
bits : 31 - 31 (1 bit)
access : read-write


OPTR

Flash option register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPTR OPTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDP ESE BOR_LEV nRST_STOP nRST_STDBY nRST_SHDW IDWG_SW IWDG_STOP IWDG_STDBY WWDG_SW nBOOT1 SRAM2_PE SRAM2_RST nSWBOOT0 nBOOT0 AGC_TRIM

RDP : Read protection level
bits : 0 - 7 (8 bit)

ESE : Security enabled
bits : 8 - 8 (1 bit)

BOR_LEV : BOR reset Level
bits : 9 - 11 (3 bit)

nRST_STOP : nRST_STOP
bits : 12 - 12 (1 bit)

nRST_STDBY : nRST_STDBY
bits : 13 - 13 (1 bit)

nRST_SHDW : nRST_SHDW
bits : 14 - 14 (1 bit)

IDWG_SW : Independent watchdog selection
bits : 16 - 16 (1 bit)

IWDG_STOP : Independent watchdog counter freeze in Stop mode
bits : 17 - 17 (1 bit)

IWDG_STDBY : Independent watchdog counter freeze in Standby mode
bits : 18 - 18 (1 bit)

WWDG_SW : Window watchdog selection
bits : 19 - 19 (1 bit)

nBOOT1 : Boot configuration
bits : 23 - 23 (1 bit)

SRAM2_PE : SRAM2 parity check enable
bits : 24 - 24 (1 bit)

SRAM2_RST : SRAM2 Erase when system reset
bits : 25 - 25 (1 bit)

nSWBOOT0 : Software Boot0
bits : 26 - 26 (1 bit)

nBOOT0 : nBoot0 option bit
bits : 27 - 27 (1 bit)

AGC_TRIM : Radio Automatic Gain Control Trimming
bits : 29 - 31 (3 bit)


PCROP1ASR

Flash Bank 1 PCROP Start address zone A register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCROP1ASR PCROP1ASR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCROP1A_STRT

PCROP1A_STRT : Bank 1 PCROPQ area start offset
bits : 0 - 8 (9 bit)


PCROP1AER

Flash Bank 1 PCROP End address zone A register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCROP1AER PCROP1AER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCROP1A_END PCROP_RDP

PCROP1A_END : Bank 1 PCROP area end offset
bits : 0 - 8 (9 bit)

PCROP_RDP : PCROP area preserved when RDP level decreased
bits : 31 - 31 (1 bit)


WRP1AR

Flash Bank 1 WRP area A address register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRP1AR WRP1AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRP1A_STRT WRP1A_END

WRP1A_STRT : Bank 1 WRP first area A start offset
bits : 0 - 7 (8 bit)

WRP1A_END : Bank 1 WRP first area A end offset
bits : 16 - 23 (8 bit)


WRP1BR

Flash Bank 1 WRP area B address register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRP1BR WRP1BR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRP1B_END WRP1B_STRT

WRP1B_END : Bank 1 WRP second area B start offset
bits : 0 - 7 (8 bit)

WRP1B_STRT : Bank 1 WRP second area B end offset
bits : 16 - 23 (8 bit)


PCROP1BSR

Flash Bank 1 PCROP Start address area B register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCROP1BSR PCROP1BSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCROP1B_STRT

PCROP1B_STRT : Bank 1 PCROP area B start offset
bits : 0 - 8 (9 bit)


PCROP1BER

Flash Bank 1 PCROP End address area B register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCROP1BER PCROP1BER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCROP1B_END

PCROP1B_END : Bank 1 PCROP area end area B offset
bits : 0 - 8 (9 bit)


IPCCBR

IPCC mailbox data buffer address register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPCCBR IPCCBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPCCDBA

IPCCDBA : PCC mailbox data buffer base address
bits : 0 - 13 (14 bit)


C2ACR

CPU2 cortex M0 access control register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2ACR C2ACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRFTEN ICEN ICRST PES

PRFTEN : CPU2 cortex M0 prefetch enable
bits : 8 - 8 (1 bit)

ICEN : CPU2 cortex M0 instruction cache enable
bits : 9 - 9 (1 bit)

ICRST : CPU2 cortex M0 instruction cache reset
bits : 11 - 11 (1 bit)

PES : CPU2 cortex M0 program erase suspend request
bits : 15 - 15 (1 bit)


C2SR

CPU2 cortex M0 status register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2SR C2SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOP OPERR PROGERR WRPERR PGAERR SIZERR PGSERR MISSERR FASTERR RDERR BSY CFGBSY PESD

EOP : End of operation
bits : 0 - 0 (1 bit)

OPERR : Operation error
bits : 1 - 1 (1 bit)

PROGERR : Programming error
bits : 3 - 3 (1 bit)

WRPERR : write protection error
bits : 4 - 4 (1 bit)

PGAERR : Programming alignment error
bits : 5 - 5 (1 bit)

SIZERR : Size error
bits : 6 - 6 (1 bit)

PGSERR : Programming sequence error
bits : 7 - 7 (1 bit)

MISSERR : Fast programming data miss error
bits : 8 - 8 (1 bit)

FASTERR : Fast programming error
bits : 9 - 9 (1 bit)

RDERR : PCROP read error
bits : 14 - 14 (1 bit)

BSY : Busy
bits : 16 - 16 (1 bit)

CFGBSY : Programming or erase configuration busy
bits : 18 - 18 (1 bit)

PESD : Programming or erase operation suspended
bits : 19 - 19 (1 bit)


C2CR

CPU2 cortex M0 control register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2CR C2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PG PER MER PNB STRT FSTPG EOPIE ERRIE RDERRIE

PG : Programming
bits : 0 - 0 (1 bit)

PER : Page erase
bits : 1 - 1 (1 bit)

MER : Masse erase
bits : 2 - 2 (1 bit)

PNB : Page Number selection
bits : 3 - 10 (8 bit)

STRT : Start
bits : 16 - 16 (1 bit)

FSTPG : Fast programming
bits : 18 - 18 (1 bit)

EOPIE : End of operation interrupt enable
bits : 24 - 24 (1 bit)

ERRIE : Error interrupt enable
bits : 25 - 25 (1 bit)

RDERRIE : PCROP read error interrupt enable
bits : 26 - 26 (1 bit)


KEYR

Flash key register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYR KEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYR

KEYR : KEYR
bits : 0 - 31 (32 bit)


SFR

Secure flash start address register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFR SFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFSA FSD DDS

SFSA : Secure flash start address
bits : 0 - 7 (8 bit)

FSD : Flash security disable
bits : 8 - 8 (1 bit)

DDS : Disable Cortex M0 debug access
bits : 12 - 12 (1 bit)


SRRVR

Secure SRAM2 start address and cortex M0 reset vector register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRRVR SRRVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBRV SBRSA BRSD SNBRSA NBRSD C2OPT

SBRV : cortex M0 access control register
bits : 0 - 17 (18 bit)

SBRSA : Secure backup SRAM2a start address
bits : 18 - 22 (5 bit)

BRSD : backup SRAM2a security disable
bits : 23 - 23 (1 bit)

SNBRSA : Secure non backup SRAM2a start address
bits : 25 - 29 (5 bit)

NBRSD : non-backup SRAM2b security disable
bits : 30 - 30 (1 bit)

C2OPT : CPU2 cortex M0 boot reset vector memory selection
bits : 31 - 31 (1 bit)


OPTKEYR

Option byte key register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OPTKEYR OPTKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPTKEYR

OPTKEYR : Option byte key
bits : 0 - 31 (32 bit)



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