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RCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CR

PLLSAI1CFGR

EXTCFGR

C2AHB1ENR

C2AHB2ENR

C2AHB3ENR

C2APB1ENR1

C2APB1ENR2

C2APB2ENR

C2APB3ENR

C2AHB1SMENR

C2AHB2SMENR

C2AHB3SMENR

C2APB1SMENR1

C2APB1SMENR2

CIER

C2APB2SMENR

C2APB3SMENR

CIFR

CICR

SMPSCR

AHB1RSTR

AHB2RSTR

AHB3RSTR

APB1RSTR1

APB1RSTR2

ICSCR

APB2RSTR

APB3RSTR

AHB1ENR

AHB2ENR

AHB3ENR

APB1ENR1

APB1ENR2

APB2ENR

AHB1SMENR

AHB2SMENR

AHB3SMENR

APB1SMENR1

APB1SMENR2

CFGR

APB2SMENR

CCIPR

BDCR

CSR

CRRCR

HSECR

PLLCFGR


CR

Clock control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSION MSIRDY MSIPLLEN MSIRANGE HSION HSIKERON HSIRDY HSIASFS HSIKERDY HSEON HSERDY HSEBYP CSSON HSEPRE PLLON PLLRDY PLLSAI1ON PLLSAI1RDY

MSION : MSI clock enable
bits : 0 - 0 (1 bit)
access : read-write

MSIRDY : MSI clock ready flag
bits : 1 - 1 (1 bit)
access : read-only

MSIPLLEN : MSI clock PLL enable
bits : 2 - 2 (1 bit)
access : read-write

MSIRANGE : MSI clock ranges
bits : 4 - 7 (4 bit)
access : read-write

HSION : HSI clock enabled
bits : 8 - 8 (1 bit)
access : read-write

HSIKERON : HSI always enable for peripheral kernels
bits : 9 - 9 (1 bit)
access : read-write

HSIRDY : HSI clock ready flag
bits : 10 - 10 (1 bit)
access : read-only

HSIASFS : HSI automatic start from Stop
bits : 11 - 11 (1 bit)
access : read-write

HSIKERDY : HSI kernel clock ready flag for peripherals requests
bits : 12 - 12 (1 bit)
access : read-only

HSEON : HSE clock enabled
bits : 16 - 16 (1 bit)
access : read-write

HSERDY : HSE clock ready flag
bits : 17 - 17 (1 bit)
access : read-only

HSEBYP : HSE crystal oscillator bypass
bits : 18 - 18 (1 bit)
access : read-write

CSSON : HSE Clock security system enable
bits : 19 - 19 (1 bit)
access : write-only

HSEPRE : HSE sysclk and PLL M divider prescaler
bits : 20 - 20 (1 bit)
access : read-write

PLLON : Main PLL enable
bits : 24 - 24 (1 bit)
access : read-write

PLLRDY : Main PLL clock ready flag
bits : 25 - 25 (1 bit)
access : read-only

PLLSAI1ON : SAI1 PLL enable
bits : 26 - 26 (1 bit)
access : read-write

PLLSAI1RDY : SAI1 PLL clock ready flag
bits : 27 - 27 (1 bit)
access : read-only


PLLSAI1CFGR

PLLSAI1 configuration register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLSAI1CFGR PLLSAI1CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLN PLLPEN PLLP PLLQEN PLLQ PLLREN PLLR

PLLN : SAIPLL multiplication factor for VCO
bits : 8 - 14 (7 bit)

PLLPEN : SAIPLL PLLSAI1CLK output enable
bits : 16 - 16 (1 bit)

PLLP : SAI1PLL division factor P for PLLSAICLK (SAI1clock)
bits : 17 - 21 (5 bit)

PLLQEN : SAIPLL PLLSAIUSBCLK output enable
bits : 24 - 24 (1 bit)

PLLQ : SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock)
bits : 25 - 27 (3 bit)

PLLREN : PLLSAI PLLADC1CLK output enable
bits : 28 - 28 (1 bit)

PLLR : PLLSAI division factor R for PLLADC1CLK (ADC clock)
bits : 29 - 31 (3 bit)


EXTCFGR

Extended clock recovery register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTCFGR EXTCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHDHPRE C2HPRE SHDHPREF C2HPREF RFCSS

SHDHPRE : Shared AHB prescaler
bits : 0 - 3 (4 bit)
access : read-write

C2HPRE : CPU2 AHB prescaler
bits : 4 - 7 (4 bit)
access : read-write

SHDHPREF : Shared AHB prescaler flag
bits : 16 - 16 (1 bit)
access : read-only

C2HPREF : CPU2 AHB prescaler flag
bits : 17 - 17 (1 bit)
access : read-only

RFCSS : RF clock source selected
bits : 20 - 20 (1 bit)
access : read-only


C2AHB1ENR

CPU2 AHB1 peripheral clock enable register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2AHB1ENR C2AHB1ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1EN DMA2EN DMAMUXEN SRAM1EN CRCEN TSCEN

DMA1EN : CPU2 DMA1 clock enable
bits : 0 - 0 (1 bit)

DMA2EN : CPU2 DMA2 clock enable
bits : 1 - 1 (1 bit)

DMAMUXEN : CPU2 DMAMUX clock enable
bits : 2 - 2 (1 bit)

SRAM1EN : CPU2 SRAM1 clock enable
bits : 9 - 9 (1 bit)

CRCEN : CPU2 CRC clock enable
bits : 12 - 12 (1 bit)

TSCEN : CPU2 Touch Sensing Controller clock enable
bits : 16 - 16 (1 bit)


C2AHB2ENR

CPU2 AHB2 peripheral clock enable register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2AHB2ENR C2AHB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOAEN GPIOBEN GPIOCEN GPIODEN GPIOEEN GPIOHEN ADCEN AES1EN

GPIOAEN : CPU2 IO port A clock enable
bits : 0 - 0 (1 bit)

GPIOBEN : CPU2 IO port B clock enable
bits : 1 - 1 (1 bit)

GPIOCEN : CPU2 IO port C clock enable
bits : 2 - 2 (1 bit)

GPIODEN : CPU2 IO port D clock enable
bits : 3 - 3 (1 bit)

GPIOEEN : CPU2 IO port E clock enable
bits : 4 - 4 (1 bit)

GPIOHEN : CPU2 IO port H clock enable
bits : 7 - 7 (1 bit)

ADCEN : CPU2 ADC clock enable
bits : 13 - 13 (1 bit)

AES1EN : CPU2 AES1 accelerator clock enable
bits : 16 - 16 (1 bit)


C2AHB3ENR

CPU2 AHB3 peripheral clock enable register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2AHB3ENR C2AHB3ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKAEN AES2EN RNGEN HSEMEN IPCCEN FLASHEN

PKAEN : CPU2 PKAEN
bits : 16 - 16 (1 bit)

AES2EN : CPU2 AES2EN
bits : 17 - 17 (1 bit)

RNGEN : CPU2 RNGEN
bits : 18 - 18 (1 bit)

HSEMEN : CPU2 HSEMEN
bits : 19 - 19 (1 bit)

IPCCEN : CPU2 IPCCEN
bits : 20 - 20 (1 bit)

FLASHEN : CPU2 FLASHEN
bits : 25 - 25 (1 bit)


C2APB1ENR1

CPU2 APB1ENR1
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2APB1ENR1 C2APB1ENR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2EN LCDEN RTCAPBEN SPI2EN I2C1EN I2C3EN CRSEN USBEN LPTIM1EN

TIM2EN : CPU2 TIM2 timer clock enable
bits : 0 - 0 (1 bit)

LCDEN : CPU2 LCD clock enable
bits : 9 - 9 (1 bit)

RTCAPBEN : CPU2 RTC APB clock enable
bits : 10 - 10 (1 bit)

SPI2EN : CPU2 SPI2 clock enable
bits : 14 - 14 (1 bit)

I2C1EN : CPU2 I2C1 clock enable
bits : 21 - 21 (1 bit)

I2C3EN : CPU2 I2C3 clock enable
bits : 23 - 23 (1 bit)

CRSEN : CPU2 CRS clock enable
bits : 24 - 24 (1 bit)

USBEN : CPU2 USB clock enable
bits : 26 - 26 (1 bit)

LPTIM1EN : CPU2 Low power timer 1 clock enable
bits : 31 - 31 (1 bit)


C2APB1ENR2

CPU2 APB1 peripheral clock enable register 2
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2APB1ENR2 C2APB1ENR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPUART1EN LPTIM2EN

LPUART1EN : CPU2 Low power UART 1 clock enable
bits : 0 - 0 (1 bit)

LPTIM2EN : CPU2 LPTIM2EN
bits : 5 - 5 (1 bit)


C2APB2ENR

CPU2 APB2ENR
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2APB2ENR C2APB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1EN SPI1EN USART1EN TIM16EN TIM17EN SAI1EN

TIM1EN : CPU2 TIM1 timer clock enable
bits : 11 - 11 (1 bit)

SPI1EN : CPU2 SPI1 clock enable
bits : 12 - 12 (1 bit)

USART1EN : CPU2 USART1clock enable
bits : 14 - 14 (1 bit)

TIM16EN : CPU2 TIM16 timer clock enable
bits : 17 - 17 (1 bit)

TIM17EN : CPU2 TIM17 timer clock enable
bits : 18 - 18 (1 bit)

SAI1EN : CPU2 SAI1 clock enable
bits : 21 - 21 (1 bit)


C2APB3ENR

CPU2 APB3ENR
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2APB3ENR C2APB3ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEEN EN802

BLEEN : CPU2 BLE interface clock enable
bits : 0 - 0 (1 bit)

EN802 : CPU2 802.15.4 interface clock enable
bits : 1 - 1 (1 bit)


C2AHB1SMENR

CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2AHB1SMENR C2AHB1SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1SMEN DMA2SMEN DMAMUXSMEN SRAM1SMEN CRCSMEN TSCSMEN

DMA1SMEN : CPU2 DMA1 clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)

DMA2SMEN : CPU2 DMA2 clocks enable during Sleep and Stop modes
bits : 1 - 1 (1 bit)

DMAMUXSMEN : CPU2 DMAMUX clocks enable during Sleep and Stop modes
bits : 2 - 2 (1 bit)

SRAM1SMEN : SRAM1 interface clock enable during CPU1 CSleep mode
bits : 9 - 9 (1 bit)

CRCSMEN : CPU2 CRCSMEN
bits : 12 - 12 (1 bit)

TSCSMEN : CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes
bits : 16 - 16 (1 bit)


C2AHB2SMENR

CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2AHB2SMENR C2AHB2SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOASMEN GPIOBSMEN GPIOCSMEN GPIODSMEN GPIOESMEN GPIOHSMEN ADCFSSMEN AES1SMEN

GPIOASMEN : CPU2 IO port A clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)

GPIOBSMEN : CPU2 IO port B clocks enable during Sleep and Stop modes
bits : 1 - 1 (1 bit)

GPIOCSMEN : CPU2 IO port C clocks enable during Sleep and Stop modes
bits : 2 - 2 (1 bit)

GPIODSMEN : CPU2 IO port D clocks enable during Sleep and Stop modes
bits : 3 - 3 (1 bit)

GPIOESMEN : CPU2 IO port E clocks enable during Sleep and Stop modes
bits : 4 - 4 (1 bit)

GPIOHSMEN : CPU2 IO port H clocks enable during Sleep and Stop modes
bits : 7 - 7 (1 bit)

ADCFSSMEN : CPU2 ADC clocks enable during Sleep and Stop modes
bits : 13 - 13 (1 bit)

AES1SMEN : CPU2 AES1 accelerator clocks enable during Sleep and Stop modes
bits : 16 - 16 (1 bit)


C2AHB3SMENR

CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2AHB3SMENR C2AHB3SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKASMEN AES2SMEN RNGSMEN SRAM2SMEN FLASHSMEN

PKASMEN : PKA accelerator clocks enable during CPU2 sleep modes
bits : 16 - 16 (1 bit)

AES2SMEN : AES2 accelerator clocks enable during CPU2 sleep modes
bits : 17 - 17 (1 bit)

RNGSMEN : True RNG clocks enable during CPU2 sleep modes
bits : 18 - 18 (1 bit)

SRAM2SMEN : SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes
bits : 24 - 24 (1 bit)

FLASHSMEN : Flash interface clocks enable during CPU2 sleep modes
bits : 25 - 25 (1 bit)


C2APB1SMENR1

CPU2 APB1SMENR1
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2APB1SMENR1 C2APB1SMENR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2SMEN LCDSMEN RTCAPBSMEN SPI2SMEN I2C1SMEN I2C3SMEN CRSMEN USBSMEN LPTIM1SMEN

TIM2SMEN : TIM2 timer clocks enable during CPU2 Sleep mode
bits : 0 - 0 (1 bit)

LCDSMEN : LCD clocks enable during CPU2 Sleep mode
bits : 9 - 9 (1 bit)

RTCAPBSMEN : RTC APB clocks enable during CPU2 Sleep mode
bits : 10 - 10 (1 bit)

SPI2SMEN : SPI2 clocks enable during CPU2 Sleep mode
bits : 14 - 14 (1 bit)

I2C1SMEN : I2C1 clocks enable during CPU2 Sleep mode
bits : 21 - 21 (1 bit)

I2C3SMEN : I2C3 clocks enable during CPU2 Sleep mode
bits : 23 - 23 (1 bit)

CRSMEN : CRS clocks enable during CPU2 Sleep mode
bits : 24 - 24 (1 bit)

USBSMEN : USB FS clocks enable during CPU2 Sleep mode
bits : 26 - 26 (1 bit)

LPTIM1SMEN : Low power timer 1 clocks enable during CPU2 Sleep mode
bits : 31 - 31 (1 bit)


C2APB1SMENR2

CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2APB1SMENR2 C2APB1SMENR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPUART1SMEN LPTIM2SMEN

LPUART1SMEN : Low power UART 1 clocks enable during CPU2 Sleep mode
bits : 0 - 0 (1 bit)

LPTIM2SMEN : Low power timer 2 clocks enable during CPU2 Sleep mode
bits : 5 - 5 (1 bit)


CIER

Clock interrupt enable register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIER CIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSI1RDYIE LSERDYIE MSIRDYIE HSIRDYIE HSERDYIE PLLRDYIE PLLSAI1RDYIE LSECSSIE HSI48RDYIE LSI2RDYIE

LSI1RDYIE : LSI1 ready interrupt enable
bits : 0 - 0 (1 bit)

LSERDYIE : LSE ready interrupt enable
bits : 1 - 1 (1 bit)

MSIRDYIE : MSI ready interrupt enable
bits : 2 - 2 (1 bit)

HSIRDYIE : HSI ready interrupt enable
bits : 3 - 3 (1 bit)

HSERDYIE : HSE ready interrupt enable
bits : 4 - 4 (1 bit)

PLLRDYIE : PLLSYS ready interrupt enable
bits : 5 - 5 (1 bit)

PLLSAI1RDYIE : PLLSAI1 ready interrupt enable
bits : 6 - 6 (1 bit)

LSECSSIE : LSE clock security system interrupt enable
bits : 9 - 9 (1 bit)

HSI48RDYIE : HSI48 ready interrupt enable
bits : 10 - 10 (1 bit)

LSI2RDYIE : LSI2 ready interrupt enable
bits : 11 - 11 (1 bit)


C2APB2SMENR

CPU2 APB2SMENR
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2APB2SMENR C2APB2SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1SMEN SPI1SMEN USART1SMEN TIM16SMEN TIM17SMEN SAI1SMEN

TIM1SMEN : TIM1 timer clocks enable during CPU2 Sleep mode
bits : 11 - 11 (1 bit)

SPI1SMEN : SPI1 clocks enable during CPU2 Sleep mode
bits : 12 - 12 (1 bit)

USART1SMEN : USART1clocks enable during CPU2 Sleep mode
bits : 14 - 14 (1 bit)

TIM16SMEN : TIM16 timer clocks enable during CPU2 Sleep mode
bits : 17 - 17 (1 bit)

TIM17SMEN : TIM17 timer clocks enable during CPU2 Sleep mode
bits : 18 - 18 (1 bit)

SAI1SMEN : SAI1 clocks enable during CPU2 Sleep mode
bits : 21 - 21 (1 bit)


C2APB3SMENR

CPU2 APB3SMENR
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2APB3SMENR C2APB3SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLESMEN SMEN802

BLESMEN : BLE interface clocks enable during CPU2 Sleep mode
bits : 0 - 0 (1 bit)

SMEN802 : 802.15.4 interface clocks enable during CPU2 Sleep modes
bits : 1 - 1 (1 bit)


CIFR

Clock interrupt flag register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIFR CIFR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSI1RDYF LSERDYF MSIRDYF HSIRDYF HSERDYF PLLRDYF PLLSAI1RDYF HSECSSF LSECSSF HSI48RDYF LSI2RDYF

LSI1RDYF : LSI1 ready interrupt flag
bits : 0 - 0 (1 bit)

LSERDYF : LSE ready interrupt flag
bits : 1 - 1 (1 bit)

MSIRDYF : MSI ready interrupt flag
bits : 2 - 2 (1 bit)

HSIRDYF : HSI ready interrupt flag
bits : 3 - 3 (1 bit)

HSERDYF : HSE ready interrupt flag
bits : 4 - 4 (1 bit)

PLLRDYF : PLL ready interrupt flag
bits : 5 - 5 (1 bit)

PLLSAI1RDYF : PLLSAI1 ready interrupt flag
bits : 6 - 6 (1 bit)

HSECSSF : HSE Clock security system interrupt flag
bits : 8 - 8 (1 bit)

LSECSSF : LSE Clock security system interrupt flag
bits : 9 - 9 (1 bit)

HSI48RDYF : HSI48 ready interrupt flag
bits : 10 - 10 (1 bit)

LSI2RDYF : LSI2 ready interrupt flag
bits : 11 - 11 (1 bit)


CICR

Clock interrupt clear register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CICR CICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSI1RDYC LSERDYC MSIRDYC HSIRDYC HSERDYC PLLRDYC PLLSAI1RDYC HSECSSC LSECSSC HSI48RDYC LSI2RDYC

LSI1RDYC : LSI1 ready interrupt clear
bits : 0 - 0 (1 bit)

LSERDYC : LSE ready interrupt clear
bits : 1 - 1 (1 bit)

MSIRDYC : MSI ready interrupt clear
bits : 2 - 2 (1 bit)

HSIRDYC : HSI ready interrupt clear
bits : 3 - 3 (1 bit)

HSERDYC : HSE ready interrupt clear
bits : 4 - 4 (1 bit)

PLLRDYC : PLL ready interrupt clear
bits : 5 - 5 (1 bit)

PLLSAI1RDYC : PLLSAI1 ready interrupt clear
bits : 6 - 6 (1 bit)

HSECSSC : HSE Clock security system interrupt clear
bits : 8 - 8 (1 bit)

LSECSSC : LSE Clock security system interrupt clear
bits : 9 - 9 (1 bit)

HSI48RDYC : HSI48 ready interrupt clear
bits : 10 - 10 (1 bit)

LSI2RDYC : LSI2 ready interrupt clear
bits : 11 - 11 (1 bit)


SMPSCR

Step Down converter control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPSCR SMPSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMPSSEL SMPSDIV SMPSSWS

SMPSSEL : Step Down converter clock selection
bits : 0 - 1 (2 bit)
access : read-write

SMPSDIV : Step Down converter clock prescaler
bits : 4 - 5 (2 bit)
access : read-write

SMPSSWS : Step Down converter clock switch status
bits : 8 - 9 (2 bit)
access : read-only


AHB1RSTR

AHB1 peripheral reset register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB1RSTR AHB1RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1RST DMA2RST DMAMUXRST CRCRST TSCRST

DMA1RST : DMA1 reset
bits : 0 - 0 (1 bit)

DMA2RST : DMA2 reset
bits : 1 - 1 (1 bit)

DMAMUXRST : DMAMUX reset
bits : 2 - 2 (1 bit)

CRCRST : CRC reset
bits : 12 - 12 (1 bit)

TSCRST : Touch Sensing Controller reset
bits : 16 - 16 (1 bit)


AHB2RSTR

AHB2 peripheral reset register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB2RSTR AHB2RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOARST GPIOBRST GPIOCRST GPIODRST GPIOERST GPIOHRST ADCRST AES1RST

GPIOARST : IO port A reset
bits : 0 - 0 (1 bit)

GPIOBRST : IO port B reset
bits : 1 - 1 (1 bit)

GPIOCRST : IO port C reset
bits : 2 - 2 (1 bit)

GPIODRST : IO port D reset
bits : 3 - 3 (1 bit)

GPIOERST : IO port E reset
bits : 4 - 4 (1 bit)

GPIOHRST : IO port H reset
bits : 7 - 7 (1 bit)

ADCRST : ADC reset
bits : 13 - 13 (1 bit)

AES1RST : AES1 hardware accelerator reset
bits : 16 - 16 (1 bit)


AHB3RSTR

AHB3 peripheral reset register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB3RSTR AHB3RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QSPIRST PKARST AES2RST RNGRST HSEMRST IPCCRST FLASHRST

QSPIRST : Quad SPI memory interface reset
bits : 8 - 8 (1 bit)

PKARST : PKA interface reset
bits : 16 - 16 (1 bit)

AES2RST : AES2 interface reset
bits : 17 - 17 (1 bit)

RNGRST : RNG interface reset
bits : 18 - 18 (1 bit)

HSEMRST : HSEM interface reset
bits : 19 - 19 (1 bit)

IPCCRST : IPCC interface reset
bits : 20 - 20 (1 bit)

FLASHRST : Flash interface reset
bits : 25 - 25 (1 bit)


APB1RSTR1

APB1 peripheral reset register 1
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1RSTR1 APB1RSTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2RST LCDRST SPI2RST I2C1RST I2C3RST CRSRST USBFSRST LPTIM1RST

TIM2RST : TIM2 timer reset
bits : 0 - 0 (1 bit)

LCDRST : LCD interface reset
bits : 9 - 9 (1 bit)

SPI2RST : SPI2 reset
bits : 14 - 14 (1 bit)

I2C1RST : I2C1 reset
bits : 21 - 21 (1 bit)

I2C3RST : I2C3 reset
bits : 23 - 23 (1 bit)

CRSRST : CRS reset
bits : 24 - 24 (1 bit)

USBFSRST : USB FS reset
bits : 26 - 26 (1 bit)

LPTIM1RST : Low Power Timer 1 reset
bits : 31 - 31 (1 bit)


APB1RSTR2

APB1 peripheral reset register 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1RSTR2 APB1RSTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPUART1RST LPTIM2RST

LPUART1RST : Low-power UART 1 reset
bits : 0 - 0 (1 bit)

LPTIM2RST : Low-power timer 2 reset
bits : 5 - 5 (1 bit)


ICSCR

Internal clock sources calibration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICSCR ICSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSICAL MSITRIM HSICAL HSITRIM

MSICAL : MSI clock calibration
bits : 0 - 7 (8 bit)
access : read-only

MSITRIM : MSI clock trimming
bits : 8 - 15 (8 bit)
access : read-write

HSICAL : HSI clock calibration
bits : 16 - 23 (8 bit)
access : read-only

HSITRIM : HSI clock trimming
bits : 24 - 30 (7 bit)
access : read-write


APB2RSTR

APB2 peripheral reset register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2RSTR APB2RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1RST SPI1RST USART1RST TIM16RST TIM17RST SAI1RST

TIM1RST : TIM1 timer reset
bits : 11 - 11 (1 bit)

SPI1RST : SPI1 reset
bits : 12 - 12 (1 bit)

USART1RST : USART1 reset
bits : 14 - 14 (1 bit)

TIM16RST : TIM16 timer reset
bits : 17 - 17 (1 bit)

TIM17RST : TIM17 timer reset
bits : 18 - 18 (1 bit)

SAI1RST : Serial audio interface 1 (SAI1) reset
bits : 21 - 21 (1 bit)


APB3RSTR

APB3 peripheral reset register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB3RSTR APB3RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFRST

RFRST : Radio system BLE reset
bits : 0 - 0 (1 bit)


AHB1ENR

AHB1 peripheral clock enable register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB1ENR AHB1ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1EN DMA2EN DMAMUXEN CRCEN TSCEN

DMA1EN : DMA1 clock enable
bits : 0 - 0 (1 bit)

DMA2EN : DMA2 clock enable
bits : 1 - 1 (1 bit)

DMAMUXEN : DMAMUX clock enable
bits : 2 - 2 (1 bit)

CRCEN : CPU1 CRC clock enable
bits : 12 - 12 (1 bit)

TSCEN : Touch Sensing Controller clock enable
bits : 16 - 16 (1 bit)


AHB2ENR

AHB2 peripheral clock enable register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB2ENR AHB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOAEN GPIOBEN GPIOCEN GPIODEN GPIOEEN GPIOHEN ADCEN AES1EN

GPIOAEN : IO port A clock enable
bits : 0 - 0 (1 bit)

GPIOBEN : IO port B clock enable
bits : 1 - 1 (1 bit)

GPIOCEN : IO port C clock enable
bits : 2 - 2 (1 bit)

GPIODEN : IO port D clock enable
bits : 3 - 3 (1 bit)

GPIOEEN : IO port E clock enable
bits : 4 - 4 (1 bit)

GPIOHEN : IO port H clock enable
bits : 7 - 7 (1 bit)

ADCEN : ADC clock enable
bits : 13 - 13 (1 bit)

AES1EN : AES1 accelerator clock enable
bits : 16 - 16 (1 bit)


AHB3ENR

AHB3 peripheral clock enable register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB3ENR AHB3ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QSPIEN PKAEN AES2EN RNGEN HSEMEN IPCCEN FLASHEN

QSPIEN : QSPIEN
bits : 8 - 8 (1 bit)

PKAEN : PKAEN
bits : 16 - 16 (1 bit)

AES2EN : AES2EN
bits : 17 - 17 (1 bit)

RNGEN : RNGEN
bits : 18 - 18 (1 bit)

HSEMEN : HSEMEN
bits : 19 - 19 (1 bit)

IPCCEN : IPCCEN
bits : 20 - 20 (1 bit)

FLASHEN : FLASHEN
bits : 25 - 25 (1 bit)


APB1ENR1

APB1ENR1
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1ENR1 APB1ENR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2EN LCDEN RTCAPBEN WWDGEN SPI2EN I2C1EN I2C3EN CRSEN USBEN LPTIM1EN

TIM2EN : CPU1 TIM2 timer clock enable
bits : 0 - 0 (1 bit)

LCDEN : CPU1 LCD clock enable
bits : 9 - 9 (1 bit)

RTCAPBEN : CPU1 RTC APB clock enable
bits : 10 - 10 (1 bit)

WWDGEN : CPU1 Window watchdog clock enable
bits : 11 - 11 (1 bit)

SPI2EN : CPU1 SPI2 clock enable
bits : 14 - 14 (1 bit)

I2C1EN : CPU1 I2C1 clock enable
bits : 21 - 21 (1 bit)

I2C3EN : CPU1 I2C3 clock enable
bits : 23 - 23 (1 bit)

CRSEN : CPU1 CRS clock enable
bits : 24 - 24 (1 bit)

USBEN : CPU1 USB clock enable
bits : 26 - 26 (1 bit)

LPTIM1EN : CPU1 Low power timer 1 clock enable
bits : 31 - 31 (1 bit)


APB1ENR2

APB1 peripheral clock enable register 2
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1ENR2 APB1ENR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPUART1EN LPTIM2EN

LPUART1EN : CPU1 Low power UART 1 clock enable
bits : 0 - 0 (1 bit)

LPTIM2EN : CPU1 LPTIM2EN
bits : 5 - 5 (1 bit)


APB2ENR

APB2ENR
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2ENR APB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1EN SPI1EN USART1EN TIM16EN TIM17EN SAI1EN

TIM1EN : CPU1 TIM1 timer clock enable
bits : 11 - 11 (1 bit)

SPI1EN : CPU1 SPI1 clock enable
bits : 12 - 12 (1 bit)

USART1EN : CPU1 USART1clock enable
bits : 14 - 14 (1 bit)

TIM16EN : CPU1 TIM16 timer clock enable
bits : 17 - 17 (1 bit)

TIM17EN : CPU1 TIM17 timer clock enable
bits : 18 - 18 (1 bit)

SAI1EN : CPU1 SAI1 clock enable
bits : 21 - 21 (1 bit)


AHB1SMENR

AHB1 peripheral clocks enable in Sleep and Stop modes register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB1SMENR AHB1SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1SMEN DMA2SMEN DMAMUXSMEN SRAM1SMEN CRCSMEN TSCSMEN

DMA1SMEN : CPU1 DMA1 clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)

DMA2SMEN : CPU1 DMA2 clocks enable during Sleep and Stop modes
bits : 1 - 1 (1 bit)

DMAMUXSMEN : CPU1 DMAMUX clocks enable during Sleep and Stop modes
bits : 2 - 2 (1 bit)

SRAM1SMEN : CPU1 SRAM1 interface clocks enable during Sleep and Stop modes
bits : 9 - 9 (1 bit)

CRCSMEN : CPU1 CRCSMEN
bits : 12 - 12 (1 bit)

TSCSMEN : CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes
bits : 16 - 16 (1 bit)


AHB2SMENR

AHB2 peripheral clocks enable in Sleep and Stop modes register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB2SMENR AHB2SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOASMEN GPIOBSMEN GPIOCSMEN GPIODSMEN GPIOESMEN GPIOHSMEN ADCFSSMEN AES1SMEN

GPIOASMEN : CPU1 IO port A clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)

GPIOBSMEN : CPU1 IO port B clocks enable during Sleep and Stop modes
bits : 1 - 1 (1 bit)

GPIOCSMEN : CPU1 IO port C clocks enable during Sleep and Stop modes
bits : 2 - 2 (1 bit)

GPIODSMEN : CPU1 IO port D clocks enable during Sleep and Stop modes
bits : 3 - 3 (1 bit)

GPIOESMEN : CPU1 IO port E clocks enable during Sleep and Stop modes
bits : 4 - 4 (1 bit)

GPIOHSMEN : CPU1 IO port H clocks enable during Sleep and Stop modes
bits : 7 - 7 (1 bit)

ADCFSSMEN : CPU1 ADC clocks enable during Sleep and Stop modes
bits : 13 - 13 (1 bit)

AES1SMEN : CPU1 AES1 accelerator clocks enable during Sleep and Stop modes
bits : 16 - 16 (1 bit)


AHB3SMENR

AHB3 peripheral clocks enable in Sleep and Stop modes register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB3SMENR AHB3SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QSPISMEN PKASMEN AES2SMEN RNGSMEN SRAM2SMEN FLASHSMEN

QSPISMEN : QSPISMEN
bits : 8 - 8 (1 bit)

PKASMEN : PKA accelerator clocks enable during CPU1 sleep mode
bits : 16 - 16 (1 bit)

AES2SMEN : AES2 accelerator clocks enable during CPU1 sleep mode
bits : 17 - 17 (1 bit)

RNGSMEN : True RNG clocks enable during CPU1 sleep mode
bits : 18 - 18 (1 bit)

SRAM2SMEN : SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode
bits : 24 - 24 (1 bit)

FLASHSMEN : Flash interface clocks enable during CPU1 sleep mode
bits : 25 - 25 (1 bit)


APB1SMENR1

APB1SMENR1
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1SMENR1 APB1SMENR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2SMEN LCDSMEN RTCAPBSMEN WWDGSMEN SPI2SMEN I2C1SMEN I2C3SMEN CRSMEN USBSMEN LPTIM1SMEN

TIM2SMEN : TIM2 timer clocks enable during CPU1 Sleep mode
bits : 0 - 0 (1 bit)

LCDSMEN : LCD clocks enable during CPU1 Sleep mode
bits : 9 - 9 (1 bit)

RTCAPBSMEN : RTC APB clocks enable during CPU1 Sleep mode
bits : 10 - 10 (1 bit)

WWDGSMEN : Window watchdog clocks enable during CPU1 Sleep mode
bits : 11 - 11 (1 bit)

SPI2SMEN : SPI2 clocks enable during CPU1 Sleep mode
bits : 14 - 14 (1 bit)

I2C1SMEN : I2C1 clocks enable during CPU1 Sleep mode
bits : 21 - 21 (1 bit)

I2C3SMEN : I2C3 clocks enable during CPU1 Sleep mode
bits : 23 - 23 (1 bit)

CRSMEN : CRS clocks enable during CPU1 Sleep mode
bits : 24 - 24 (1 bit)

USBSMEN : USB FS clocks enable during CPU1 Sleep mode
bits : 26 - 26 (1 bit)

LPTIM1SMEN : Low power timer 1 clocks enable during CPU1 Sleep mode
bits : 31 - 31 (1 bit)


APB1SMENR2

APB1 peripheral clocks enable in Sleep and Stop modes register 2
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1SMENR2 APB1SMENR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPUART1SMEN LPTIM2SMEN

LPUART1SMEN : Low power UART 1 clocks enable during CPU1 Sleep mode
bits : 0 - 0 (1 bit)

LPTIM2SMEN : Low power timer 2 clocks enable during CPU1 Sleep mode
bits : 5 - 5 (1 bit)


CFGR

Clock configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW SWS HPRE PPRE1 PPRE2 STOPWUCK HPREF PPRE1F PPRE2F MCOSEL MCOPRE

SW : System clock switch
bits : 0 - 1 (2 bit)
access : read-write

SWS : System clock switch status
bits : 2 - 3 (2 bit)
access : read-only

HPRE : AHB prescaler
bits : 4 - 7 (4 bit)
access : read-write

PPRE1 : PB low-speed prescaler (APB1)
bits : 8 - 10 (3 bit)
access : read-write

PPRE2 : APB high-speed prescaler (APB2)
bits : 11 - 13 (3 bit)
access : read-write

STOPWUCK : Wakeup from Stop and CSS backup clock selection
bits : 15 - 15 (1 bit)
access : read-write

HPREF : AHB prescaler flag
bits : 16 - 16 (1 bit)
access : read-only

PPRE1F : APB1 prescaler flag
bits : 17 - 17 (1 bit)
access : read-only

PPRE2F : APB2 prescaler flag
bits : 18 - 18 (1 bit)
access : read-only

MCOSEL : Microcontroller clock output
bits : 24 - 27 (4 bit)
access : read-write

MCOPRE : Microcontroller clock output prescaler
bits : 28 - 30 (3 bit)
access : read-write


APB2SMENR

APB2SMENR
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2SMENR APB2SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1SMEN SPI1SMEN USART1SMEN TIM16SMEN TIM17SMEN SAI1SMEN

TIM1SMEN : TIM1 timer clocks enable during CPU1 Sleep mode
bits : 11 - 11 (1 bit)

SPI1SMEN : SPI1 clocks enable during CPU1 Sleep mode
bits : 12 - 12 (1 bit)

USART1SMEN : USART1clocks enable during CPU1 Sleep mode
bits : 14 - 14 (1 bit)

TIM16SMEN : TIM16 timer clocks enable during CPU1 Sleep mode
bits : 17 - 17 (1 bit)

TIM17SMEN : TIM17 timer clocks enable during CPU1 Sleep mode
bits : 18 - 18 (1 bit)

SAI1SMEN : SAI1 clocks enable during CPU1 Sleep mode
bits : 21 - 21 (1 bit)


CCIPR

CCIPR
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCIPR CCIPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART1SEL LPUART1SEL I2C1SEL I2C3SEL LPTIM1SEL LPTIM2SEL SAI1SEL CLK48SEL ADCSEL RNGSEL

USART1SEL : USART1 clock source selection
bits : 0 - 1 (2 bit)

LPUART1SEL : LPUART1 clock source selection
bits : 10 - 11 (2 bit)

I2C1SEL : I2C1 clock source selection
bits : 12 - 13 (2 bit)

I2C3SEL : I2C3 clock source selection
bits : 16 - 17 (2 bit)

LPTIM1SEL : Low power timer 1 clock source selection
bits : 18 - 19 (2 bit)

LPTIM2SEL : Low power timer 2 clock source selection
bits : 20 - 21 (2 bit)

SAI1SEL : SAI1 clock source selection
bits : 22 - 23 (2 bit)

CLK48SEL : 48 MHz clock source selection
bits : 26 - 27 (2 bit)

ADCSEL : ADCs clock source selection
bits : 28 - 29 (2 bit)

RNGSEL : RNG clock source selection
bits : 30 - 31 (2 bit)


BDCR

BDCR
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDCR BDCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSEON LSERDY LSEBYP LSEDRV LSECSSON LSECSSD_ RTCSEL RTCEN BDRST LSCOEN LSCOSEL

LSEON : LSE oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSERDY : LSE oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

LSEBYP : LSE oscillator bypass
bits : 2 - 2 (1 bit)
access : read-write

LSEDRV : SE oscillator drive capability
bits : 3 - 4 (2 bit)
access : read-write

LSECSSON : LSECSSON
bits : 5 - 5 (1 bit)
access : read-write

LSECSSD_ : CSS on LSE failure detection
bits : 6 - 6 (1 bit)
access : read-only

RTCSEL : RTC clock source selection
bits : 8 - 9 (2 bit)
access : read-write

RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)
access : read-write

BDRST : Backup domain software reset
bits : 16 - 16 (1 bit)
access : read-write

LSCOEN : Low speed clock output enable
bits : 24 - 24 (1 bit)
access : read-write

LSCOSEL : Low speed clock output selection
bits : 25 - 25 (1 bit)
access : read-write


CSR

CSR
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSI1ON LSI1RDY LSI2ON LSI2RDY LSI2TRIMEN LSI2TRIMOK LSI2BW RFWKPSEL RFRSTS RMVF OBLRSTF PINRSTF BORRSTF SFTRSTF IWDGRSTF WWDGRSTF LPWRRSTF

LSI1ON : LSI1 oscillator enabled
bits : 0 - 0 (1 bit)
access : read-write

LSI1RDY : LSI1 oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

LSI2ON : LSI2 oscillator enabled
bits : 2 - 2 (1 bit)
access : read-write

LSI2RDY : LSI2 oscillator ready
bits : 3 - 3 (1 bit)
access : read-only

LSI2TRIMEN : LSI2 oscillator trimming enable
bits : 4 - 4 (1 bit)
access : read-write

LSI2TRIMOK : LSI2 oscillator trim OK
bits : 5 - 5 (1 bit)
access : read-only

LSI2BW : LSI2 oscillator bias configuration
bits : 8 - 11 (4 bit)
access : read-write

RFWKPSEL : RF system wakeup clock source selection
bits : 14 - 15 (2 bit)
access : read-write

RFRSTS : Radio system BLE and 802.15.4 reset status
bits : 16 - 16 (1 bit)
access : read-only

RMVF : Remove reset flag
bits : 23 - 23 (1 bit)
access : read-write

OBLRSTF : Option byte loader reset flag
bits : 25 - 25 (1 bit)
access : read-only

PINRSTF : Pin reset flag
bits : 26 - 26 (1 bit)
access : read-only

BORRSTF : BOR flag
bits : 27 - 27 (1 bit)
access : read-only

SFTRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-only

IWDGRSTF : Independent window watchdog reset flag
bits : 29 - 29 (1 bit)
access : read-only

WWDGRSTF : Window watchdog reset flag
bits : 30 - 30 (1 bit)
access : read-only

LPWRRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
access : read-only


CRRCR

Clock recovery RC register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRRCR CRRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSI48ON HSI48RDY HSI48CAL

HSI48ON : HSI48 oscillator enabled
bits : 0 - 0 (1 bit)
access : read-write

HSI48RDY : HSI48 clock ready
bits : 1 - 1 (1 bit)
access : read-only

HSI48CAL : HSI48 clock calibration
bits : 7 - 15 (9 bit)
access : read-only


HSECR

Clock HSE register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSECR HSECR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UNLOCKED HSES HSEGMC HSETUNE

UNLOCKED : Register lock system
bits : 0 - 0 (1 bit)
access : read-write

HSES : HSE Sense amplifier threshold
bits : 3 - 3 (1 bit)
access : read-write

HSEGMC : HSE current control
bits : 4 - 6 (3 bit)
access : read-write

HSETUNE : HSE capacitor tuning
bits : 8 - 13 (6 bit)
access : read-only


PLLCFGR

PLLSYS configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLCFGR PLLCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLSRC PLLM PLLN PLLPEN PLLP PLLQEN PLLQ PLLREN PLLR

PLLSRC : Main PLL, PLLSAI1 and PLLSAI2 entry clock source
bits : 0 - 1 (2 bit)

PLLM : Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
bits : 4 - 6 (3 bit)

PLLN : Main PLLSYS multiplication factor N
bits : 8 - 14 (7 bit)

PLLPEN : Main PLLSYSP output enable
bits : 16 - 16 (1 bit)

PLLP : Main PLL division factor P for PPLSYSSAICLK
bits : 17 - 21 (5 bit)

PLLQEN : Main PLLSYSQ output enable
bits : 24 - 24 (1 bit)

PLLQ : Main PLLSYS division factor Q for PLLSYSUSBCLK
bits : 25 - 27 (3 bit)

PLLREN : Main PLLSYSR PLLCLK output enable
bits : 28 - 28 (1 bit)

PLLR : Main PLLSYS division factor R for SYSCLK (system clock)
bits : 29 - 31 (3 bit)



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