\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Control register CPU1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXOIE : processor 1 Receive channel occupied interrupt enable
bits : 0 - 0 (1 bit)
TXFIE : processor 1 Transmit channel free interrupt enable
bits : 16 - 16 (1 bit)
Control register CPU2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXOIE : processor 2 Receive channel occupied interrupt enable
bits : 0 - 0 (1 bit)
TXFIE : processor 2 Transmit channel free interrupt enable
bits : 16 - 16 (1 bit)
Mask register CPU2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1OM : processor 2 Receive channel 1 occupied interrupt enable
bits : 0 - 0 (1 bit)
CH2OM : processor 2 Receive channel 2 occupied interrupt enable
bits : 1 - 1 (1 bit)
CH3OM : processor 2 Receive channel 3 occupied interrupt enable
bits : 2 - 2 (1 bit)
CH4OM : processor 2 Receive channel 4 occupied interrupt enable
bits : 3 - 3 (1 bit)
CH5OM : processor 2 Receive channel 5 occupied interrupt enable
bits : 4 - 4 (1 bit)
CH6OM : processor 2 Receive channel 6 occupied interrupt enable
bits : 5 - 5 (1 bit)
CH1FM : processor 2 Transmit channel 1 free interrupt mask
bits : 16 - 16 (1 bit)
CH2FM : processor 2 Transmit channel 2 free interrupt mask
bits : 17 - 17 (1 bit)
CH3FM : processor 2 Transmit channel 3 free interrupt mask
bits : 18 - 18 (1 bit)
CH4FM : processor 2 Transmit channel 4 free interrupt mask
bits : 19 - 19 (1 bit)
CH5FM : processor 2 Transmit channel 5 free interrupt mask
bits : 20 - 20 (1 bit)
CH6FM : processor 2 Transmit channel 6 free interrupt mask
bits : 21 - 21 (1 bit)
Status Set or Clear register CPU2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH1C : processor 2 Receive channel 1 status clear
bits : 0 - 0 (1 bit)
CH2C : processor 2 Receive channel 2 status clear
bits : 1 - 1 (1 bit)
CH3C : processor 2 Receive channel 3 status clear
bits : 2 - 2 (1 bit)
CH4C : processor 2 Receive channel 4 status clear
bits : 3 - 3 (1 bit)
CH5C : processor 2 Receive channel 5 status clear
bits : 4 - 4 (1 bit)
CH6C : processor 2 Receive channel 6 status clear
bits : 5 - 5 (1 bit)
CH1S : processor 2 Transmit channel 1 status set
bits : 16 - 16 (1 bit)
CH2S : processor 2 Transmit channel 2 status set
bits : 17 - 17 (1 bit)
CH3S : processor 2 Transmit channel 3 status set
bits : 18 - 18 (1 bit)
CH4S : processor 2 Transmit channel 4 status set
bits : 19 - 19 (1 bit)
CH5S : processor 2 Transmit channel 5 status set
bits : 20 - 20 (1 bit)
CH6S : processor 2 Transmit channel 6 status set
bits : 21 - 21 (1 bit)
CPU2 to CPU1 status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH1F : processor 2 transmit to process 1 Receive channel 1 status flag
bits : 0 - 0 (1 bit)
CH2F : processor 2 transmit to process 1 Receive channel 2 status flag
bits : 1 - 1 (1 bit)
CH3F : processor 2 transmit to process 1 Receive channel 3 status flag
bits : 2 - 2 (1 bit)
CH4F : processor 2 transmit to process 1 Receive channel 4 status flag
bits : 3 - 3 (1 bit)
CH5F : processor 2 transmit to process 1 Receive channel 5 status flag
bits : 4 - 4 (1 bit)
CH6F : processor 2 transmit to process 1 Receive channel 6 status flag
bits : 5 - 5 (1 bit)
IPCC Hardware configuration register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHANNELS : Number of channels per CPU supported by the IP, range 1 to 16
bits : 0 - 7 (8 bit)
IPCC version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINREV : Minor Revision
bits : 0 - 3 (4 bit)
MAJREV : Major Revision
bits : 4 - 7 (4 bit)
IPCC indentification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPID : Identification Code
bits : 0 - 31 (32 bit)
IPCC size indentification register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SID : Size Identification Code
bits : 0 - 31 (32 bit)
Mask register CPU1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1OM : processor 1 Receive channel 1 occupied interrupt enable
bits : 0 - 0 (1 bit)
CH2OM : processor 1 Receive channel 2 occupied interrupt enable
bits : 1 - 1 (1 bit)
CH3OM : processor 1 Receive channel 3 occupied interrupt enable
bits : 2 - 2 (1 bit)
CH4OM : processor 1 Receive channel 4 occupied interrupt enable
bits : 3 - 3 (1 bit)
CH5OM : processor 1 Receive channel 5 occupied interrupt enable
bits : 4 - 4 (1 bit)
CH6OM : processor 1 Receive channel 6 occupied interrupt enable
bits : 5 - 5 (1 bit)
CH1FM : processor 1 Transmit channel 1 free interrupt mask
bits : 16 - 16 (1 bit)
CH2FM : processor 1 Transmit channel 2 free interrupt mask
bits : 17 - 17 (1 bit)
CH3FM : processor 1 Transmit channel 3 free interrupt mask
bits : 18 - 18 (1 bit)
CH4FM : processor 1 Transmit channel 4 free interrupt mask
bits : 19 - 19 (1 bit)
CH5FM : processor 1 Transmit channel 5 free interrupt mask
bits : 20 - 20 (1 bit)
CH6FM : processor 1 Transmit channel 6 free interrupt mask
bits : 21 - 21 (1 bit)
Status Set or Clear register CPU1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH1C : processor 1 Receive channel 1 status clear
bits : 0 - 0 (1 bit)
CH2C : processor 1 Receive channel 2 status clear
bits : 1 - 1 (1 bit)
CH3C : processor 1 Receive channel 3 status clear
bits : 2 - 2 (1 bit)
CH4C : processor 1 Receive channel 4 status clear
bits : 3 - 3 (1 bit)
CH5C : processor 1 Receive channel 5 status clear
bits : 4 - 4 (1 bit)
CH6C : processor 1 Receive channel 6 status clear
bits : 5 - 5 (1 bit)
CH1S : processor 1 Transmit channel 1 status set
bits : 16 - 16 (1 bit)
CH2S : processor 1 Transmit channel 2 status set
bits : 17 - 17 (1 bit)
CH3S : processor 1 Transmit channel 3 status set
bits : 18 - 18 (1 bit)
CH4S : processor 1 Transmit channel 4 status set
bits : 19 - 19 (1 bit)
CH5S : processor 1 Transmit channel 5 status set
bits : 20 - 20 (1 bit)
CH6S : processor 1 Transmit channel 6 status set
bits : 21 - 21 (1 bit)
CPU1 to CPU2 status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH1F : processor 1 transmit to process 2 Receive channel 1 status flag
bits : 0 - 0 (1 bit)
CH2F : processor 1 transmit to process 2 Receive channel 2 status flag
bits : 1 - 1 (1 bit)
CH3F : processor 1 transmit to process 2 Receive channel 3 status flag
bits : 2 - 2 (1 bit)
CH4F : processor 1 transmit to process 2 Receive channel 4 status flag
bits : 3 - 3 (1 bit)
CH5F : processor 1 transmit to process 2 Receive channel 5 status flag
bits : 4 - 4 (1 bit)
CH6F : processor 1 transmit to process 2 Receive channel 6 status flag
bits : 5 - 5 (1 bit)
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