\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
rising trigger selection register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RT : Rising trigger event configuration bit of Configurable Event input
bits : 0 - 21 (22 bit)
RT_31 : Rising trigger event configuration bit of Configurable Event input
bits : 31 - 31 (1 bit)
rising trigger selection register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RT33 : Rising trigger event configuration bit of Configurable Event input
bits : 1 - 1 (1 bit)
RT40_41 : Rising trigger event configuration bit of Configurable Event input
bits : 8 - 9 (2 bit)
falling trigger selection register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FT33 : Falling trigger event configuration bit of Configurable Event input
bits : 1 - 1 (1 bit)
FT40_41 : Falling trigger event configuration bit of Configurable Event input
bits : 8 - 9 (2 bit)
software interrupt event register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWI33 : Software interrupt on event
bits : 1 - 1 (1 bit)
SWI40_41 : Software interrupt on event
bits : 8 - 9 (2 bit)
pending register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIF33 : Configurable event inputs x+32 Pending bit.
bits : 1 - 1 (1 bit)
PIF40_41 : Configurable event inputs x+32 Pending bit.
bits : 8 - 9 (2 bit)
EXTI Hardware configuration registers
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPUEVENT : HW configuration CPU event generation
bits : 0 - 31 (32 bit)
Hardware configuration registers
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPUEVENT : HW configuration CPU event generation
bits : 0 - 31 (32 bit)
Hardware configuration registers
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPUEVENT : HW configuration CPU event generation
bits : 0 - 31 (32 bit)
Hardware configuration registers
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EVENT_TRG : HW configuration event trigger type
bits : 0 - 31 (32 bit)
Hardware configuration registers
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EVENT_TRG : HW configuration event trigger type
bits : 0 - 31 (32 bit)
Hardware configuration registers
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EVENT_TRG : HW configuration event trigger type
bits : 0 - 31 (32 bit)
Hardware configuration register 1
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NBEVENTS : HW configuration number of event
bits : 0 - 7 (8 bit)
NBCPUS : HW configuration number of CPUs
bits : 8 - 11 (4 bit)
CPUEVTEN : HW configuration of CPU(m) event output enable
bits : 12 - 15 (4 bit)
EXTI IP Version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINREV : Minor Revision number
bits : 0 - 3 (4 bit)
MAJREV : Major Revision number
bits : 4 - 7 (4 bit)
Identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPID : IP Identification
bits : 0 - 31 (32 bit)
Size ID register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SID : Size Identification
bits : 0 - 31 (32 bit)
falling trigger selection register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FT : Falling trigger event configuration bit of Configurable Event input
bits : 0 - 21 (22 bit)
FT_31 : Falling trigger event configuration bit of Configurable Event input
bits : 31 - 31 (1 bit)
software interrupt event register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWI : Software interrupt on event
bits : 0 - 21 (22 bit)
SWI_31 : Software interrupt on event
bits : 31 - 31 (1 bit)
CPUm wakeup with interrupt mask register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM : CPU(m) wakeup with interrupt Mask on Event input
bits : 0 - 31 (32 bit)
CPUm wakeup with event mask register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM0_15 : CPU(m) Wakeup with event generation Mask on Event input
bits : 0 - 15 (16 bit)
EM17_21 : CPU(m) Wakeup with event generation Mask on Event input
bits : 17 - 21 (5 bit)
CPUm wakeup with interrupt mask register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM : CPUm Wakeup with interrupt Mask on Event input
bits : 0 - 16 (17 bit)
CPUm wakeup with event mask register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM : CPU(m) Wakeup with event generation Mask on Event input
bits : 8 - 9 (2 bit)
EXTI pending register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIF : Configurable event inputs Pending bit
bits : 0 - 21 (22 bit)
PIF_31 : Configurable event inputs Pending bit
bits : 31 - 31 (1 bit)
CPUm wakeup with interrupt mask register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM : CPU(m) wakeup with interrupt Mask on Event input
bits : 0 - 31 (32 bit)
CPUm wakeup with event mask register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM0_15 : CPU(m) Wakeup with event generation Mask on Event input
bits : 0 - 15 (16 bit)
EM17_21 : CPU(m) Wakeup with event generation Mask on Event input
bits : 17 - 21 (5 bit)
CPUm wakeup with interrupt mask register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM : CPUm Wakeup with interrupt Mask on Event input
bits : 0 - 16 (17 bit)
CPUm wakeup with event mask register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM : CPU(m) Wakeup with event generation Mask on Event input
bits : 8 - 9 (2 bit)
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