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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

ADC_ISR (ISR)

ADC_CFGR2 (CFGR2)

ADC_SMPR (SMPR)

ADC_AWD1TR (AWD1TR)

ADC_AWD2TR (AWD2TR)

ADC_CHSELR0 (CHSELR0)

ADC_CHSELR1 (CHSELR1)

ADC_AWD3TR (AWD3TR)

ADC_CCR (CCR)

ADC_IER (IER)

ADC_DR (DR)

ADC_CR (CR)

ADC_AWD2CR (AWD2CR)

ADC_AWD3CR (AWD3CR)

ADC_CALFACT (CALFACT)

ADC_CFGR1 (CFGR1)


ADC_ISR (ISR)

ADC interrupt and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_ISR ADC_ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADRDY EOSMP EOC EOS OVR AWD1 AWD2 AWD3 EOCAL CCRDY

ADRDY : ADRDY
bits : 0 - 0 (1 bit)

EOSMP : EOSMP
bits : 1 - 1 (1 bit)

EOC : EOC
bits : 2 - 2 (1 bit)

EOS : EOS
bits : 3 - 3 (1 bit)

OVR : OVR
bits : 4 - 4 (1 bit)

AWD1 : AWD1
bits : 7 - 7 (1 bit)

AWD2 : AWD2
bits : 8 - 8 (1 bit)

AWD3 : AWD3
bits : 9 - 9 (1 bit)

EOCAL : EOCAL
bits : 11 - 11 (1 bit)

CCRDY : CCRDY
bits : 13 - 13 (1 bit)


ADC_CFGR2 (CFGR2)

ADC configuration register 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CFGR2 ADC_CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVSE OVSR0 OVSR1 OVSR2 OVSS0 OVSS1 OVSS2 OVSS3 TOVS LFTRIG CKMODE

OVSE : OVSE
bits : 0 - 0 (1 bit)

OVSR0 : OVSR0
bits : 2 - 2 (1 bit)

OVSR1 : OVSR1
bits : 3 - 3 (1 bit)

OVSR2 : OVSR2
bits : 4 - 4 (1 bit)

OVSS0 : OVSS0
bits : 5 - 5 (1 bit)

OVSS1 : OVSS1
bits : 6 - 6 (1 bit)

OVSS2 : OVSS2
bits : 7 - 7 (1 bit)

OVSS3 : OVSS3
bits : 8 - 8 (1 bit)

TOVS : TOVS
bits : 9 - 9 (1 bit)

LFTRIG : LFTRIG
bits : 29 - 29 (1 bit)

CKMODE : CKMODE
bits : 30 - 31 (2 bit)


ADC_SMPR (SMPR)

ADC sampling time register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_SMPR ADC_SMPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMP1 SMP2 SMPSEL

SMP1 : SMP1
bits : 0 - 2 (3 bit)

SMP2 : SMP2
bits : 4 - 6 (3 bit)

SMPSEL : SMPSEL
bits : 8 - 25 (18 bit)


ADC_AWD1TR (AWD1TR)

ADC watchdog threshold register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_AWD1TR ADC_AWD1TR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LT1 HT1

LT1 : LT1
bits : 0 - 11 (12 bit)

HT1 : HT1
bits : 16 - 27 (12 bit)


ADC_AWD2TR (AWD2TR)

ADC watchdog threshold register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_AWD2TR ADC_AWD2TR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LT2 HT2

LT2 : LT2
bits : 0 - 11 (12 bit)

HT2 : HT2
bits : 16 - 27 (12 bit)


ADC_CHSELR0 (CHSELR0)

channel selection register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CHSELR0 ADC_CHSELR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHSEL

CHSEL : CHSEL
bits : 0 - 17 (18 bit)


ADC_CHSELR1 (CHSELR1)

channel selection register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : ADC_CHSELR0
reset_Mask : 0x0

ADC_CHSELR1 ADC_CHSELR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ1 SQ2 SQ3 SQ4 SQ5 SQ6 SQ7 SQ8

SQ1 : SQ1
bits : 0 - 3 (4 bit)

SQ2 : SQ2
bits : 4 - 7 (4 bit)

SQ3 : SQ3
bits : 8 - 11 (4 bit)

SQ4 : SQ4
bits : 12 - 15 (4 bit)

SQ5 : SQ5
bits : 16 - 19 (4 bit)

SQ6 : SQ6
bits : 20 - 23 (4 bit)

SQ7 : SQ7
bits : 24 - 27 (4 bit)

SQ8 : SQ8
bits : 28 - 31 (4 bit)


ADC_AWD3TR (AWD3TR)

ADC watchdog threshold register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_AWD3TR ADC_AWD3TR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LT3 HT3

LT3 : LT3
bits : 0 - 11 (12 bit)

HT3 : HT3
bits : 16 - 27 (12 bit)


ADC_CCR (CCR)

ADC common configuration register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CCR ADC_CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESC0 PRESC1 PRESC2 PRESC3 VREFEN TSEN VBATEN

PRESC0 : PRESC0
bits : 18 - 18 (1 bit)

PRESC1 : PRESC1
bits : 19 - 19 (1 bit)

PRESC2 : PRESC2
bits : 20 - 20 (1 bit)

PRESC3 : PRESC3
bits : 21 - 21 (1 bit)

VREFEN : VREFEN
bits : 22 - 22 (1 bit)

TSEN : TSEN
bits : 23 - 23 (1 bit)

VBATEN : VBATEN
bits : 24 - 24 (1 bit)


ADC_IER (IER)

ADC interrupt enable register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_IER ADC_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADRDYIE EOSMPIE EOCIE EOSIE OVRIE AWD1IE AWD2IE AWD3IE EOCALIE CCRDYIE

ADRDYIE : ADRDYIE
bits : 0 - 0 (1 bit)

EOSMPIE : EOSMPIE
bits : 1 - 1 (1 bit)

EOCIE : EOCIE
bits : 2 - 2 (1 bit)

EOSIE : EOSIE
bits : 3 - 3 (1 bit)

OVRIE : OVRIE
bits : 4 - 4 (1 bit)

AWD1IE : AWD1IE
bits : 7 - 7 (1 bit)

AWD2IE : AWD2IE
bits : 8 - 8 (1 bit)

AWD3IE : AWD3IE
bits : 9 - 9 (1 bit)

EOCALIE : EOCALIE
bits : 11 - 11 (1 bit)

CCRDYIE : CCRDYIE
bits : 13 - 13 (1 bit)


ADC_DR (DR)

ADC data register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADC_DR ADC_DR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA
bits : 0 - 15 (16 bit)


ADC_CR (CR)

ADC control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CR ADC_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADEN ADDIS ADSTART ADSTP ADVREGEN ADCAL

ADEN : ADEN
bits : 0 - 0 (1 bit)

ADDIS : ADDIS
bits : 1 - 1 (1 bit)

ADSTART : ADSTART
bits : 2 - 2 (1 bit)

ADSTP : ADSTP
bits : 4 - 4 (1 bit)

ADVREGEN : ADVREGEN
bits : 28 - 28 (1 bit)

ADCAL : ADCAL
bits : 31 - 31 (1 bit)


ADC_AWD2CR (AWD2CR)

ADC Analog Watchdog 2 Configuration register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_AWD2CR ADC_AWD2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD2CH

AWD2CH : AWD2CH
bits : 0 - 17 (18 bit)


ADC_AWD3CR (AWD3CR)

ADC Analog Watchdog 3 Configuration register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_AWD3CR ADC_AWD3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD3CH

AWD3CH : AWD3CH
bits : 0 - 17 (18 bit)


ADC_CALFACT (CALFACT)

ADC Calibration factor
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CALFACT ADC_CALFACT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALFACT

CALFACT : CALFACT
bits : 0 - 6 (7 bit)


ADC_CFGR1 (CFGR1)

ADC configuration register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CFGR1 ADC_CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAEN DMACFG SCANDIR RES ALIGN EXTSEL EXTEN OVRMOD CONT WAIT AUTOFF DISCEN CHSELRMOD AWD1SGL AWD1EN AWD1CH

DMAEN : DMAEN
bits : 0 - 0 (1 bit)

DMACFG : DMACFG
bits : 1 - 1 (1 bit)

SCANDIR : SCANDIR
bits : 2 - 2 (1 bit)

RES : RES
bits : 3 - 4 (2 bit)

ALIGN : ALIGN
bits : 5 - 5 (1 bit)

EXTSEL : EXTSEL
bits : 6 - 8 (3 bit)

EXTEN : EXTEN
bits : 10 - 11 (2 bit)

OVRMOD : OVRMOD
bits : 12 - 12 (1 bit)

CONT : CONT
bits : 13 - 13 (1 bit)

WAIT : WAIT
bits : 14 - 14 (1 bit)

AUTOFF : AUTOFF
bits : 15 - 15 (1 bit)

DISCEN : DISCEN
bits : 16 - 16 (1 bit)

CHSELRMOD : CHSELRMOD
bits : 21 - 21 (1 bit)

AWD1SGL : AWD1SGL
bits : 22 - 22 (1 bit)

AWD1EN : AWD1EN
bits : 23 - 23 (1 bit)

AWD1CH : AWD1CH
bits : 26 - 30 (5 bit)



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