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DAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CR

DHR8R1

DHR12RD

DHR12LD

DHR8RD

DOR1

SR

CCR

MCR

SWTRGR

SHSR1

SHHR

SHRR

DHR12R1

DHR12L1


CR

control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN1 TEN1 TSEL10 TSEL11 TSEL12 TSEL13 WAVE1 MAMP1 DMAEN1 DMAUDRIE1 CEN1

EN1 : DAC channel1 enable
bits : 0 - 0 (1 bit)

TEN1 : DAC channel1 trigger enable
bits : 1 - 1 (1 bit)

TSEL10 : TSEL10
bits : 2 - 2 (1 bit)

TSEL11 : TSEL11
bits : 3 - 3 (1 bit)

TSEL12 : TSEL12
bits : 4 - 4 (1 bit)

TSEL13 : DAC channel1 trigger selection
bits : 5 - 5 (1 bit)

WAVE1 : DAC channel1 noise/triangle wave generation enable
bits : 6 - 7 (2 bit)

MAMP1 : DAC channel1 mask/amplitude selector
bits : 8 - 11 (4 bit)

DMAEN1 : DAC channel1 DMA enable
bits : 12 - 12 (1 bit)

DMAUDRIE1 : DAC channel1 DMA Underrun Interrupt enable
bits : 13 - 13 (1 bit)

CEN1 : DAC Channel 1 calibration enable
bits : 14 - 14 (1 bit)


DHR8R1

channel1 8-bit right aligned data holding register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHR8R1 DHR8R1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR

DACC1DHR : DAC channel1 8-bit right-aligned data
bits : 0 - 7 (8 bit)


DHR12RD

Dual DAC 12-bit right-aligned data holding register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHR12RD DHR12RD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR

DACC1DHR : DAC channel1 12-bit right-aligned data
bits : 0 - 11 (12 bit)


DHR12LD

Dual DAC 12-bit left aligned data holding register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHR12LD DHR12LD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR

DACC1DHR : DAC channel1 12-bit left-aligned data
bits : 4 - 15 (12 bit)


DHR8RD

Dual DAC 8-bit right aligned data holding register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHR8RD DHR8RD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR

DACC1DHR : DAC channel1 8-bit right-aligned data
bits : 0 - 7 (8 bit)


DOR1

DAC channel1 data output register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DOR1 DOR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DOR

DACC1DOR : DACC1DOR
bits : 0 - 11 (12 bit)


SR

status register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAUDR1 CAL_FLAG1 BWST1

DMAUDR1 : DAC channel1 DMA underrun flag
bits : 13 - 13 (1 bit)
access : read-write

CAL_FLAG1 : DAC Channel 1 calibration offset status
bits : 14 - 14 (1 bit)
access : read-only

BWST1 : DAC Channel 1 busy writing sample time flag
bits : 15 - 15 (1 bit)
access : read-only


CCR

calibration control register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTRIM1

OTRIM1 : DAC Channel 1 offset trimming value
bits : 0 - 4 (5 bit)


MCR

mode control register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE1

MODE1 : DAC Channel 1 mode
bits : 0 - 2 (3 bit)


SWTRGR

software trigger register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWTRGR SWTRGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWTRIG1

SWTRIG1 : DAC channel1 software trigger
bits : 0 - 0 (1 bit)
access : write-only


SHSR1

Sample and Hold sample time register 1
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHSR1 SHSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSAMPLE1

TSAMPLE1 : DAC Channel 1 sample Time (only valid in Sample and Hold mode)
bits : 0 - 9 (10 bit)


SHHR

Sample and Hold hold time register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHHR SHHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THOLD1

THOLD1 : DAC Channel 1 hold Time (only valid in Sample and Hold mode)
bits : 0 - 9 (10 bit)


SHRR

Sample and Hold refresh time register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHRR SHRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TREFRESH1

TREFRESH1 : DAC Channel 1 refresh Time (only valid in Sample and Hold mode)
bits : 0 - 7 (8 bit)


DHR12R1

channel1 12-bit right-aligned data holding register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHR12R1 DHR12R1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR

DACC1DHR : DAC channel1 12-bit right-aligned data
bits : 0 - 11 (12 bit)


DHR12L1

channel1 12-bit left aligned data holding register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHR12L1 DHR12L1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR

DACC1DHR : DAC channel1 12-bit left-aligned data
bits : 4 - 15 (12 bit)



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