\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
rising trigger selection register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RT : Rising trigger event configuration bit of Configurable Event input
bits : 0 - 16 (17 bit)
RT21 : Rising trigger event configuration bit of Configurable Event input
bits : 21 - 22 (2 bit)
rising trigger selection register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RT34 : Rising trigger event configuration bit of Configurable Event input
bits : 2 - 2 (1 bit)
RT40 : Rising trigger event configuration bit of Configurable Event input
bits : 8 - 8 (1 bit)
RT41 : Rising trigger event configuration bit of Configurable Event input
bits : 9 - 9 (1 bit)
RT45 : Rising trigger event configuration bit of Configurable Event input
bits : 13 - 13 (1 bit)
falling trigger selection register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FT34 : Falling trigger event configuration bit of Configurable Event input
bits : 2 - 2 (1 bit)
FT40 : Falling trigger event configuration bit of Configurable Event input
bits : 8 - 8 (1 bit)
FT41 : Falling trigger event configuration bit of Configurable Event input
bits : 9 - 9 (1 bit)
FT45 : Falling trigger event configuration bit of Configurable Event input
bits : 13 - 13 (1 bit)
software interrupt event register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWI34 : Software interrupt on event
bits : 2 - 2 (1 bit)
SWI40 : Software interrupt on event
bits : 8 - 8 (1 bit)
SWI41 : Software interrupt on event
bits : 9 - 9 (1 bit)
SWI45 : Software interrupt on event 45
bits : 13 - 13 (1 bit)
pending register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIF34 : Configurable event inputs 33 Pending bit.
bits : 2 - 2 (1 bit)
PIF40 : Configurable event inputs 40_41 Pending bit.
bits : 8 - 8 (1 bit)
PIF41 : Configurable event inputs 40_41 Pending bit.
bits : 9 - 9 (1 bit)
PIF45 : Configurable event inputs 45 Pending bit.
bits : 13 - 13 (1 bit)
falling trigger selection register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FT : Falling trigger event configuration bit of Configurable Event input
bits : 0 - 16 (17 bit)
FT21 : Falling trigger event configuration bit of Configurable Event input
bits : 21 - 22 (2 bit)
software interrupt event register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWI : Software interrupt on event
bits : 0 - 16 (17 bit)
SWI21 : Software interrupt on event
bits : 21 - 22 (2 bit)
interrupt mask register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM : wakeup with interrupt Mask on event input
bits : 0 - 31 (32 bit)
event mask register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM0 : Wakeup with event generation Mask on Event input
bits : 0 - 0 (1 bit)
EM1 : Wakeup with event generation Mask on Event input
bits : 1 - 1 (1 bit)
EM2 : Wakeup with event generation Mask on Event input
bits : 2 - 2 (1 bit)
EM3 : Wakeup with event generation Mask on Event input
bits : 3 - 3 (1 bit)
EM4 : Wakeup with event generation Mask on Event input
bits : 4 - 4 (1 bit)
EM5 : Wakeup with event generation Mask on Event input
bits : 5 - 5 (1 bit)
EM6 : Wakeup with event generation Mask on Event input
bits : 6 - 6 (1 bit)
EM7 : Wakeup with event generation Mask on Event input
bits : 7 - 7 (1 bit)
EM8 : Wakeup with event generation Mask on Event input
bits : 8 - 8 (1 bit)
EM9 : Wakeup with event generation Mask on Event input
bits : 9 - 9 (1 bit)
EM10 : Wakeup with event generation Mask on Event input
bits : 10 - 10 (1 bit)
EM11 : Wakeup with event generation Mask on Event input
bits : 11 - 11 (1 bit)
EM12 : Wakeup with event generation Mask on Event input
bits : 12 - 12 (1 bit)
EM13 : Wakeup with event generation Mask on Event input
bits : 13 - 13 (1 bit)
EM14 : Wakeup with event generation Mask on Event input
bits : 14 - 14 (1 bit)
EM15 : Wakeup with event generation Mask on Event input
bits : 15 - 15 (1 bit)
EM17 : Wakeup with event generation Mask on Event input
bits : 17 - 17 (1 bit)
EM18 : Wakeup with event generation Mask on Event input
bits : 18 - 18 (1 bit)
EM19 : Wakeup with event generation Mask on Event input
bits : 19 - 19 (1 bit)
EM20 : Wakeup with event generation Mask on Event input
bits : 20 - 20 (1 bit)
EM21 : Wakeup with event generation Mask on Event input
bits : 21 - 21 (1 bit)
EM22 : Wakeup with event generation Mask on Event input
bits : 22 - 22 (1 bit)
wakeup with interrupt mask register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM34 : wakeup with interrupt mask on event input
bits : 2 - 2 (1 bit)
IM36 : wakeup with interrupt mask on event input
bits : 4 - 4 (1 bit)
IM37 : wakeup with interrupt mask on event input
bits : 5 - 5 (1 bit)
IM38 : wakeup with interrupt mask on event input
bits : 6 - 6 (1 bit)
IM39 : wakeup with interrupt mask on event input
bits : 7 - 7 (1 bit)
IM40 : wakeup with interrupt mask on event input
bits : 8 - 8 (1 bit)
IM41 : wakeup with interrupt mask on event input
bits : 9 - 9 (1 bit)
IM42 : wakeup with interrupt mask on event input
bits : 10 - 10 (1 bit)
IM43 : wakeup with interrupt mask on event input
bits : 11 - 11 (1 bit)
IM44 : wakeup with interrupt mask on event input
bits : 12 - 12 (1 bit)
IM45 : wakeup with interrupt mask on event input
bits : 13 - 13 (1 bit)
IM46 : wakeup with interrupt mask on event input
bits : 14 - 14 (1 bit)
wakeup with event mask register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM40 : Wakeup with event generation Mask on Event input
bits : 8 - 8 (1 bit)
EM41 : Wakeup with event generation Mask on Event input
bits : 9 - 9 (1 bit)
EXTI pending register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIF : Configurable event inputs Pending bit
bits : 0 - 16 (17 bit)
PIF21 : Configurable event inputs Pending bit
bits : 21 - 22 (2 bit)
interrupt mask register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM : wakeup with interrupt Mask on Event input
bits : 0 - 31 (32 bit)
event mask register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM0 : Wakeup with event generation Mask on Event input
bits : 0 - 0 (1 bit)
EM1 : Wakeup with event generation Mask on Event input
bits : 1 - 1 (1 bit)
EM2 : Wakeup with event generation Mask on Event input
bits : 2 - 2 (1 bit)
EM3 : Wakeup with event generation Mask on Event input
bits : 3 - 3 (1 bit)
EM4 : Wakeup with event generation Mask on Event input
bits : 4 - 4 (1 bit)
EM5 : Wakeup with event generation Mask on Event input
bits : 5 - 5 (1 bit)
EM6 : Wakeup with event generation Mask on Event input
bits : 6 - 6 (1 bit)
EM7 : Wakeup with event generation Mask on Event input
bits : 7 - 7 (1 bit)
EM8 : Wakeup with event generation Mask on Event input
bits : 8 - 8 (1 bit)
EM9 : Wakeup with event generation Mask on Event input
bits : 9 - 9 (1 bit)
EM10 : Wakeup with event generation Mask on Event input
bits : 10 - 10 (1 bit)
EM11 : Wakeup with event generation Mask on Event input
bits : 11 - 11 (1 bit)
EM12 : Wakeup with event generation Mask on Event input
bits : 12 - 12 (1 bit)
EM13 : Wakeup with event generation Mask on Event input
bits : 13 - 13 (1 bit)
EM14 : Wakeup with event generation Mask on Event input
bits : 14 - 14 (1 bit)
EM15 : Wakeup with event generation Mask on Event input
bits : 15 - 15 (1 bit)
EM17 : Wakeup with event generation Mask on Event input
bits : 17 - 17 (1 bit)
EM18 : Wakeup with event generation Mask on Event input
bits : 18 - 18 (1 bit)
EM19 : Wakeup with event generation Mask on Event input
bits : 19 - 19 (1 bit)
EM20 : Wakeup with event generation Mask on Event input
bits : 20 - 20 (1 bit)
EM21 : Wakeup with event generation Mask on Event input
bits : 21 - 21 (1 bit)
EM22 : Wakeup with event generation Mask on Event input
bits : 22 - 22 (1 bit)
wakeup with interrupt mask register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM34 : wakeup with interrupt mask on event input
bits : 2 - 2 (1 bit)
IM36 : wakeup with interrupt mask on event input
bits : 4 - 4 (1 bit)
IM37 : wakeup with interrupt mask on event input
bits : 5 - 5 (1 bit)
IM38 : wakeup with interrupt mask on event input
bits : 6 - 6 (1 bit)
IM39 : wakeup with interrupt mask on event input
bits : 7 - 7 (1 bit)
IM40 : wakeup with interrupt mask on event input
bits : 8 - 8 (1 bit)
IM41 : wakeup with interrupt mask on event input
bits : 9 - 9 (1 bit)
IM42 : wakeup with interrupt mask on event input
bits : 10 - 10 (1 bit)
IM43 : wakeup with interrupt mask on event input
bits : 11 - 11 (1 bit)
IM44 : wakeup with interrupt mask on event input
bits : 12 - 12 (1 bit)
IM45 : wakeup with interrupt mask on event input
bits : 13 - 13 (1 bit)
IM46 : wakeup with interrupt mask on event input
bits : 14 - 14 (1 bit)
wakeup with event mask register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM40 : Wakeup with event generation Mask on Event input
bits : 8 - 8 (1 bit)
EM41 : Wakeup with event generation Mask on Event input
bits : 9 - 9 (1 bit)
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