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HSEM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

HSEM_R0 (R0)

HSEM_R4 (R4)

HSEM_C1IER (C1IER)

HSEM_C1ICR (C1ICR)

HSEM_C1ISR (C1ISR)

HSEM_C1MISR (C1MISR)

HSEM_C2IER (C2IER)

HSEM_C2ICR (C2ICR)

HSEM_C2ISR (C2ISR)

HSEM_C2MISR (C2MISR)

HSEM_R5 (R5)

HSEM_CR (CR)

HSEM_KEYR (KEYR)

HSEM_R6 (R6)

HSEM_R7 (R7)

HSEM_R8 (R8)

HSEM_R9 (R9)

HSEM_R10 (R10)

HSEM_R11 (R11)

HSEM_R12 (R12)

HSEM_R13 (R13)

HSEM_R14 (R14)

HSEM_R15 (R15)

HSEM_R1 (R1)

HSEM_R2 (R2)

HSEM_RLR0 (RLR0)

HSEM_RLR1 (RLR1)

HSEM_RLR2 (RLR2)

HSEM_RLR3 (RLR3)

HSEM_RLR4 (RLR4)

HSEM_RLR5 (RLR5)

HSEM_RLR6 (RLR6)

HSEM_RLR7 (RLR7)

HSEM_RLR8 (RLR8)

HSEM_RLR9 (RLR9)

HSEM_RLR10 (RLR10)

HSEM_RLR11 (RLR11)

HSEM_RLR12 (RLR12)

HSEM_RLR13 (RLR13)

HSEM_RLR14 (RLR14)

HSEM_RLR15 (RLR15)

HSEM_R3 (R3)


HSEM_R0 (R0)

HSEM register HSEM_R0 HSEM_R31
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R0 HSEM_R0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_R4 (R4)

HSEM register HSEM_R0 HSEM_R31
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R4 HSEM_R4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_C1IER (C1IER)

HSEM Interrupt enable register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_C1IER HSEM_C1IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISE0 ISE1 ISE2 ISE3 ISE4 ISE5 ISE6 ISE7 ISE8 ISE9 ISE10 ISE11 ISE12 ISE13 ISE14 ISE15

ISE0 : Interrupt semaphore n enable bit
bits : 0 - 0 (1 bit)

ISE1 : Interrupt semaphore n enable bit
bits : 1 - 1 (1 bit)

ISE2 : Interrupt semaphore n enable bit
bits : 2 - 2 (1 bit)

ISE3 : Interrupt semaphore n enable bit
bits : 3 - 3 (1 bit)

ISE4 : Interrupt semaphore n enable bit
bits : 4 - 4 (1 bit)

ISE5 : Interrupt semaphore n enable bit
bits : 5 - 5 (1 bit)

ISE6 : Interrupt semaphore n enable bit
bits : 6 - 6 (1 bit)

ISE7 : Interrupt semaphore n enable bit
bits : 7 - 7 (1 bit)

ISE8 : Interrupt semaphore n enable bit
bits : 8 - 8 (1 bit)

ISE9 : Interrupt semaphore n enable bit
bits : 9 - 9 (1 bit)

ISE10 : Interrupt semaphore n enable bit
bits : 10 - 10 (1 bit)

ISE11 : Interrupt semaphore n enable bit
bits : 11 - 11 (1 bit)

ISE12 : Interrupt semaphore n enable bit
bits : 12 - 12 (1 bit)

ISE13 : Interrupt semaphore n enable bit
bits : 13 - 13 (1 bit)

ISE14 : Interrupt semaphore n enable bit
bits : 14 - 14 (1 bit)

ISE15 : Interrupt semaphore n enable bit
bits : 15 - 15 (1 bit)


HSEM_C1ICR (C1ICR)

HSEM Interrupt clear register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_C1ICR HSEM_C1ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISC0 ISC1 ISC2 ISC3 ISC4 ISC5 ISC6 ISC7 ISC8 ISC9 ISC10 ISC11 ISC12 ISC13 ISC14 ISC15

ISC0 : Interrupt(N) semaphore n clear bit
bits : 0 - 0 (1 bit)

ISC1 : Interrupt(N) semaphore n clear bit
bits : 1 - 1 (1 bit)

ISC2 : Interrupt(N) semaphore n clear bit
bits : 2 - 2 (1 bit)

ISC3 : Interrupt(N) semaphore n clear bit
bits : 3 - 3 (1 bit)

ISC4 : Interrupt(N) semaphore n clear bit
bits : 4 - 4 (1 bit)

ISC5 : Interrupt(N) semaphore n clear bit
bits : 5 - 5 (1 bit)

ISC6 : Interrupt(N) semaphore n clear bit
bits : 6 - 6 (1 bit)

ISC7 : Interrupt(N) semaphore n clear bit
bits : 7 - 7 (1 bit)

ISC8 : Interrupt(N) semaphore n clear bit
bits : 8 - 8 (1 bit)

ISC9 : Interrupt(N) semaphore n clear bit
bits : 9 - 9 (1 bit)

ISC10 : Interrupt(N) semaphore n clear bit
bits : 10 - 10 (1 bit)

ISC11 : Interrupt(N) semaphore n clear bit
bits : 11 - 11 (1 bit)

ISC12 : Interrupt(N) semaphore n clear bit
bits : 12 - 12 (1 bit)

ISC13 : Interrupt(N) semaphore n clear bit
bits : 13 - 13 (1 bit)

ISC14 : Interrupt(N) semaphore n clear bit
bits : 14 - 14 (1 bit)

ISC15 : Interrupt(N) semaphore n clear bit
bits : 15 - 15 (1 bit)


HSEM_C1ISR (C1ISR)

HSEM Interrupt status register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_C1ISR HSEM_C1ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISF0 ISF1 ISF2 ISF3 ISF4 ISF5 ISF6 ISF7 ISF8 ISF9 ISF10 ISF11 ISF12 ISF13 ISF14 ISF15

ISF0 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 0 - 0 (1 bit)

ISF1 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 1 - 1 (1 bit)

ISF2 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 2 - 2 (1 bit)

ISF3 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 3 - 3 (1 bit)

ISF4 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 4 - 4 (1 bit)

ISF5 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 5 - 5 (1 bit)

ISF6 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 6 - 6 (1 bit)

ISF7 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 7 - 7 (1 bit)

ISF8 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 8 - 8 (1 bit)

ISF9 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 9 - 9 (1 bit)

ISF10 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 10 - 10 (1 bit)

ISF11 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 11 - 11 (1 bit)

ISF12 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 12 - 12 (1 bit)

ISF13 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 13 - 13 (1 bit)

ISF14 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 14 - 14 (1 bit)

ISF15 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 15 - 15 (1 bit)


HSEM_C1MISR (C1MISR)

HSEM Masked interrupt status register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_C1MISR HSEM_C1MISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MISF0 MISF1 MISF2 MISF3 MISF4 MISF5 MISF6 MISF7 MISF8 MISF9 MISF10 MISF11 MISF12 MISF13 MISF14 MISF15

MISF0 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 0 - 0 (1 bit)

MISF1 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 1 - 1 (1 bit)

MISF2 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 2 - 2 (1 bit)

MISF3 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 3 - 3 (1 bit)

MISF4 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 4 - 4 (1 bit)

MISF5 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 5 - 5 (1 bit)

MISF6 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 6 - 6 (1 bit)

MISF7 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 7 - 7 (1 bit)

MISF8 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 8 - 8 (1 bit)

MISF9 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 9 - 9 (1 bit)

MISF10 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 10 - 10 (1 bit)

MISF11 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 11 - 11 (1 bit)

MISF12 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 12 - 12 (1 bit)

MISF13 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 13 - 13 (1 bit)

MISF14 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 14 - 14 (1 bit)

MISF15 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 15 - 15 (1 bit)


HSEM_C2IER (C2IER)

HSEM Interrupt enable register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_C2IER HSEM_C2IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISE0 ISE1 ISE2 ISE3 ISE4 ISE5 ISE6 ISE7 ISE8 ISE9 ISE10 ISE11 ISE12 ISE13 ISE14 ISE15

ISE0 : Interrupt semaphore n enable bit
bits : 0 - 0 (1 bit)

ISE1 : Interrupt semaphore n enable bit
bits : 1 - 1 (1 bit)

ISE2 : Interrupt semaphore n enable bit
bits : 2 - 2 (1 bit)

ISE3 : Interrupt semaphore n enable bit
bits : 3 - 3 (1 bit)

ISE4 : Interrupt semaphore n enable bit
bits : 4 - 4 (1 bit)

ISE5 : Interrupt semaphore n enable bit
bits : 5 - 5 (1 bit)

ISE6 : Interrupt semaphore n enable bit
bits : 6 - 6 (1 bit)

ISE7 : Interrupt semaphore n enable bit
bits : 7 - 7 (1 bit)

ISE8 : Interrupt semaphore n enable bit
bits : 8 - 8 (1 bit)

ISE9 : Interrupt semaphore n enable bit
bits : 9 - 9 (1 bit)

ISE10 : Interrupt semaphore n enable bit
bits : 10 - 10 (1 bit)

ISE11 : Interrupt semaphore n enable bit
bits : 11 - 11 (1 bit)

ISE12 : Interrupt semaphore n enable bit
bits : 12 - 12 (1 bit)

ISE13 : Interrupt semaphore n enable bit
bits : 13 - 13 (1 bit)

ISE14 : Interrupt semaphore n enable bit
bits : 14 - 14 (1 bit)

ISE15 : Interrupt semaphore n enable bit
bits : 15 - 15 (1 bit)


HSEM_C2ICR (C2ICR)

HSEM Interrupt clear register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_C2ICR HSEM_C2ICR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISC0 ISC1 ISC2 ISC3 ISC4 ISC5 ISC6 ISC7 ISC8 ISC9 ISC10 ISC11 ISC12 ISC13 ISC14 ISC15

ISC0 : Interrupt(N) semaphore n clear bit
bits : 0 - 0 (1 bit)

ISC1 : Interrupt(N) semaphore n clear bit
bits : 1 - 1 (1 bit)

ISC2 : Interrupt(N) semaphore n clear bit
bits : 2 - 2 (1 bit)

ISC3 : Interrupt(N) semaphore n clear bit
bits : 3 - 3 (1 bit)

ISC4 : Interrupt(N) semaphore n clear bit
bits : 4 - 4 (1 bit)

ISC5 : Interrupt(N) semaphore n clear bit
bits : 5 - 5 (1 bit)

ISC6 : Interrupt(N) semaphore n clear bit
bits : 6 - 6 (1 bit)

ISC7 : Interrupt(N) semaphore n clear bit
bits : 7 - 7 (1 bit)

ISC8 : Interrupt(N) semaphore n clear bit
bits : 8 - 8 (1 bit)

ISC9 : Interrupt(N) semaphore n clear bit
bits : 9 - 9 (1 bit)

ISC10 : Interrupt(N) semaphore n clear bit
bits : 10 - 10 (1 bit)

ISC11 : Interrupt(N) semaphore n clear bit
bits : 11 - 11 (1 bit)

ISC12 : Interrupt(N) semaphore n clear bit
bits : 12 - 12 (1 bit)

ISC13 : Interrupt(N) semaphore n clear bit
bits : 13 - 13 (1 bit)

ISC14 : Interrupt(N) semaphore n clear bit
bits : 14 - 14 (1 bit)

ISC15 : Interrupt(N) semaphore n clear bit
bits : 15 - 15 (1 bit)


HSEM_C2ISR (C2ISR)

HSEM Interrupt status register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_C2ISR HSEM_C2ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISF0 ISF1 ISF2 ISF3 ISF4 ISF5 ISF6 ISF7 ISF8 ISF9 ISF10 ISF11 ISF12 ISF13 ISF14 ISF15

ISF0 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 0 - 0 (1 bit)

ISF1 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 1 - 1 (1 bit)

ISF2 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 2 - 2 (1 bit)

ISF3 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 3 - 3 (1 bit)

ISF4 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 4 - 4 (1 bit)

ISF5 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 5 - 5 (1 bit)

ISF6 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 6 - 6 (1 bit)

ISF7 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 7 - 7 (1 bit)

ISF8 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 8 - 8 (1 bit)

ISF9 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 9 - 9 (1 bit)

ISF10 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 10 - 10 (1 bit)

ISF11 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 11 - 11 (1 bit)

ISF12 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 12 - 12 (1 bit)

ISF13 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 13 - 13 (1 bit)

ISF14 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 14 - 14 (1 bit)

ISF15 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 15 - 15 (1 bit)


HSEM_C2MISR (C2MISR)

HSEM Masked interrupt status register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_C2MISR HSEM_C2MISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MISF0 MISF1 MISF2 MISF3 MISF4 MISF5 MISF6 MISF7 MISF8 MISF9 MISF10 MISF11 MISF12 MISF13 MISF14 MISF15

MISF0 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 0 - 0 (1 bit)

MISF1 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 1 - 1 (1 bit)

MISF2 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 2 - 2 (1 bit)

MISF3 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 3 - 3 (1 bit)

MISF4 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 4 - 4 (1 bit)

MISF5 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 5 - 5 (1 bit)

MISF6 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 6 - 6 (1 bit)

MISF7 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 7 - 7 (1 bit)

MISF8 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 8 - 8 (1 bit)

MISF9 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 9 - 9 (1 bit)

MISF10 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 10 - 10 (1 bit)

MISF11 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 11 - 11 (1 bit)

MISF12 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 12 - 12 (1 bit)

MISF13 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 13 - 13 (1 bit)

MISF14 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 14 - 14 (1 bit)

MISF15 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 15 - 15 (1 bit)


HSEM_R5 (R5)

HSEM register HSEM_R0 HSEM_R31
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R5 HSEM_R5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_CR (CR)

HSEM Clear register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_CR HSEM_CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COREID KEY

COREID : COREID
bits : 8 - 11 (4 bit)

KEY : Semaphore clear Key
bits : 16 - 31 (16 bit)


HSEM_KEYR (KEYR)

HSEM Interrupt clear register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_KEYR HSEM_KEYR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : Semaphore Clear Key
bits : 16 - 31 (16 bit)


HSEM_R6 (R6)

HSEM register HSEM_R0 HSEM_R31
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R6 HSEM_R6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_R7 (R7)

HSEM register HSEM_R0 HSEM_R31
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R7 HSEM_R7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_R8 (R8)

HSEM register HSEM_R0 HSEM_R31
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R8 HSEM_R8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_R9 (R9)

HSEM register HSEM_R0 HSEM_R31
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R9 HSEM_R9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_R10 (R10)

HSEM register HSEM_R0 HSEM_R31
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R10 HSEM_R10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_R11 (R11)

HSEM register HSEM_R0 HSEM_R31
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R11 HSEM_R11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_R12 (R12)

HSEM register HSEM_R0 HSEM_R31
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R12 HSEM_R12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_R13 (R13)

HSEM register HSEM_R0 HSEM_R31
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R13 HSEM_R13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_R14 (R14)

HSEM register HSEM_R0 HSEM_R31
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R14 HSEM_R14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_R15 (R15)

HSEM register HSEM_R0 HSEM_R31
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R15 HSEM_R15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_R1 (R1)

HSEM register HSEM_R0 HSEM_R31
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R1 HSEM_R1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_R2 (R2)

HSEM register HSEM_R0 HSEM_R31
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R2 HSEM_R2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_RLR0 (RLR0)

HSEM Read lock register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR0 HSEM_RLR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_RLR1 (RLR1)

HSEM Read lock register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR1 HSEM_RLR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_RLR2 (RLR2)

HSEM Read lock register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR2 HSEM_RLR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_RLR3 (RLR3)

HSEM Read lock register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR3 HSEM_RLR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_RLR4 (RLR4)

HSEM Read lock register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR4 HSEM_RLR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_RLR5 (RLR5)

HSEM Read lock register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR5 HSEM_RLR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_RLR6 (RLR6)

HSEM Read lock register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR6 HSEM_RLR6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_RLR7 (RLR7)

HSEM Read lock register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR7 HSEM_RLR7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_RLR8 (RLR8)

HSEM Read lock register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR8 HSEM_RLR8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_RLR9 (RLR9)

HSEM Read lock register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR9 HSEM_RLR9 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_RLR10 (RLR10)

HSEM Read lock register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR10 HSEM_RLR10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_RLR11 (RLR11)

HSEM Read lock register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR11 HSEM_RLR11 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_RLR12 (RLR12)

HSEM Read lock register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR12 HSEM_RLR12 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_RLR13 (RLR13)

HSEM Read lock register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR13 HSEM_RLR13 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_RLR14 (RLR14)

HSEM Read lock register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR14 HSEM_RLR14 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_RLR15 (RLR15)

HSEM Read lock register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR15 HSEM_RLR15 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)


HSEM_R3 (R3)

HSEM register HSEM_R0 HSEM_R31
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R3 HSEM_R3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : Lock indication
bits : 31 - 31 (1 bit)



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