\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
HSEM register HSEM_R0 HSEM_R31
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM register HSEM_R0 HSEM_R31
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM Interrupt enable register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISE0 : Interrupt semaphore n enable bit
bits : 0 - 0 (1 bit)
ISE1 : Interrupt semaphore n enable bit
bits : 1 - 1 (1 bit)
ISE2 : Interrupt semaphore n enable bit
bits : 2 - 2 (1 bit)
ISE3 : Interrupt semaphore n enable bit
bits : 3 - 3 (1 bit)
ISE4 : Interrupt semaphore n enable bit
bits : 4 - 4 (1 bit)
ISE5 : Interrupt semaphore n enable bit
bits : 5 - 5 (1 bit)
ISE6 : Interrupt semaphore n enable bit
bits : 6 - 6 (1 bit)
ISE7 : Interrupt semaphore n enable bit
bits : 7 - 7 (1 bit)
ISE8 : Interrupt semaphore n enable bit
bits : 8 - 8 (1 bit)
ISE9 : Interrupt semaphore n enable bit
bits : 9 - 9 (1 bit)
ISE10 : Interrupt semaphore n enable bit
bits : 10 - 10 (1 bit)
ISE11 : Interrupt semaphore n enable bit
bits : 11 - 11 (1 bit)
ISE12 : Interrupt semaphore n enable bit
bits : 12 - 12 (1 bit)
ISE13 : Interrupt semaphore n enable bit
bits : 13 - 13 (1 bit)
ISE14 : Interrupt semaphore n enable bit
bits : 14 - 14 (1 bit)
ISE15 : Interrupt semaphore n enable bit
bits : 15 - 15 (1 bit)
HSEM Interrupt clear register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISC0 : Interrupt(N) semaphore n clear bit
bits : 0 - 0 (1 bit)
ISC1 : Interrupt(N) semaphore n clear bit
bits : 1 - 1 (1 bit)
ISC2 : Interrupt(N) semaphore n clear bit
bits : 2 - 2 (1 bit)
ISC3 : Interrupt(N) semaphore n clear bit
bits : 3 - 3 (1 bit)
ISC4 : Interrupt(N) semaphore n clear bit
bits : 4 - 4 (1 bit)
ISC5 : Interrupt(N) semaphore n clear bit
bits : 5 - 5 (1 bit)
ISC6 : Interrupt(N) semaphore n clear bit
bits : 6 - 6 (1 bit)
ISC7 : Interrupt(N) semaphore n clear bit
bits : 7 - 7 (1 bit)
ISC8 : Interrupt(N) semaphore n clear bit
bits : 8 - 8 (1 bit)
ISC9 : Interrupt(N) semaphore n clear bit
bits : 9 - 9 (1 bit)
ISC10 : Interrupt(N) semaphore n clear bit
bits : 10 - 10 (1 bit)
ISC11 : Interrupt(N) semaphore n clear bit
bits : 11 - 11 (1 bit)
ISC12 : Interrupt(N) semaphore n clear bit
bits : 12 - 12 (1 bit)
ISC13 : Interrupt(N) semaphore n clear bit
bits : 13 - 13 (1 bit)
ISC14 : Interrupt(N) semaphore n clear bit
bits : 14 - 14 (1 bit)
ISC15 : Interrupt(N) semaphore n clear bit
bits : 15 - 15 (1 bit)
HSEM Interrupt status register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ISF0 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 0 - 0 (1 bit)
ISF1 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 1 - 1 (1 bit)
ISF2 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 2 - 2 (1 bit)
ISF3 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 3 - 3 (1 bit)
ISF4 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 4 - 4 (1 bit)
ISF5 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 5 - 5 (1 bit)
ISF6 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 6 - 6 (1 bit)
ISF7 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 7 - 7 (1 bit)
ISF8 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 8 - 8 (1 bit)
ISF9 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 9 - 9 (1 bit)
ISF10 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 10 - 10 (1 bit)
ISF11 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 11 - 11 (1 bit)
ISF12 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 12 - 12 (1 bit)
ISF13 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 13 - 13 (1 bit)
ISF14 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 14 - 14 (1 bit)
ISF15 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 15 - 15 (1 bit)
HSEM Masked interrupt status register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MISF0 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 0 - 0 (1 bit)
MISF1 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 1 - 1 (1 bit)
MISF2 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 2 - 2 (1 bit)
MISF3 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 3 - 3 (1 bit)
MISF4 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 4 - 4 (1 bit)
MISF5 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 5 - 5 (1 bit)
MISF6 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 6 - 6 (1 bit)
MISF7 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 7 - 7 (1 bit)
MISF8 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 8 - 8 (1 bit)
MISF9 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 9 - 9 (1 bit)
MISF10 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 10 - 10 (1 bit)
MISF11 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 11 - 11 (1 bit)
MISF12 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 12 - 12 (1 bit)
MISF13 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 13 - 13 (1 bit)
MISF14 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 14 - 14 (1 bit)
MISF15 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 15 - 15 (1 bit)
HSEM Interrupt enable register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISE0 : Interrupt semaphore n enable bit
bits : 0 - 0 (1 bit)
ISE1 : Interrupt semaphore n enable bit
bits : 1 - 1 (1 bit)
ISE2 : Interrupt semaphore n enable bit
bits : 2 - 2 (1 bit)
ISE3 : Interrupt semaphore n enable bit
bits : 3 - 3 (1 bit)
ISE4 : Interrupt semaphore n enable bit
bits : 4 - 4 (1 bit)
ISE5 : Interrupt semaphore n enable bit
bits : 5 - 5 (1 bit)
ISE6 : Interrupt semaphore n enable bit
bits : 6 - 6 (1 bit)
ISE7 : Interrupt semaphore n enable bit
bits : 7 - 7 (1 bit)
ISE8 : Interrupt semaphore n enable bit
bits : 8 - 8 (1 bit)
ISE9 : Interrupt semaphore n enable bit
bits : 9 - 9 (1 bit)
ISE10 : Interrupt semaphore n enable bit
bits : 10 - 10 (1 bit)
ISE11 : Interrupt semaphore n enable bit
bits : 11 - 11 (1 bit)
ISE12 : Interrupt semaphore n enable bit
bits : 12 - 12 (1 bit)
ISE13 : Interrupt semaphore n enable bit
bits : 13 - 13 (1 bit)
ISE14 : Interrupt semaphore n enable bit
bits : 14 - 14 (1 bit)
ISE15 : Interrupt semaphore n enable bit
bits : 15 - 15 (1 bit)
HSEM Interrupt clear register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ISC0 : Interrupt(N) semaphore n clear bit
bits : 0 - 0 (1 bit)
ISC1 : Interrupt(N) semaphore n clear bit
bits : 1 - 1 (1 bit)
ISC2 : Interrupt(N) semaphore n clear bit
bits : 2 - 2 (1 bit)
ISC3 : Interrupt(N) semaphore n clear bit
bits : 3 - 3 (1 bit)
ISC4 : Interrupt(N) semaphore n clear bit
bits : 4 - 4 (1 bit)
ISC5 : Interrupt(N) semaphore n clear bit
bits : 5 - 5 (1 bit)
ISC6 : Interrupt(N) semaphore n clear bit
bits : 6 - 6 (1 bit)
ISC7 : Interrupt(N) semaphore n clear bit
bits : 7 - 7 (1 bit)
ISC8 : Interrupt(N) semaphore n clear bit
bits : 8 - 8 (1 bit)
ISC9 : Interrupt(N) semaphore n clear bit
bits : 9 - 9 (1 bit)
ISC10 : Interrupt(N) semaphore n clear bit
bits : 10 - 10 (1 bit)
ISC11 : Interrupt(N) semaphore n clear bit
bits : 11 - 11 (1 bit)
ISC12 : Interrupt(N) semaphore n clear bit
bits : 12 - 12 (1 bit)
ISC13 : Interrupt(N) semaphore n clear bit
bits : 13 - 13 (1 bit)
ISC14 : Interrupt(N) semaphore n clear bit
bits : 14 - 14 (1 bit)
ISC15 : Interrupt(N) semaphore n clear bit
bits : 15 - 15 (1 bit)
HSEM Interrupt status register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ISF0 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 0 - 0 (1 bit)
ISF1 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 1 - 1 (1 bit)
ISF2 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 2 - 2 (1 bit)
ISF3 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 3 - 3 (1 bit)
ISF4 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 4 - 4 (1 bit)
ISF5 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 5 - 5 (1 bit)
ISF6 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 6 - 6 (1 bit)
ISF7 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 7 - 7 (1 bit)
ISF8 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 8 - 8 (1 bit)
ISF9 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 9 - 9 (1 bit)
ISF10 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 10 - 10 (1 bit)
ISF11 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 11 - 11 (1 bit)
ISF12 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 12 - 12 (1 bit)
ISF13 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 13 - 13 (1 bit)
ISF14 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 14 - 14 (1 bit)
ISF15 : Interrupt(N) semaphore n status bit before enable (mask)
bits : 15 - 15 (1 bit)
HSEM Masked interrupt status register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MISF0 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 0 - 0 (1 bit)
MISF1 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 1 - 1 (1 bit)
MISF2 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 2 - 2 (1 bit)
MISF3 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 3 - 3 (1 bit)
MISF4 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 4 - 4 (1 bit)
MISF5 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 5 - 5 (1 bit)
MISF6 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 6 - 6 (1 bit)
MISF7 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 7 - 7 (1 bit)
MISF8 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 8 - 8 (1 bit)
MISF9 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 9 - 9 (1 bit)
MISF10 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 10 - 10 (1 bit)
MISF11 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 11 - 11 (1 bit)
MISF12 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 12 - 12 (1 bit)
MISF13 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 13 - 13 (1 bit)
MISF14 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 14 - 14 (1 bit)
MISF15 : masked interrupt(N) semaphore n status bit after enable (mask)
bits : 15 - 15 (1 bit)
HSEM register HSEM_R0 HSEM_R31
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM Clear register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COREID : COREID
bits : 8 - 11 (4 bit)
KEY : Semaphore clear Key
bits : 16 - 31 (16 bit)
HSEM Interrupt clear register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : Semaphore Clear Key
bits : 16 - 31 (16 bit)
HSEM register HSEM_R0 HSEM_R31
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM register HSEM_R0 HSEM_R31
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM register HSEM_R0 HSEM_R31
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM register HSEM_R0 HSEM_R31
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM register HSEM_R0 HSEM_R31
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM register HSEM_R0 HSEM_R31
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM register HSEM_R0 HSEM_R31
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM register HSEM_R0 HSEM_R31
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM register HSEM_R0 HSEM_R31
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM register HSEM_R0 HSEM_R31
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM register HSEM_R0 HSEM_R31
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM register HSEM_R0 HSEM_R31
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM Read lock register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM Read lock register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM Read lock register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM Read lock register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM Read lock register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM Read lock register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM Read lock register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM Read lock register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM Read lock register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM Read lock register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM Read lock register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM Read lock register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM Read lock register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM Read lock register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM Read lock register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM Read lock register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
HSEM register HSEM_R0 HSEM_R31
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROCID : Semaphore ProcessID
bits : 0 - 7 (8 bit)
COREID : COREID
bits : 8 - 11 (4 bit)
LOCK : Lock indication
bits : 31 - 31 (1 bit)
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