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IPCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

IPCC_C1CR (C1CR)

IPCC_C2CR (C2CR)

IPCC_C2MR (C2MR)

IPCC_C2SCR (C2SCR)

IPCC_C2TOC1SR (C2TOC1SR)

IPCC_HWCFGR (HWCFGR)

IPCC_VERR (VERR)

IPCC_IPIDR (IPIDR)

IPCC_SIDR (SIDR)

IPCC_C1MR (C1MR)

IPCC_C1SCR (C1SCR)

IPCC_C1TOC2SR (C1TOC2SR)


IPCC_C1CR (C1CR)

IPCC Processor 1 control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPCC_C1CR IPCC_C1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXOIE TXFIE

RXOIE : RXOIE
bits : 0 - 0 (1 bit)

TXFIE : TXFIE
bits : 16 - 16 (1 bit)


IPCC_C2CR (C2CR)

IPCC Processor 2 control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPCC_C2CR IPCC_C2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXOIE TXFIE

RXOIE : RXOIE
bits : 0 - 0 (1 bit)

TXFIE : TXFIE
bits : 16 - 16 (1 bit)


IPCC_C2MR (C2MR)

IPCC Processor 2 mask register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPCC_C2MR IPCC_C2MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1OM CH2OM CH3OM CH4OM CH5OM CH6OM CH1FM CH2FM CH3FM CH4FM CH5FM CH6FM

CH1OM : CH1OM
bits : 0 - 0 (1 bit)

CH2OM : CH2OM
bits : 1 - 1 (1 bit)

CH3OM : CH3OM
bits : 2 - 2 (1 bit)

CH4OM : CH4OM
bits : 3 - 3 (1 bit)

CH5OM : CH5OM
bits : 4 - 4 (1 bit)

CH6OM : CH6OM
bits : 5 - 5 (1 bit)

CH1FM : CH1FM
bits : 16 - 16 (1 bit)

CH2FM : CH2FM
bits : 17 - 17 (1 bit)

CH3FM : CH3FM
bits : 18 - 18 (1 bit)

CH4FM : CH4FM
bits : 19 - 19 (1 bit)

CH5FM : CH5FM
bits : 20 - 20 (1 bit)

CH6FM : CH6FM
bits : 21 - 21 (1 bit)


IPCC_C2SCR (C2SCR)

Reading this register will always return 0x0000 0000.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPCC_C2SCR IPCC_C2SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1C CH2C CH3C CH4C CH5C CH6C CH1S CH2S CH3S CH4S CH5S CH6S

CH1C : CH1C
bits : 0 - 0 (1 bit)

CH2C : CH2C
bits : 1 - 1 (1 bit)

CH3C : CH3C
bits : 2 - 2 (1 bit)

CH4C : CH4C
bits : 3 - 3 (1 bit)

CH5C : CH5C
bits : 4 - 4 (1 bit)

CH6C : CH6C
bits : 5 - 5 (1 bit)

CH1S : CH1S
bits : 16 - 16 (1 bit)

CH2S : CH2S
bits : 17 - 17 (1 bit)

CH3S : CH3S
bits : 18 - 18 (1 bit)

CH4S : CH4S
bits : 19 - 19 (1 bit)

CH5S : CH5S
bits : 20 - 20 (1 bit)

CH6S : CH6S
bits : 21 - 21 (1 bit)


IPCC_C2TOC1SR (C2TOC1SR)

IPCC processor 2 to processor 1 status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPCC_C2TOC1SR IPCC_C2TOC1SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1F CH2F CH3F CH4F CH5F CH6F

CH1F : CH1F
bits : 0 - 0 (1 bit)

CH2F : CH2F
bits : 1 - 1 (1 bit)

CH3F : CH3F
bits : 2 - 2 (1 bit)

CH4F : CH4F
bits : 3 - 3 (1 bit)

CH5F : CH5F
bits : 4 - 4 (1 bit)

CH6F : CH6F
bits : 5 - 5 (1 bit)


IPCC_HWCFGR (HWCFGR)

IPCC Hardware configuration register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPCC_HWCFGR IPCC_HWCFGR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNELS

CHANNELS : CHANNELS
bits : 0 - 7 (8 bit)


IPCC_VERR (VERR)

IPCC IP Version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPCC_VERR IPCC_VERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINREV MAJREV

MINREV : MINREV
bits : 0 - 3 (4 bit)

MAJREV : MAJREV
bits : 4 - 7 (4 bit)


IPCC_IPIDR (IPIDR)

IPCC IP Identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPCC_IPIDR IPCC_IPIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID

ID : ID
bits : 0 - 31 (32 bit)


IPCC_SIDR (SIDR)

IPCC Size ID register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPCC_SIDR IPCC_SIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SID

SID : SID
bits : 0 - 31 (32 bit)


IPCC_C1MR (C1MR)

IPCC Processor 1 mask register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPCC_C1MR IPCC_C1MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1OM CH2OM CH3OM CH4OM CH5OM CH6OM CH1FM CH2FM CH3FM CH4FM CH5FM CH6FM

CH1OM : CH1OM
bits : 0 - 0 (1 bit)

CH2OM : CH2OM
bits : 1 - 1 (1 bit)

CH3OM : CH3OM
bits : 2 - 2 (1 bit)

CH4OM : CH4OM
bits : 3 - 3 (1 bit)

CH5OM : CH5OM
bits : 4 - 4 (1 bit)

CH6OM : CH6OM
bits : 5 - 5 (1 bit)

CH1FM : CH1FM
bits : 16 - 16 (1 bit)

CH2FM : CH2FM
bits : 17 - 17 (1 bit)

CH3FM : CH3FM
bits : 18 - 18 (1 bit)

CH4FM : CH4FM
bits : 19 - 19 (1 bit)

CH5FM : CH5FM
bits : 20 - 20 (1 bit)

CH6FM : CH6FM
bits : 21 - 21 (1 bit)


IPCC_C1SCR (C1SCR)

Reading this register will always return 0x0000 0000.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPCC_C1SCR IPCC_C1SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1C CH2C CH3C CH4C CH5C CH6C CH1S CH2S CH3S CH4S CH5S CH6S

CH1C : CH1C
bits : 0 - 0 (1 bit)

CH2C : CH2C
bits : 1 - 1 (1 bit)

CH3C : CH3C
bits : 2 - 2 (1 bit)

CH4C : CH4C
bits : 3 - 3 (1 bit)

CH5C : CH5C
bits : 4 - 4 (1 bit)

CH6C : CH6C
bits : 5 - 5 (1 bit)

CH1S : CH1S
bits : 16 - 16 (1 bit)

CH2S : CH2S
bits : 17 - 17 (1 bit)

CH3S : CH3S
bits : 18 - 18 (1 bit)

CH4S : CH4S
bits : 19 - 19 (1 bit)

CH5S : CH5S
bits : 20 - 20 (1 bit)

CH6S : CH6S
bits : 21 - 21 (1 bit)


IPCC_C1TOC2SR (C1TOC2SR)

IPCC processor 1 to processor 2 status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPCC_C1TOC2SR IPCC_C1TOC2SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1F CH2F CH3F CH4F CH5F CH6F

CH1F : CH1F
bits : 0 - 0 (1 bit)

CH2F : CH2F
bits : 1 - 1 (1 bit)

CH3F : CH3F
bits : 2 - 2 (1 bit)

CH4F : CH4F
bits : 3 - 3 (1 bit)

CH5F : CH5F
bits : 4 - 4 (1 bit)

CH6F : CH6F
bits : 5 - 5 (1 bit)



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