\n
address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection :
memory remap register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEM_MODE : Memory mapping selection
bits : 0 - 2 (3 bit)
external interrupt configuration register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTI8 : EXTI 8 configuration bits
bits : 0 - 2 (3 bit)
EXTI9 : EXTI 9 configuration bits
bits : 4 - 6 (3 bit)
EXTI10 : EXTI 10 configuration bits
bits : 8 - 10 (3 bit)
EXTI11 : EXTI 11 configuration bits
bits : 12 - 14 (3 bit)
SYSCFG CPU1 interrupt mask register 1
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTCSTAMPTAMPLSECSSIM : RTCSTAMPTAMPLSECSSIM
bits : 0 - 0 (1 bit)
RTCSSRUIM : RTCSSRUIM
bits : 2 - 2 (1 bit)
EXTI5IM : EXTI5IM
bits : 21 - 21 (1 bit)
EXTI6IM : EXTI6IM
bits : 22 - 22 (1 bit)
EXTI7IM : EXTI7IM
bits : 23 - 23 (1 bit)
EXTI8IM : EXTI8IM
bits : 24 - 24 (1 bit)
EXTI9IM : EXTI9IM
bits : 25 - 25 (1 bit)
EXTI10IM : EXTI10IM
bits : 26 - 26 (1 bit)
EXTI11IM : EXTI11IM
bits : 27 - 27 (1 bit)
EXTI12IM : EXTI12IM
bits : 28 - 28 (1 bit)
EXTI13IM : EXTI13IM
bits : 29 - 29 (1 bit)
EXTI14IM : EXTI14IM
bits : 30 - 30 (1 bit)
EXTI15IM : EXTI15IM
bits : 31 - 31 (1 bit)
SYSCFG CPU1 interrupt mask register 2
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PVM3IM : PVM3IM
bits : 18 - 18 (1 bit)
PVDIM : PVDIM
bits : 20 - 20 (1 bit)
SYSCFG CPU2 interrupt mask register 1
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTCSTAMPTAMPLSECSSIM : RTCSTAMPTAMPLSECSSIM
bits : 0 - 0 (1 bit)
RTCALARMIM : RTCALARMIM
bits : 1 - 1 (1 bit)
RTCSSRUIM : RTCSSRUIM
bits : 2 - 2 (1 bit)
RTCWKUPIM : RTCWKUPIM
bits : 3 - 3 (1 bit)
RCCIM : RCCIM
bits : 5 - 5 (1 bit)
FLASHIM : FLASHIM
bits : 6 - 6 (1 bit)
PKAIM : PKAIM
bits : 8 - 8 (1 bit)
AESIM : AESIM
bits : 10 - 10 (1 bit)
COMPIM : COMPIM
bits : 11 - 11 (1 bit)
ADCIM : ADCIM
bits : 12 - 12 (1 bit)
DACIM : DACIM
bits : 13 - 13 (1 bit)
EXTI0IM : EXTI0IM
bits : 16 - 16 (1 bit)
EXTI1IM : EXTI1IM
bits : 17 - 17 (1 bit)
EXTI2IM : EXTI2IM
bits : 18 - 18 (1 bit)
EXTI3IM : EXTI3IM
bits : 19 - 19 (1 bit)
EXTI4IM : EXTI4IM
bits : 20 - 20 (1 bit)
EXTI5IM : EXTI5IM
bits : 21 - 21 (1 bit)
EXTI6IM : EXTI6IM
bits : 22 - 22 (1 bit)
EXTI7IM : EXTI7IM
bits : 23 - 23 (1 bit)
EXTI8IM : EXTI8IM
bits : 24 - 24 (1 bit)
EXTI9IM : EXTI9IM
bits : 25 - 25 (1 bit)
EXTI10IM : EXTI10IM
bits : 26 - 26 (1 bit)
EXTI11IM : EXTI11IM
bits : 27 - 27 (1 bit)
EXTI12IM : EXTI12IM
bits : 28 - 28 (1 bit)
EXTI13IM : EXTI13IM
bits : 29 - 29 (1 bit)
EXTI14IM : EXTI14IM
bits : 30 - 30 (1 bit)
EXTI15IM : EXTI15IM
bits : 31 - 31 (1 bit)
SYSCFG CPU2 interrupt mask register 2
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1CH1IM : DMA1CH1IM
bits : 0 - 0 (1 bit)
DMA1CH2IM : DMA1CH2IM
bits : 1 - 1 (1 bit)
DMA1CH3IM : DMA1CH3IM
bits : 2 - 2 (1 bit)
DMA1CH4IM : DMA1CH4IM
bits : 3 - 3 (1 bit)
DMA1CH5IM : DMA1CH5IM
bits : 4 - 4 (1 bit)
DMA1CH6IM : DMA1CH6IM
bits : 5 - 5 (1 bit)
DMA1CH7IM : DMA1CH7IM
bits : 6 - 6 (1 bit)
DMA2CH1IM : DMA2CH1IM
bits : 8 - 8 (1 bit)
DMA2CH2IM : DMA2CH2IM
bits : 9 - 9 (1 bit)
DMA2CH3IM : DMA2CH3IM
bits : 10 - 10 (1 bit)
DMA2CH4IM : DMA2CH4IM
bits : 11 - 11 (1 bit)
DMA2CH5IM : DMA2CH5IM
bits : 12 - 12 (1 bit)
DMA2CH6IM : DMA2CH6IM
bits : 13 - 13 (1 bit)
DMA2CH7IM : DMA2CH7IM
bits : 14 - 14 (1 bit)
DMAMUX1IM : DMAMUX1IM
bits : 15 - 15 (1 bit)
PVM3IM : PVM3IM
bits : 18 - 18 (1 bit)
PVDIM : PVDIM
bits : 20 - 20 (1 bit)
external interrupt configuration register 4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTI12 : EXTI12 configuration bits
bits : 0 - 2 (3 bit)
EXTI13 : EXTI13 configuration bits
bits : 4 - 6 (3 bit)
EXTI14 : EXTI14 configuration bits
bits : 8 - 10 (3 bit)
EXTI15 : EXTI15 configuration bits
bits : 12 - 14 (3 bit)
SCSR
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM2ER : SRAM2 erase
bits : 0 - 0 (1 bit)
access : read-write
SRAMBSY : SRAM1, SRAM2 and PKA SRAM busy by erase operation
bits : 1 - 1 (1 bit)
access : read-only
PKASRAMBSY : PKA SRAM busy by erase operation
bits : 8 - 8 (1 bit)
access : read-only
CFGR2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLL : CPU1 LOCKUP (Hardfault) output enable bit
bits : 0 - 0 (1 bit)
access : read-write
SPL : SRAM2 parity lock bit
bits : 1 - 1 (1 bit)
access : read-write
PVDL : PVD lock enable bit
bits : 2 - 2 (1 bit)
access : read-write
ECCL : ECC Lock
bits : 3 - 3 (1 bit)
access : read-write
SPF : SRAM2 parity error flag
bits : 8 - 8 (1 bit)
access : read-write
SWPR
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0WP : SRAM2 1Kbyte page 0 write protection
bits : 0 - 0 (1 bit)
P1WP : SRAM2 1Kbyte page 1 write protection
bits : 1 - 1 (1 bit)
P2WP : SRAM2 1Kbyte page 2 write protection
bits : 2 - 2 (1 bit)
P3WP : SRAM2 1Kbyte page 3 write protection
bits : 3 - 3 (1 bit)
P4WP : SRAM2 1Kbyte page 4 write protection
bits : 4 - 4 (1 bit)
P5WP : SRAM2 1Kbyte page 5 write protection
bits : 5 - 5 (1 bit)
P6WP : SRAM2 1Kbyte page 6 write protection
bits : 6 - 6 (1 bit)
P7WP : SRAM2 1Kbyte page 7 write protection
bits : 7 - 7 (1 bit)
P8WP : SRAM2 1Kbyte page 8 write protection
bits : 8 - 8 (1 bit)
P9WP : SRAM2 1Kbyte page 9 write protection
bits : 9 - 9 (1 bit)
P10WP : SRAM2 1Kbyte page 10 write protection
bits : 10 - 10 (1 bit)
P11WP : SRAM2 1Kbyte page 11 write protection
bits : 11 - 11 (1 bit)
P12WP : SRAM2 1Kbyte page 12 write protection
bits : 12 - 12 (1 bit)
P13WP : SRAM2 1Kbyte page 13 write protection
bits : 13 - 13 (1 bit)
P14WP : SRAM2 1Kbyte page 14 write protection
bits : 14 - 14 (1 bit)
P15WP : SRAM2 1Kbyte page 15 write protection
bits : 15 - 15 (1 bit)
P16WP : SRAM2 1Kbyte page 16 write protection
bits : 16 - 16 (1 bit)
P17WP : SRAM2 1Kbyte page 17 write protection
bits : 17 - 17 (1 bit)
P18WP : SRAM2 1Kbyte page 18 write protection
bits : 18 - 18 (1 bit)
P19WP : SRAM2 1Kbyte page 19 write protection
bits : 19 - 19 (1 bit)
P20WP : SRAM2 1Kbyte page 20 write protection
bits : 20 - 20 (1 bit)
P21WP : SRAM2 1Kbyte page 21 write protection
bits : 21 - 21 (1 bit)
P22WP : SRAM2 1Kbyte page 22 write protection
bits : 22 - 22 (1 bit)
P23WP : SRAM2 1Kbyte page 23 write protection
bits : 23 - 23 (1 bit)
P24WP : SRAM2 1Kbyte page 24 write protection
bits : 24 - 24 (1 bit)
P25WP : SRAM2 1Kbyte page 25 write protection
bits : 25 - 25 (1 bit)
P26WP : SRAM2 1Kbyte page 26 write protection
bits : 26 - 26 (1 bit)
P27WP : SRAM2 1Kbyte page 27 write protection
bits : 27 - 27 (1 bit)
P28WP : SRAM2 1Kbyte page 28 write protection
bits : 28 - 28 (1 bit)
P29WP : SRAM2 1Kbyte page 29 write protection
bits : 29 - 29 (1 bit)
P30WP : SRAM2 1Kbyte page 30 write protection
bits : 30 - 30 (1 bit)
P31WP : SRAM2 1Kbyte page 31 write protection
bits : 31 - 31 (1 bit)
radio debug control register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFTBSEL : radio debug test bus selection
bits : 0 - 0 (1 bit)
SKR
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : SRAM2 write protection key for software erase
bits : 0 - 7 (8 bit)
configuration register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOSTEN : I/O analog switch voltage booster enable
bits : 8 - 8 (1 bit)
I2C_PB6_FMP : Fast-mode Plus (Fm+) driving capability activation on PB6
bits : 16 - 16 (1 bit)
I2C_PB7_FMP : Fast-mode Plus (Fm+) driving capability activation on PB7
bits : 17 - 17 (1 bit)
I2C_PB8_FMP : Fast-mode Plus (Fm+) driving capability activation on PB8
bits : 18 - 18 (1 bit)
I2C_PB9_FMP : Fast-mode Plus (Fm+) driving capability activation on PB9
bits : 19 - 19 (1 bit)
I2C1_FMP : I2C1 Fast-mode Plus driving capability activation
bits : 20 - 20 (1 bit)
I2C2_FMP : I2C2 Fast-mode Plus driving capability activation
bits : 21 - 21 (1 bit)
I2C3_FMP : I2C3 Fast-mode Plus driving capability activation
bits : 22 - 22 (1 bit)
external interrupt configuration register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTI0 : EXTI 0 configuration bits
bits : 0 - 2 (3 bit)
EXTI1 : EXTI 1 configuration bits
bits : 4 - 6 (3 bit)
EXTI2 : EXTI 2 configuration bits
bits : 8 - 10 (3 bit)
EXTI3 : EXTI 3 configuration bits
bits : 12 - 14 (3 bit)
external interrupt configuration register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTI4 : EXTI 4 configuration bits
bits : 0 - 2 (3 bit)
EXTI5 : EXTI 5 configuration bits
bits : 4 - 6 (3 bit)
EXTI6 : EXTI 6 configuration bits
bits : 8 - 10 (3 bit)
EXTI7 : EXTI 7 configuration bits
bits : 12 - 14 (3 bit)
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