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TZSC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

IER1

MISR1

ICR1


IER1

TZIC interrupt enable register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER1 IER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TZICIE TZSCIE AESIE RNGIE SUBGHZSPIIE PWRIE FLASHIFIE DMA1IE DMA2IE DMAMUX1IE FLASHIE SRAM1IE SRAM2IE PKAIE

TZICIE : TZICIE
bits : 0 - 0 (1 bit)

TZSCIE : TZSCIE
bits : 1 - 1 (1 bit)

AESIE : AESIE
bits : 2 - 2 (1 bit)

RNGIE : RNGIE
bits : 3 - 3 (1 bit)

SUBGHZSPIIE : SUBGHZSPIIE
bits : 4 - 4 (1 bit)

PWRIE : PWRIE
bits : 5 - 5 (1 bit)

FLASHIFIE : FLASHIFIE
bits : 6 - 6 (1 bit)

DMA1IE : DMA1IE
bits : 7 - 7 (1 bit)

DMA2IE : DMA2IE
bits : 8 - 8 (1 bit)

DMAMUX1IE : DMAMUX1IE
bits : 9 - 9 (1 bit)

FLASHIE : FLASHIE
bits : 10 - 10 (1 bit)

SRAM1IE : SRAM1IE
bits : 11 - 11 (1 bit)

SRAM2IE : SRAM2IE
bits : 12 - 12 (1 bit)

PKAIE : PKAIE
bits : 13 - 13 (1 bit)


MISR1

TZIC status register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MISR1 MISR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TZICMF TZSCMF AESMF RNGMF SUBGHZSPIMF PWRMF FLASHIFMF DMA1MF DMA2MF DMAMUX1MF FLASHMF SRAM1MF SRAM2MF PKAMF

TZICMF : TZICMF
bits : 0 - 0 (1 bit)

TZSCMF : TZSCMF
bits : 1 - 1 (1 bit)

AESMF : AESMF
bits : 2 - 2 (1 bit)

RNGMF : RNGMF
bits : 3 - 3 (1 bit)

SUBGHZSPIMF : SUBGHZSPIMF
bits : 4 - 4 (1 bit)

PWRMF : PWRMF
bits : 5 - 5 (1 bit)

FLASHIFMF : FLASHIFMF
bits : 6 - 6 (1 bit)

DMA1MF : DMA1MF
bits : 7 - 7 (1 bit)

DMA2MF : DMA2MF
bits : 8 - 8 (1 bit)

DMAMUX1MF : DMAMUX1MF
bits : 9 - 9 (1 bit)

FLASHMF : FLASHMF
bits : 10 - 10 (1 bit)

SRAM1MF : SRAM1MF
bits : 11 - 11 (1 bit)

SRAM2MF : SRAM2MF
bits : 12 - 12 (1 bit)

PKAMF : PKAMF
bits : 13 - 13 (1 bit)


ICR1

TZIC interrupt status clear register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICR1 ICR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TZICCF TZSCCF AESCF RNGCF SUBGHZSPICF PWRCF FLASHIFCF DMA1CF DMA2CF DMAMUX1CF FLASHCF SRAM1CF SRAM2CF PKACF

TZICCF : TZICCF
bits : 0 - 0 (1 bit)

TZSCCF : TZSCCF
bits : 1 - 1 (1 bit)

AESCF : AESCF
bits : 2 - 2 (1 bit)

RNGCF : RNGCF
bits : 3 - 3 (1 bit)

SUBGHZSPICF : SUBGHZSPICF
bits : 4 - 4 (1 bit)

PWRCF : PWRCF
bits : 5 - 5 (1 bit)

FLASHIFCF : FLASHIFCF
bits : 6 - 6 (1 bit)

DMA1CF : DMA1CF
bits : 7 - 7 (1 bit)

DMA2CF : DMA2CF
bits : 8 - 8 (1 bit)

DMAMUX1CF : DMAMUX1CF
bits : 9 - 9 (1 bit)

FLASHCF : FLASHCF
bits : 10 - 10 (1 bit)

SRAM1CF : SRAM1CF
bits : 11 - 11 (1 bit)

SRAM2CF : SRAM2CF
bits : 12 - 12 (1 bit)

PKACF : PKACF
bits : 13 - 13 (1 bit)



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