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TZSC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

TZSC_CR (CR)

TZSC_SECCFGR1 (SECCFGR1)

TZSC_MPCWM1_UPWMR (MPCWM1_UPWMR)

TZSC_MPCWM1_UPWWMR (MPCWM1_UPWWMR)

TZSC_MPCWM2_UPWMR (MPCWM2_UPWMR)

TZSC_MPCWM3_UPWMR (MPCWM3_UPWMR)

TZSC_PRIVCFGR1 (PRIVCFGR1)


TZSC_CR (CR)

TZSC control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_CR TZSC_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCK

LCK : LCK
bits : 0 - 0 (1 bit)


TZSC_SECCFGR1 (SECCFGR1)

TZSC security configuration register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_SECCFGR1 TZSC_SECCFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AESSEC RNGSEC PKASEC

AESSEC : AESSEC
bits : 2 - 2 (1 bit)

RNGSEC : RNGSEC
bits : 3 - 3 (1 bit)

PKASEC : PKASEC
bits : 13 - 13 (1 bit)


TZSC_MPCWM1_UPWMR (MPCWM1_UPWMR)

Unprivileged Water Mark 1 register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM1_UPWMR TZSC_MPCWM1_UPWMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LGTH

LGTH : LGTH
bits : 16 - 27 (12 bit)


TZSC_MPCWM1_UPWWMR (MPCWM1_UPWWMR)

Unprivileged Writable Water Mark 1 register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM1_UPWWMR TZSC_MPCWM1_UPWWMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LGTH

LGTH : Define the length of Flash Unprivileged Writable area, in 2
bits : 16 - 27 (12 bit)


TZSC_MPCWM2_UPWMR (MPCWM2_UPWMR)

Unprivileged Water Mark 2 register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM2_UPWMR TZSC_MPCWM2_UPWMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LGTH

LGTH : LGTH
bits : 16 - 27 (12 bit)


TZSC_MPCWM3_UPWMR (MPCWM3_UPWMR)

Unprivileged Water Mark 3 register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_MPCWM3_UPWMR TZSC_MPCWM3_UPWMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LGTH

LGTH : LGTH
bits : 16 - 27 (12 bit)


TZSC_PRIVCFGR1 (PRIVCFGR1)

TZSC privilege configuration register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSC_PRIVCFGR1 TZSC_PRIVCFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AESPRIV RNGPRIV SUBGHZSPIPRIV PKAPRIV

AESPRIV : AESPRIV
bits : 2 - 2 (1 bit)

RNGPRIV : RNGPRIV
bits : 3 - 3 (1 bit)

SUBGHZSPIPRIV : SUBGHZSPIPRIV
bits : 4 - 4 (1 bit)

PKAPRIV : PKAPRIV
bits : 13 - 13 (1 bit)



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