\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN1 : DAC channel1 enable
bits : 0 - 0 (1 bit)
TEN1 : DAC channel1 trigger enable
bits : 1 - 1 (1 bit)
TSEL10 : TSEL10
bits : 2 - 2 (1 bit)
TSEL11 : TSEL11
bits : 3 - 3 (1 bit)
TSEL12 : TSEL12
bits : 4 - 4 (1 bit)
TSEL13 : DAC channel1 trigger selection
bits : 5 - 5 (1 bit)
WAVE1 : DAC channel1 noise/triangle wave generation enable
bits : 6 - 7 (2 bit)
MAMP1 : DAC channel1 mask/amplitude selector
bits : 8 - 11 (4 bit)
DMAEN1 : DAC channel1 DMA enable
bits : 12 - 12 (1 bit)
DMAUDRIE1 : DAC channel1 DMA Underrun Interrupt enable
bits : 13 - 13 (1 bit)
CEN1 : DAC Channel 1 calibration enable
bits : 14 - 14 (1 bit)
channel1 8-bit right aligned data holding register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 8-bit right-aligned data
bits : 0 - 7 (8 bit)
Dual DAC 12-bit right-aligned data holding register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 12-bit right-aligned data
bits : 0 - 11 (12 bit)
Dual DAC 12-bit left aligned data holding register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 12-bit left-aligned data
bits : 4 - 15 (12 bit)
Dual DAC 8-bit right aligned data holding register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 8-bit right-aligned data
bits : 0 - 7 (8 bit)
DAC channel1 data output register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DACC1DOR : DACC1DOR
bits : 0 - 11 (12 bit)
status register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAUDR1 : DAC channel1 DMA underrun flag
bits : 13 - 13 (1 bit)
access : read-write
CAL_FLAG1 : DAC Channel 1 calibration offset status
bits : 14 - 14 (1 bit)
access : read-only
BWST1 : DAC Channel 1 busy writing sample time flag
bits : 15 - 15 (1 bit)
access : read-only
calibration control register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OTRIM1 : DAC Channel 1 offset trimming value
bits : 0 - 4 (5 bit)
mode control register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE1 : DAC Channel 1 mode
bits : 0 - 2 (3 bit)
software trigger register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWTRIG1 : DAC channel1 software trigger
bits : 0 - 0 (1 bit)
access : write-only
Sample and Hold sample time register 1
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSAMPLE1 : DAC Channel 1 sample Time (only valid in Sample and Hold mode)
bits : 0 - 9 (10 bit)
Sample and Hold hold time register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THOLD1 : DAC Channel 1 hold Time (only valid in Sample and Hold mode)
bits : 0 - 9 (10 bit)
Sample and Hold refresh time register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TREFRESH1 : DAC Channel 1 refresh Time (only valid in Sample and Hold mode)
bits : 0 - 7 (8 bit)
channel1 12-bit right-aligned data holding register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 12-bit right-aligned data
bits : 0 - 11 (12 bit)
channel1 12-bit left aligned data holding register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DAC channel1 12-bit left-aligned data
bits : 4 - 15 (12 bit)
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