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RCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CR

EXTCFGR

C2AHB1ENR

C2AHB2ENR

C2AHB3ENR

C2APB1ENR1

C2APB1ENR2

C2APB2ENR

C2APB3ENR

C2AHB1SMENR

C2AHB2SMENR

C2AHB3SMENR

C2APB1SMENR1

C2APB1SMENR2

CIER

C2APB2SMENR

C2APB3SMENR

CIFR

CICR

AHB1RSTR

AHB2RSTR

AHB3RSTR

APB1RSTR1

APB1RSTR2

ICSCR

APB2RSTR

APB3RSTR

AHB1ENR

AHB2ENR

AHB3ENR

APB1ENR1

APB1ENR2

APB2ENR

APB3ENR

AHB1SMENR

AHB2SMENR

AHB3SMENR

APB1SMENR1

APB1SMENR2

CFGR

APB2SMENR

APB3SMENR

CCIPR

BDCR

CSR

PLLCFGR


CR

Clock control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSION MSIRDY MSIPLLEN MSIRGSEL MSIRANGE HSION HSIKERON HSIRDY HSIASFS HSIKERDY HSEON HSERDY CSSON HSEPRE HSEBYPPWR PLLON PLLRDY

MSION : MSI clock enable
bits : 0 - 0 (1 bit)
access : read-write

MSIRDY : MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready)
bits : 1 - 1 (1 bit)
access : read-only

MSIPLLEN : MSI clock PLL enable
bits : 2 - 2 (1 bit)
access : read-write

MSIRGSEL : MSI range control selection
bits : 3 - 3 (1 bit)
access : read-write

MSIRANGE : MSI clock ranges
bits : 4 - 7 (4 bit)
access : read-write

HSION : HSI16 clock enable
bits : 8 - 8 (1 bit)
access : read-write

HSIKERON : HSI16 always enable for peripheral kernel clocks.
bits : 9 - 9 (1 bit)
access : read-write

HSIRDY : HSI16 clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI16 is ready)
bits : 10 - 10 (1 bit)
access : read-only

HSIASFS : HSI16 automatic start from Stop
bits : 11 - 11 (1 bit)
access : read-write

HSIKERDY : HSI16 kernel clock ready flag for peripherals requests.
bits : 12 - 12 (1 bit)
access : read-only

HSEON : HSE32 clock enable
bits : 16 - 16 (1 bit)
access : read-write

HSERDY : HSE32 clock ready flag
bits : 17 - 17 (1 bit)
access : read-only

CSSON : HSE32 Clock security system enable
bits : 19 - 19 (1 bit)
access : read-write

HSEPRE : HSE32 sysclk prescaler
bits : 20 - 20 (1 bit)
access : read-write

HSEBYPPWR : Enable HSE32 VDDTCXO output on package pin PB0-VDDTCXO.
bits : 21 - 21 (1 bit)
access : read-write

PLLON : Main PLL enable
bits : 24 - 24 (1 bit)
access : read-write

PLLRDY : Main PLL clock ready flag
bits : 25 - 25 (1 bit)
access : read-only


EXTCFGR

Extended clock recovery register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTCFGR EXTCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHDHPRE C2HPRE SHDHPREF C2HPREF

SHDHPRE : HCLK3 shared prescaler (AHB3, Flash, and SRAM2)
bits : 0 - 3 (4 bit)
access : read-write

C2HPRE : [dual core device only] HCLK2 prescaler (CPU2)
bits : 4 - 7 (4 bit)
access : read-write

SHDHPREF : HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2)
bits : 16 - 16 (1 bit)
access : read-only

C2HPREF : CLK2 prescaler flag (CPU2)
bits : 17 - 17 (1 bit)
access : read-only


C2AHB1ENR

CPU2 AHB1 peripheral clock enable register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2AHB1ENR C2AHB1ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1EN DMA2EN DMAMUX1EN CRCEN

DMA1EN : CPU2 DMA1 clock enable
bits : 0 - 0 (1 bit)

DMA2EN : CPU2 DMA2 clock enable
bits : 1 - 1 (1 bit)

DMAMUX1EN : CPU2 DMAMUX1 clock enable
bits : 2 - 2 (1 bit)

CRCEN : CPU2 CRC clock enable
bits : 12 - 12 (1 bit)


C2AHB2ENR

CPU2 AHB2 peripheral clock enable register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2AHB2ENR C2AHB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOAEN GPIOBEN GPIOCEN GPIOHEN

GPIOAEN : CPU2 IO port A clock enable
bits : 0 - 0 (1 bit)

GPIOBEN : CPU2 IO port B clock enable
bits : 1 - 1 (1 bit)

GPIOCEN : CPU2 IO port C clock enable
bits : 2 - 2 (1 bit)

GPIOHEN : CPU2 IO port H clock enable
bits : 7 - 7 (1 bit)


C2AHB3ENR

CPU2 AHB3 peripheral clock enable register [dual core device only]
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2AHB3ENR C2AHB3ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKAEN AESEN RNGEN HSEMEN IPCCEN FLASHEN

PKAEN : CPU2 PKA accelerator clock enable
bits : 16 - 16 (1 bit)

AESEN : CPU2 AES accelerator clock enable
bits : 17 - 17 (1 bit)

RNGEN : CPU2 True RNG clocks enable
bits : 18 - 18 (1 bit)

HSEMEN : CPU2 HSEM clock enable
bits : 19 - 19 (1 bit)

IPCCEN : CPU2 IPCC interface clock enable
bits : 20 - 20 (1 bit)

FLASHEN : CPU2 Flash interface clock enable
bits : 25 - 25 (1 bit)


C2APB1ENR1

CPU2 APB1 peripheral clock enable register 1 [dual core device only]
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2APB1ENR1 C2APB1ENR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2EN RTCAPBEN SPI2S2EN USART2EN I2C1EN I2C2EN I2C3EN DAC1EN LPTIM1EN

TIM2EN : CPU2 TIM2 timer clock enable
bits : 0 - 0 (1 bit)

RTCAPBEN : CPU2 RTC APB clock enable
bits : 10 - 10 (1 bit)

SPI2S2EN : CPU2 SPI2S2 clock enable
bits : 14 - 14 (1 bit)

USART2EN : CPU2 USART2 clock enable
bits : 17 - 17 (1 bit)

I2C1EN : CPU2 I2C1 clocks enable
bits : 21 - 21 (1 bit)

I2C2EN : CPU2 I2C2 clocks enable
bits : 22 - 22 (1 bit)

I2C3EN : CPU2 I2C3 clocks enable
bits : 23 - 23 (1 bit)

DAC1EN : CPU2 DAC1 clock enable
bits : 29 - 29 (1 bit)

LPTIM1EN : CPU2 Low power timer 1 clocks enable
bits : 31 - 31 (1 bit)


C2APB1ENR2

CPU2 APB1 peripheral clock enable register 2 [dual core device only]
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2APB1ENR2 C2APB1ENR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPUART1EN LPTIM2EN LPTIM3EN

LPUART1EN : CPU2 Low power UART 1 clocks enable
bits : 0 - 0 (1 bit)

LPTIM2EN : CPU2 Low power timer 2 clocks enable
bits : 5 - 5 (1 bit)

LPTIM3EN : CPU2 Low power timer 3 clocks enable
bits : 6 - 6 (1 bit)


C2APB2ENR

CPU2 APB2 peripheral clock enable register [dual core device only]
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2APB2ENR C2APB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCEN TIM1EN SPI1EN USART1EN TIM16EN TIM17EN

ADCEN : ADC clocks enable
bits : 9 - 9 (1 bit)

TIM1EN : CPU2 TIM1 timer clock enable
bits : 11 - 11 (1 bit)

SPI1EN : CPU2 SPI1 clock enable
bits : 12 - 12 (1 bit)

USART1EN : CPU2 USART1clocks enable
bits : 14 - 14 (1 bit)

TIM16EN : CPU2 TIM16 timer clock enable
bits : 17 - 17 (1 bit)

TIM17EN : CPU2 TIM17 timer clock enable
bits : 18 - 18 (1 bit)


C2APB3ENR

CPU2 APB3 peripheral clock enable register [dual core device only]
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2APB3ENR C2APB3ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBGHZSPIEN

SUBGHZSPIEN : CPU2 sub-GHz radio SPI clock enable
bits : 0 - 0 (1 bit)


C2AHB1SMENR

CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only]
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2AHB1SMENR C2AHB1SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1SMEN DMA2SMEN DMAMUX1SMEN CRCSMEN

DMA1SMEN : DMA1 clock enable during CPU2 CSleep mode.
bits : 0 - 0 (1 bit)

DMA2SMEN : DMA2 clock enable during CPU2 CSleep mode.
bits : 1 - 1 (1 bit)

DMAMUX1SMEN : DMAMUX1 clock enable during CPU2 CSleep mode.
bits : 2 - 2 (1 bit)

CRCSMEN : CRC clock enable during CPU2 CSleep mode.
bits : 12 - 12 (1 bit)


C2AHB2SMENR

CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only]
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2AHB2SMENR C2AHB2SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOASMEN GPIOBSMEN GPIOCSMEN GPIOHSMEN

GPIOASMEN : IO port A clock enable during CPU2 CSleep mode.
bits : 0 - 0 (1 bit)

GPIOBSMEN : IO port B clock enable during CPU2 CSleep mode.
bits : 1 - 1 (1 bit)

GPIOCSMEN : IO port C clock enable during CPU2 CSleep mode.
bits : 2 - 2 (1 bit)

GPIOHSMEN : IO port H clock enable during CPU2 CSleep mode.
bits : 7 - 7 (1 bit)


C2AHB3SMENR

CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only]
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2AHB3SMENR C2AHB3SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKASMEN AESSMEN RNGSMEN SRAM1SMEN SRAM2SMEN FLASHSMEN

PKASMEN : PKA accelerator clock enable during CPU2 CSleep mode.
bits : 16 - 16 (1 bit)

AESSMEN : AES accelerator clock enable during CPU2 CSleep mode.
bits : 17 - 17 (1 bit)

RNGSMEN : True RNG clock enable during CPU2 CSleep and CStop mode.
bits : 18 - 18 (1 bit)

SRAM1SMEN : SRAM1 interface clock enable during CPU2 CSleep mode.
bits : 23 - 23 (1 bit)

SRAM2SMEN : SRAM2 memory interface clock enable during CPU2 CSleep mode.
bits : 24 - 24 (1 bit)

FLASHSMEN : Flash interface clock enable during CPU2 CSleep mode.
bits : 25 - 25 (1 bit)


C2APB1SMENR1

CPU2 APB1 peripheral clocks enable in Sleep mode register 1 [dual core device only]
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2APB1SMENR1 C2APB1SMENR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2SMEN RTCAPBSMEN SPI2S2SMEN USART2SMEN I2C1SMEN I2C2SMEN I2C3SMEN DAC1SMEN LPTIM1SMEN

TIM2SMEN : TIM2 timer clock enable during CPU2 CSleep mode.
bits : 0 - 0 (1 bit)

RTCAPBSMEN : RTC bus clock enable during CPU2 CSleep mode.
bits : 10 - 10 (1 bit)

SPI2S2SMEN : SPI2S2 clock enable during CPU2 CSleep mode.
bits : 14 - 14 (1 bit)

USART2SMEN : USART2 clock enable during CPU2 CSleep mode.
bits : 17 - 17 (1 bit)

I2C1SMEN : I2C1 clock enable during CPU2 CSleep and CStop modes
bits : 21 - 21 (1 bit)

I2C2SMEN : I2C2 clock enable during CPU2 CSleep and CStop modes
bits : 22 - 22 (1 bit)

I2C3SMEN : I2C3 clock enable during CPU2 CSleep and CStop modes
bits : 23 - 23 (1 bit)

DAC1SMEN : DAC1 clock enable during CPU2 CSleep mode.
bits : 29 - 29 (1 bit)

LPTIM1SMEN : Low power timer 1 clock enable during CPU2 CSleep and CStop mode
bits : 31 - 31 (1 bit)


C2APB1SMENR2

CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only]
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2APB1SMENR2 C2APB1SMENR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPUART1SMEN LPTIM2SMEN LPTIM3SMEN

LPUART1SMEN : Low power UART 1 clock enable during CPU2 CSleep and CStop mode
bits : 0 - 0 (1 bit)

LPTIM2SMEN : Low power timer 2 clocks enable during CPU2 CSleep and CStop modes.
bits : 5 - 5 (1 bit)

LPTIM3SMEN : Low power timer 3 clocks enable during CPU2 CSleep and CStop modes.
bits : 6 - 6 (1 bit)


CIER

Clock interrupt enable register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIER CIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYIE LSERDYIE MSIRDYIE HSIRDYIE HSERDYIE PLLRDYIE LSECSSIE

LSIRDYIE : LSI ready interrupt enable
bits : 0 - 0 (1 bit)

LSERDYIE : LSE ready interrupt enable
bits : 1 - 1 (1 bit)

MSIRDYIE : MSI ready interrupt enable
bits : 2 - 2 (1 bit)

HSIRDYIE : HSI16 ready interrupt enable
bits : 3 - 3 (1 bit)

HSERDYIE : HSE32 ready interrupt enable
bits : 4 - 4 (1 bit)

PLLRDYIE : PLL ready interrupt enable
bits : 5 - 5 (1 bit)

LSECSSIE : LSE clock security system interrupt enable
bits : 9 - 9 (1 bit)


C2APB2SMENR

CPU2 APB2 peripheral clocks enable in Sleep mode register [dual core device only]
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2APB2SMENR C2APB2SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCSMEN TIM1SMEN SPI1SMEN USART1SMEN TIM16SMEN TIM17SMEN

ADCSMEN : ADC clocks enable during CPU2 Csleep and CStop modes
bits : 9 - 9 (1 bit)

TIM1SMEN : TIM1 timer clock enable during CPU2 CSleep mode
bits : 11 - 11 (1 bit)

SPI1SMEN : SPI1 clock enable during CPU2 CSleep mode
bits : 12 - 12 (1 bit)

USART1SMEN : USART1clock enable during CPU2 CSleep and CStop mode
bits : 14 - 14 (1 bit)

TIM16SMEN : TIM16 timer clock enable during CPU2 CSleep mode
bits : 17 - 17 (1 bit)

TIM17SMEN : TIM17 timer clock enable during CPU2 CSleep mode
bits : 18 - 18 (1 bit)


C2APB3SMENR

CPU2 APB3 peripheral clock enable in Sleep mode register [dual core device only]
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2APB3SMENR C2APB3SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBGHZSPISMEN

SUBGHZSPISMEN : sub-GHz radio SPI clock enable during CPU2 CSleep and CStop modes
bits : 0 - 0 (1 bit)


CIFR

Clock interrupt flag register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIFR CIFR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYF LSERDYF MSIRDYF HSIRDYF HSERDYF PLLRDYF CSSF LSECSSF

LSIRDYF : LSI ready interrupt flag
bits : 0 - 0 (1 bit)

LSERDYF : LSE ready interrupt flag
bits : 1 - 1 (1 bit)

MSIRDYF : MSI ready interrupt flag
bits : 2 - 2 (1 bit)

HSIRDYF : HSI16 ready interrupt flag
bits : 3 - 3 (1 bit)

HSERDYF : HSE32 ready interrupt flag
bits : 4 - 4 (1 bit)

PLLRDYF : PLL ready interrupt flag
bits : 5 - 5 (1 bit)

CSSF : HSE32 Clock security system interrupt flag
bits : 8 - 8 (1 bit)

LSECSSF : LSE Clock security system interrupt flag
bits : 9 - 9 (1 bit)


CICR

Clock interrupt clear register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CICR CICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYC LSERDYC MSIRDYC HSIRDYC HSERDYC PLLRDYC CSSC LSECSSC

LSIRDYC : LSI ready interrupt clear
bits : 0 - 0 (1 bit)

LSERDYC : LSE ready interrupt clear
bits : 1 - 1 (1 bit)

MSIRDYC : MSI ready interrupt clear
bits : 2 - 2 (1 bit)

HSIRDYC : HSI16 ready interrupt clear
bits : 3 - 3 (1 bit)

HSERDYC : HSE32 ready interrupt clear
bits : 4 - 4 (1 bit)

PLLRDYC : PLL ready interrupt clear
bits : 5 - 5 (1 bit)

CSSC : HSE32 Clock security system interrupt clear
bits : 8 - 8 (1 bit)

LSECSSC : LSE Clock security system interrupt clear
bits : 9 - 9 (1 bit)


AHB1RSTR

AHB1 peripheral reset register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB1RSTR AHB1RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1RST DMA2RST DMAMUX1RST CRCRST

DMA1RST : DMA1 reset
bits : 0 - 0 (1 bit)

DMA2RST : DMA2 reset
bits : 1 - 1 (1 bit)

DMAMUX1RST : DMAMUX1 reset
bits : 2 - 2 (1 bit)

CRCRST : CRC reset
bits : 12 - 12 (1 bit)


AHB2RSTR

AHB2 peripheral reset register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB2RSTR AHB2RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOARST GPIOBRST GPIOCRST GPIOHRST

GPIOARST : IO port A reset
bits : 0 - 0 (1 bit)

GPIOBRST : IO port B reset
bits : 1 - 1 (1 bit)

GPIOCRST : IO port C reset
bits : 2 - 2 (1 bit)

GPIOHRST : IO port H reset
bits : 7 - 7 (1 bit)


AHB3RSTR

AHB3 peripheral reset register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB3RSTR AHB3RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKARST AESRST RNGRST HSEMRST IPCCRST FLASHRST

PKARST : PKARST
bits : 16 - 16 (1 bit)

AESRST : AESRST
bits : 17 - 17 (1 bit)

RNGRST : RNGRST
bits : 18 - 18 (1 bit)

HSEMRST : HSEMRST
bits : 19 - 19 (1 bit)

IPCCRST : IPCCRST
bits : 20 - 20 (1 bit)

FLASHRST : Flash interface reset
bits : 25 - 25 (1 bit)


APB1RSTR1

APB1 peripheral reset register 1
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1RSTR1 APB1RSTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2RST SPI2S2RST USART2RST I2C1RST I2C2RST I2C3RST DACRST LPTIM1RST

TIM2RST : TIM2 timer reset
bits : 0 - 0 (1 bit)

SPI2S2RST : SPI2S2 reset
bits : 14 - 14 (1 bit)

USART2RST : USART2 reset
bits : 17 - 17 (1 bit)

I2C1RST : I2C1 reset
bits : 21 - 21 (1 bit)

I2C2RST : I2C2 reset
bits : 22 - 22 (1 bit)

I2C3RST : I2C3 reset
bits : 23 - 23 (1 bit)

DACRST : DAC1 reset
bits : 29 - 29 (1 bit)

LPTIM1RST : Low Power Timer 1 reset
bits : 31 - 31 (1 bit)


APB1RSTR2

APB1 peripheral reset register 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1RSTR2 APB1RSTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPUART1RST LPTIM2RST LPTIM3RST

LPUART1RST : Low-power UART 1 reset
bits : 0 - 0 (1 bit)

LPTIM2RST : Low-power timer 2 reset
bits : 5 - 5 (1 bit)

LPTIM3RST : Low-power timer 3 reset
bits : 6 - 6 (1 bit)


ICSCR

Internal clock sources calibration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICSCR ICSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSICAL MSITRIM HSICAL HSITRIM

MSICAL : MSI clock calibration
bits : 0 - 7 (8 bit)
access : read-only

MSITRIM : MSI clock trimming
bits : 8 - 15 (8 bit)
access : read-write

HSICAL : HSI16 clock calibration
bits : 16 - 23 (8 bit)
access : read-only

HSITRIM : HSI16 clock trimming
bits : 24 - 30 (7 bit)
access : read-write


APB2RSTR

APB2 peripheral reset register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2RSTR APB2RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCRST TIM1RST SPI1RST USART1RST TIM16RST TIM17RST

ADCRST : ADC reset
bits : 9 - 9 (1 bit)

TIM1RST : TIM1 timer reset
bits : 11 - 11 (1 bit)

SPI1RST : SPI1 reset
bits : 12 - 12 (1 bit)

USART1RST : USART1 reset
bits : 14 - 14 (1 bit)

TIM16RST : TIM16 timer reset
bits : 17 - 17 (1 bit)

TIM17RST : TIM17 timer reset
bits : 18 - 18 (1 bit)


APB3RSTR

APB3 peripheral reset register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB3RSTR APB3RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBGHZSPIRST

SUBGHZSPIRST : Sub-GHz radio SPI reset
bits : 0 - 0 (1 bit)


AHB1ENR

AHB1 peripheral clock enable register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB1ENR AHB1ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1EN DMA2EN DMAMUX1EN CRCEN

DMA1EN : CPU1 DMA1 clock enable
bits : 0 - 0 (1 bit)

DMA2EN : CPU1 DMA2 clock enable
bits : 1 - 1 (1 bit)

DMAMUX1EN : CPU1 DMAMUX1 clock enable
bits : 2 - 2 (1 bit)

CRCEN : CPU1 CRC clock enable
bits : 12 - 12 (1 bit)


AHB2ENR

AHB2 peripheral clock enable register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB2ENR AHB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOAEN GPIOBEN GPIOCEN GPIOHEN

GPIOAEN : CPU1 IO port A clock enable
bits : 0 - 0 (1 bit)

GPIOBEN : CPU1 IO port B clock enable
bits : 1 - 1 (1 bit)

GPIOCEN : CPU1 IO port C clock enable
bits : 2 - 2 (1 bit)

GPIOHEN : CPU1 IO port H clock enable
bits : 7 - 7 (1 bit)


AHB3ENR

AHB3 peripheral clock enable register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB3ENR AHB3ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKAEN AESEN RNGEN HSEMEN IPCCEN FLASHEN

PKAEN : PKAEN
bits : 16 - 16 (1 bit)

AESEN : AESEN
bits : 17 - 17 (1 bit)

RNGEN : RNGEN
bits : 18 - 18 (1 bit)

HSEMEN : HSEMEN
bits : 19 - 19 (1 bit)

IPCCEN : IPCCEN
bits : 20 - 20 (1 bit)

FLASHEN : CPU1 Flash interface clock enable
bits : 25 - 25 (1 bit)


APB1ENR1

APB1 peripheral clock enable register 1
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1ENR1 APB1ENR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2EN RTCAPBEN WWDGEN SPI2S2EN USART2EN I2C1EN I2C2EN I2C3EN DAC1EN LPTIM1EN

TIM2EN : CPU1 TIM2 timer clock enable
bits : 0 - 0 (1 bit)
access : read-write

RTCAPBEN : CPU1 RTC APB clock enable
bits : 10 - 10 (1 bit)
access : read-write

WWDGEN : CPU1 Window watchdog clock enable
bits : 11 - 11 (1 bit)
access : read-write

SPI2S2EN : CPU1 SPI2S2 clock enable
bits : 14 - 14 (1 bit)
access : read-write

USART2EN : CPU1 USART2 clock enable
bits : 17 - 17 (1 bit)
access : read-write

I2C1EN : CPU1 I2C1 clocks enable
bits : 21 - 21 (1 bit)
access : read-write

I2C2EN : CPU1 I2C2 clocks enable
bits : 22 - 22 (1 bit)
access : read-write

I2C3EN : CPU1 I2C3 clocks enable
bits : 23 - 23 (1 bit)
access : read-write

DAC1EN : CPU1 DAC1 clock enable
bits : 29 - 29 (1 bit)
access : read-write

LPTIM1EN : CPU1 Low power timer 1 clocks enable
bits : 31 - 31 (1 bit)
access : read-write


APB1ENR2

APB1 peripheral clock enable register 2
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1ENR2 APB1ENR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPUART1EN LPTIM2EN LPTIM3EN

LPUART1EN : CPU1 Low power UART 1 clocks enable
bits : 0 - 0 (1 bit)

LPTIM2EN : CPU1 Low power timer 2 clocks enable
bits : 5 - 5 (1 bit)

LPTIM3EN : CPU1 Low power timer 3 clocks enable
bits : 6 - 6 (1 bit)


APB2ENR

APB2 peripheral clock enable register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2ENR APB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCEN TIM1EN SPI1EN USART1EN TIM16EN TIM17EN

ADCEN : CPU1 ADC clocks enable
bits : 9 - 9 (1 bit)

TIM1EN : CPU1 TIM1 timer clock enable
bits : 11 - 11 (1 bit)

SPI1EN : CPU1 SPI1 clock enable
bits : 12 - 12 (1 bit)

USART1EN : CPU1 USART1clocks enable
bits : 14 - 14 (1 bit)

TIM16EN : CPU1 TIM16 timer clock enable
bits : 17 - 17 (1 bit)

TIM17EN : CPU1 TIM17 timer clock enable
bits : 18 - 18 (1 bit)


APB3ENR

APB3 peripheral clock enable register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB3ENR APB3ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBGHZSPIEN

SUBGHZSPIEN : sub-GHz radio SPI clock enable
bits : 0 - 0 (1 bit)


AHB1SMENR

AHB1 peripheral clocks enable in Sleep modes register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB1SMENR AHB1SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1SMEN DMA2SMEN DMAMUX1SMEN CRCSMEN

DMA1SMEN : DMA1 clock enable during CPU1 CSleep mode.
bits : 0 - 0 (1 bit)

DMA2SMEN : DMA2 clock enable during CPU1 CSleep mode
bits : 1 - 1 (1 bit)

DMAMUX1SMEN : DMAMUX1 clock enable during CPU1 CSleep mode.
bits : 2 - 2 (1 bit)

CRCSMEN : CRC clock enable during CPU1 CSleep mode.
bits : 12 - 12 (1 bit)


AHB2SMENR

AHB2 peripheral clocks enable in Sleep modes register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB2SMENR AHB2SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOASMEN GPIOBSMEN GPIOCSMEN GPIOHSMEN

GPIOASMEN : IO port A clock enable during CPU1 CSleep mode.
bits : 0 - 0 (1 bit)

GPIOBSMEN : IO port B clock enable during CPU1 CSleep mode.
bits : 1 - 1 (1 bit)

GPIOCSMEN : IO port C clock enable during CPU1 CSleep mode.
bits : 2 - 2 (1 bit)

GPIOHSMEN : IO port H clock enable during CPU1 CSleep mode.
bits : 7 - 7 (1 bit)


AHB3SMENR

AHB3 peripheral clocks enable in Sleep and Stop modes register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB3SMENR AHB3SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKASMEN AESSMEN RNGSMEN SRAM1SMEN SRAM2SMEN FLASHSMEN

PKASMEN : PKA accelerator clock enable during CPU1 CSleep mode.
bits : 16 - 16 (1 bit)

AESSMEN : AES accelerator clock enable during CPU1 CSleep mode.
bits : 17 - 17 (1 bit)

RNGSMEN : True RNG clocks enable during CPU1 Csleep and CStop modes
bits : 18 - 18 (1 bit)

SRAM1SMEN : SRAM1 interface clock enable during CPU1 CSleep mode.
bits : 23 - 23 (1 bit)

SRAM2SMEN : SRAM2 memory interface clock enable during CPU1 CSleep mode
bits : 24 - 24 (1 bit)

FLASHSMEN : Flash interface clock enable during CPU1 CSleep mode.
bits : 25 - 25 (1 bit)


APB1SMENR1

APB1 peripheral clocks enable in Sleep mode register 1
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1SMENR1 APB1SMENR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2SMEN RTCAPBSMEN WWDGSMEN SPI2S2SMEN USART2SMEN I2C1SMEN I2C2SMEN I2C3SMEN DACSMEN LPTIM1SMEN

TIM2SMEN : TIM2 timer clock enable during CPU1 CSleep mode.
bits : 0 - 0 (1 bit)

RTCAPBSMEN : RTC bus clock enable during CPU1 CSleep mode.
bits : 10 - 10 (1 bit)

WWDGSMEN : Window watchdog clocks enable during CPU1 CSleep mode.
bits : 11 - 11 (1 bit)

SPI2S2SMEN : SPI2S2 clock enable during CPU1 CSleep mode.
bits : 14 - 14 (1 bit)

USART2SMEN : USART2 clock enable during CPU1 CSleep mode.
bits : 17 - 17 (1 bit)

I2C1SMEN : I2C1 clock enable during CPU1 Csleep and CStop modes
bits : 21 - 21 (1 bit)

I2C2SMEN : I2C2 clock enable during CPU1 Csleep and CStop modes
bits : 22 - 22 (1 bit)

I2C3SMEN : I2C3 clock enable during CPU1 Csleep and CStop modes
bits : 23 - 23 (1 bit)

DACSMEN : DAC1 clock enable during CPU1 CSleep mode.
bits : 29 - 29 (1 bit)

LPTIM1SMEN : Low power timer 1 clock enable during CPU1 Csleep and CStop mode
bits : 31 - 31 (1 bit)


APB1SMENR2

APB1 peripheral clocks enable in Sleep mode register 2
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1SMENR2 APB1SMENR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPUART1SMEN LPTIM2SMEN LPTIM3SMEN

LPUART1SMEN : Low power UART 1 clock enable during CPU1 Csleep and CStop modes.
bits : 0 - 0 (1 bit)

LPTIM2SMEN : Low power timer 2 clock enable during CPU1 Csleep and CStop modes
bits : 5 - 5 (1 bit)

LPTIM3SMEN : Low power timer 3 clock enable during CPU1 Csleep and CStop modes
bits : 6 - 6 (1 bit)


CFGR

Clock configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW SWS HPRE PPRE1 PPRE2 STOPWUCK HPREF PPRE1F PPRE2F MCOSEL MCOPRE

SW : System clock switch
bits : 0 - 1 (2 bit)
access : read-write

SWS : System clock switch status
bits : 2 - 3 (2 bit)
access : read-only

HPRE : HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.)
bits : 4 - 7 (4 bit)
access : read-write

PPRE1 : PCLK1 low-speed prescaler (APB1)
bits : 8 - 10 (3 bit)
access : read-write

PPRE2 : PCLK2 high-speed prescaler (APB2)
bits : 11 - 13 (3 bit)
access : read-write

STOPWUCK : Wakeup from Stop and CSS backup clock selection
bits : 15 - 15 (1 bit)
access : read-write

HPREF : HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1)
bits : 16 - 16 (1 bit)
access : read-only

PPRE1F : PCLK1 prescaler flag (APB1)
bits : 17 - 17 (1 bit)
access : read-only

PPRE2F : PCLK2 prescaler flag (APB2)
bits : 18 - 18 (1 bit)
access : read-only

MCOSEL : Microcontroller clock output
bits : 24 - 27 (4 bit)
access : read-write

MCOPRE : Microcontroller clock output prescaler
bits : 28 - 30 (3 bit)
access : read-write


APB2SMENR

APB2 peripheral clocks enable in Sleep mode register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2SMENR APB2SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCSMEN TIM1SMEN SPI1SMEN USART1SMEN TIM16SMEN TIM17SMEN

ADCSMEN : ADC clocks enable during CPU1 Csleep and CStop modes
bits : 9 - 9 (1 bit)

TIM1SMEN : TIM1 timer clock enable during CPU1 CSleep mode.
bits : 11 - 11 (1 bit)

SPI1SMEN : SPI1 clock enable during CPU1 CSleep mode.
bits : 12 - 12 (1 bit)

USART1SMEN : USART1 clock enable during CPU1 Csleep and CStop modes.
bits : 14 - 14 (1 bit)

TIM16SMEN : TIM16 timer clock enable during CPU1 CSleep mode.
bits : 17 - 17 (1 bit)

TIM17SMEN : TIM17 timer clock enable during CPU1 CSleep mode.
bits : 18 - 18 (1 bit)


APB3SMENR

APB3 peripheral clock enable in Sleep mode register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB3SMENR APB3SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBGHZSPISMEN

SUBGHZSPISMEN : Sub-GHz radio SPI clock enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)


CCIPR

Peripherals independent clock configuration register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCIPR CCIPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART1SEL USART2SEL SPI2S2SEL LPUART1SEL I2C1SEL I2C2SEL I2C3SEL LPTIM1SEL LPTIM2SEL LPTIM3SEL ADCSEL RNGSEL

USART1SEL : USART1 clock source selection
bits : 0 - 1 (2 bit)

USART2SEL : USART2 clock source selection
bits : 2 - 3 (2 bit)

SPI2S2SEL : SPI2S2 I2S clock source selection
bits : 8 - 9 (2 bit)

LPUART1SEL : LPUART1 clock source selection
bits : 10 - 11 (2 bit)

I2C1SEL : I2C1 clock source selection
bits : 12 - 13 (2 bit)

I2C2SEL : I2C2 clock source selection
bits : 14 - 15 (2 bit)

I2C3SEL : I2C3 clock source selection
bits : 16 - 17 (2 bit)

LPTIM1SEL : Low power timer 1 clock source selection
bits : 18 - 19 (2 bit)

LPTIM2SEL : Low power timer 2 clock source selection
bits : 20 - 21 (2 bit)

LPTIM3SEL : Low power timer 3 clock source selection
bits : 22 - 23 (2 bit)

ADCSEL : ADC clock source selection
bits : 28 - 29 (2 bit)

RNGSEL : RNG clock source selection
bits : 30 - 31 (2 bit)


BDCR

Backup domain control register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDCR BDCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSEON LSERDY LSEBYP LSEDRV LSECSSON LSECSSD LSESYSEN RTCSEL LSESYSRDY RTCEN BDRST LSCOEN LSCOSEL

LSEON : LSE oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSERDY : LSE oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

LSEBYP : LSE oscillator bypass
bits : 2 - 2 (1 bit)
access : read-write

LSEDRV : LSE oscillator drive capability
bits : 3 - 4 (2 bit)
access : read-write

LSECSSON : CSS on LSE enable
bits : 5 - 5 (1 bit)
access : read-write

LSECSSD : CSS on LSE failure Detection
bits : 6 - 6 (1 bit)
access : read-only

LSESYSEN : LSE system clock enable
bits : 7 - 7 (1 bit)
access : read-write

RTCSEL : RTC clock source selection
bits : 8 - 9 (2 bit)
access : read-write

LSESYSRDY : LSE system clock ready
bits : 11 - 11 (1 bit)
access : read-only

RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)
access : read-write

BDRST : Backup domain software reset
bits : 16 - 16 (1 bit)
access : read-write

LSCOEN : Low speed clock output enable
bits : 24 - 24 (1 bit)
access : read-write

LSCOSEL : Low speed clock output selection
bits : 25 - 25 (1 bit)
access : read-write


CSR

Control/status register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSION LSIRDY LSIPRE MSISRANGE RFRSTF RFRST RMVF RFILARSTF OBLRSTF PINRSTF BORRSTF SFTRSTF IWDGRSTF WWDGRSTF LPWRRSTF

LSION : LSI oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSIRDY : LSI oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

LSIPRE : LSI frequency prescaler
bits : 4 - 4 (1 bit)
access : read-write

MSISRANGE : MSI clock ranges
bits : 8 - 11 (4 bit)
access : read-write

RFRSTF : Radio in reset status flag
bits : 14 - 14 (1 bit)
access : read-only

RFRST : Radio reset
bits : 15 - 15 (1 bit)
access : read-write

RMVF : Remove reset flag
bits : 23 - 23 (1 bit)
access : read-write

RFILARSTF : Radio illegal access flag
bits : 24 - 24 (1 bit)
access : read-only

OBLRSTF : Option byte loader reset flag
bits : 25 - 25 (1 bit)
access : read-only

PINRSTF : Pin reset flag
bits : 26 - 26 (1 bit)
access : read-only

BORRSTF : BOR flag
bits : 27 - 27 (1 bit)
access : read-only

SFTRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-only

IWDGRSTF : Independent window watchdog reset flag
bits : 29 - 29 (1 bit)
access : read-only

WWDGRSTF : Window watchdog reset flag
bits : 30 - 30 (1 bit)
access : read-only

LPWRRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
access : read-only


PLLCFGR

PLL configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLCFGR PLLCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLSRC PLLM PLLN PLLPEN PLLP PLLQEN PLLQ PLLREN PLLR

PLLSRC : Main PLL entry clock source
bits : 0 - 1 (2 bit)

PLLM : Division factor for the main PLL input clock
bits : 4 - 6 (3 bit)

PLLN : Main PLL multiplication factor for VCO
bits : 8 - 14 (7 bit)

PLLPEN : Main PLL PLLPCLK output enable
bits : 16 - 16 (1 bit)

PLLP : Main PLL division factor for PLLPCLK.
bits : 17 - 21 (5 bit)

PLLQEN : Main PLL PLLQCLK output enable
bits : 24 - 24 (1 bit)

PLLQ : Main PLL division factor for PLLQCLK
bits : 25 - 27 (3 bit)

PLLREN : Main PLL PLLRCLK output enable
bits : 28 - 28 (1 bit)

PLLR : Main PLL division factor for PLLRCLK
bits : 29 - 31 (3 bit)



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