\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
TZSC_MPCWM1_UPWMR (MPCWM1_UPWMR)
TZSC_MPCWM1_UPWWMR (MPCWM1_UPWWMR)
TZSC_MPCWM2_UPWMR (MPCWM2_UPWMR)
TZSC_MPCWM3_UPWMR (MPCWM3_UPWMR)
TZSC control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCK : LCK
bits : 0 - 0 (1 bit)
TZSC security configuration register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AESSEC : AESSEC
bits : 2 - 2 (1 bit)
RNGSEC : RNGSEC
bits : 3 - 3 (1 bit)
PKASEC : PKASEC
bits : 13 - 13 (1 bit)
Unprivileged Water Mark 1 register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LGTH : LGTH
bits : 16 - 27 (12 bit)
Unprivileged Writable Water Mark 1 register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LGTH : Define the length of Flash Unprivileged Writable area, in 2
bits : 16 - 27 (12 bit)
Unprivileged Water Mark 2 register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LGTH : LGTH
bits : 16 - 27 (12 bit)
Unprivileged Water Mark 3 register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LGTH : LGTH
bits : 16 - 27 (12 bit)
TZSC privilege configuration register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AESPRIV : AESPRIV
bits : 2 - 2 (1 bit)
RNGPRIV : RNGPRIV
bits : 3 - 3 (1 bit)
SUBGHZSPIPRIV : SUBGHZSPIPRIV
bits : 4 - 4 (1 bit)
PKAPRIV : PKAPRIV
bits : 13 - 13 (1 bit)
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