\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
DBGMCU Identity Code Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEV_ID : Device ID
bits : 0 - 11 (12 bit)
REV_ID : Revision
bits : 16 - 31 (16 bit)
DBGMCU CPU1 APB1 Peripheral Freeze Register 1
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_TIM2_STOP : TIM2 stop in CPU1 debug
bits : 0 - 0 (1 bit)
DBG_RTC_STOP : RTC stop in CPU1 debug
bits : 10 - 10 (1 bit)
DBG_WWDG_STOP : WWDG stop in CPU1 debug
bits : 11 - 11 (1 bit)
DBG_IWDG_STOP : IWDG stop in CPU1 debug
bits : 12 - 12 (1 bit)
DBG_I2C1_STOP : I2C1 SMBUS timeout stop in CPU1 debug
bits : 21 - 21 (1 bit)
DBG_I2C2_STOP : I2C2 SMBUS timeout stop in CPU1 debug
bits : 22 - 22 (1 bit)
DBG_I2C3_STOP : I2C3 SMBUS timeout stop in CPU1 debug
bits : 23 - 23 (1 bit)
DBG_LPTIM1_STOP : LPTIM1 stop in CPU1 debug
bits : 31 - 31 (1 bit)
DBGMCU Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_SLEEP : Allow debug in SLEEP mode
bits : 0 - 0 (1 bit)
DBG_STOP : Allow debug in STOP mode
bits : 1 - 1 (1 bit)
DBG_STANDBY : Allow debug in STANDBY mode
bits : 2 - 2 (1 bit)
DBGMCU CPU1 APB1 Peripheral Freeze Register 2
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_LPTIM2_STOP : DBG_LPTIM2_STOP
bits : 5 - 5 (1 bit)
DBG_LPTIM3_STOP : DBG_LPTIM3_STOP
bits : 6 - 6 (1 bit)
DBGMCU CPU1 APB2 Peripheral Freeze Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_TIM1_STOP : DBG_TIM1_STOP
bits : 11 - 11 (1 bit)
DBG_TIM16_STOP : DBG_TIM16_STOP
bits : 17 - 17 (1 bit)
DBG_TIM17_STOP : DBG_TIM17_STOP
bits : 18 - 18 (1 bit)
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