\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
interrupt status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GIF1 : global interrupt flag for channel 1
bits : 0 - 0 (1 bit)
TCIF1 : transfer complete (TC) flag for channel 1
bits : 1 - 1 (1 bit)
HTIF1 : half transfer (HT) flag for channel 1
bits : 2 - 2 (1 bit)
TEIF1 : transfer error (TE) flag for channel 1
bits : 3 - 3 (1 bit)
GIF2 : global interrupt flag for channel 2
bits : 4 - 4 (1 bit)
TCIF2 : transfer complete (TC) flag for channel 2
bits : 5 - 5 (1 bit)
HTIF2 : half transfer (HT) flag for channel 2
bits : 6 - 6 (1 bit)
TEIF2 : transfer error (TE) flag for channel 2
bits : 7 - 7 (1 bit)
GIF3 : global interrupt flag for channel 3
bits : 8 - 8 (1 bit)
TCIF3 : transfer complete (TC) flag for channel 3
bits : 9 - 9 (1 bit)
HTIF3 : half transfer (HT) flag for channel 3
bits : 10 - 10 (1 bit)
TEIF3 : transfer error (TE) flag for channel 3
bits : 11 - 11 (1 bit)
GIF4 : global interrupt flag for channel 4
bits : 12 - 12 (1 bit)
TCIF4 : transfer complete (TC) flag for channel 4
bits : 13 - 13 (1 bit)
HTIF4 : half transfer (HT) flag for channel 4
bits : 14 - 14 (1 bit)
TEIF4 : transfer error (TE) flag for channel 4
bits : 15 - 15 (1 bit)
GIF5 : global interrupt flag for channel 5
bits : 16 - 16 (1 bit)
TCIF5 : transfer complete (TC) flag for channel 5
bits : 17 - 17 (1 bit)
HTIF5 : half transfer (HT) flag for channel 5
bits : 18 - 18 (1 bit)
TEIF5 : transfer error (TE) flag for channel 5
bits : 19 - 19 (1 bit)
GIF6 : global interrupt flag for channel 6
bits : 20 - 20 (1 bit)
TCIF6 : transfer complete (TC) flag for channel 6
bits : 21 - 21 (1 bit)
HTIF6 : half transfer (HT) flag for channel 6
bits : 22 - 22 (1 bit)
TEIF6 : transfer error (TE) flag for channel 6
bits : 23 - 23 (1 bit)
GIF7 : global interrupt flag for channel 7
bits : 24 - 24 (1 bit)
TCIF7 : transfer complete (TC) flag for channel 7
bits : 25 - 25 (1 bit)
HTIF7 : half transfer (HT) flag for channel 7
bits : 26 - 26 (1 bit)
TEIF7 : transfer error (TE) flag for channel 7
bits : 27 - 27 (1 bit)
channel x peripheral address register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : peripheral address
bits : 0 - 31 (32 bit)
channel x memory address register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : peripheral address
bits : 0 - 31 (32 bit)
channel x configuration register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
TCIE : transfer complete interrupt enable
bits : 1 - 1 (1 bit)
HTIE : half transfer interrupt enable
bits : 2 - 2 (1 bit)
TEIE : transfer error interrupt enable
bits : 3 - 3 (1 bit)
DIR : data transfer direction
bits : 4 - 4 (1 bit)
CIRC : circular mode
bits : 5 - 5 (1 bit)
PINC : peripheral increment mode
bits : 6 - 6 (1 bit)
MINC : memory increment mode
bits : 7 - 7 (1 bit)
PSIZE : peripheral size
bits : 8 - 9 (2 bit)
MSIZE : memory size
bits : 10 - 11 (2 bit)
PL : priority level
bits : 12 - 13 (2 bit)
MEM2MEM : memory-to-memory mode
bits : 14 - 14 (1 bit)
SECM : ecure mode
bits : 17 - 17 (1 bit)
SSEC : ecurity of the DMA transfer from the source
bits : 18 - 18 (1 bit)
DSEC : ecurity of the DMA transfer to the destination
bits : 19 - 19 (1 bit)
PRIV : rivileged mode
bits : 20 - 20 (1 bit)
channel x number of data to transfer register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : number of data to transfer (0 to 218 - 1)
bits : 0 - 17 (18 bit)
channel x peripheral address register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : peripheral address
bits : 0 - 31 (32 bit)
channel x memory address register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : peripheral address
bits : 0 - 31 (32 bit)
channel x configuration register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
TCIE : transfer complete interrupt enable
bits : 1 - 1 (1 bit)
HTIE : half transfer interrupt enable
bits : 2 - 2 (1 bit)
TEIE : transfer error interrupt enable
bits : 3 - 3 (1 bit)
DIR : data transfer direction
bits : 4 - 4 (1 bit)
CIRC : circular mode
bits : 5 - 5 (1 bit)
PINC : peripheral increment mode
bits : 6 - 6 (1 bit)
MINC : memory increment mode
bits : 7 - 7 (1 bit)
PSIZE : peripheral size
bits : 8 - 9 (2 bit)
MSIZE : memory size
bits : 10 - 11 (2 bit)
PL : priority level
bits : 12 - 13 (2 bit)
MEM2MEM : memory-to-memory mode
bits : 14 - 14 (1 bit)
SECM : ecure mode
bits : 17 - 17 (1 bit)
SSEC : ecurity of the DMA transfer from the source
bits : 18 - 18 (1 bit)
DSEC : ecurity of the DMA transfer to the destination
bits : 19 - 19 (1 bit)
PRIV : rivileged mode
bits : 20 - 20 (1 bit)
channel x number of data to transfer register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : number of data to transfer (0 to 218 - 1)
bits : 0 - 17 (18 bit)
channel x peripheral address register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : peripheral address
bits : 0 - 31 (32 bit)
channel x memory address register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : peripheral address
bits : 0 - 31 (32 bit)
interrupt flag clear register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
GIF1 : global interrupt flag clear for channel 1
bits : 0 - 0 (1 bit)
TCIF1 : transfer complete flag clear for channel 1
bits : 1 - 1 (1 bit)
HTIF1 : half transfer flag clear for channel 1
bits : 2 - 2 (1 bit)
TEIF1 : transfer error flag clear for channel 1
bits : 3 - 3 (1 bit)
GIF2 : global interrupt flag clear for channel 2
bits : 4 - 4 (1 bit)
TCIF2 : transfer complete flag clear for channel 2
bits : 5 - 5 (1 bit)
HTIF2 : half transfer flag clear for channel 2
bits : 6 - 6 (1 bit)
TEIF2 : transfer error flag clear for channel 2
bits : 7 - 7 (1 bit)
GIF3 : global interrupt flag clear for channel 3
bits : 8 - 8 (1 bit)
TCIF3 : transfer complete flag clear for channel 3
bits : 9 - 9 (1 bit)
HTIF3 : half transfer flag clear for channel 3
bits : 10 - 10 (1 bit)
TEIF3 : transfer error flag clear for channel 3
bits : 11 - 11 (1 bit)
GIF4 : global interrupt flag clear for channel 4
bits : 12 - 12 (1 bit)
TCIF4 : transfer complete flag clear for channel 4
bits : 13 - 13 (1 bit)
HTIF4 : half transfer flag clear for channel 4
bits : 14 - 14 (1 bit)
TEIF4 : transfer error flag clear for channel 4
bits : 15 - 15 (1 bit)
GIF5 : global interrupt flag clear for channel 5
bits : 16 - 16 (1 bit)
TCIF5 : transfer complete flag clear for channel 5
bits : 17 - 17 (1 bit)
HTIF5 : half transfer flag clear for channel 5
bits : 18 - 18 (1 bit)
TEIF5 : transfer error flag clear for channel 5
bits : 19 - 19 (1 bit)
GIF6 : global interrupt flag clear for channel 6
bits : 20 - 20 (1 bit)
TCIF6 : transfer complete flag clear for channel 6
bits : 21 - 21 (1 bit)
HTIF6 : half transfer flag clear for channel 6
bits : 22 - 22 (1 bit)
TEIF6 : transfer error flag clear for channel 6
bits : 23 - 23 (1 bit)
GIF7 : global interrupt flag clear for channel 7
bits : 24 - 24 (1 bit)
TCIF7 : transfer complete flag clear for channel 7
bits : 25 - 25 (1 bit)
HTIF7 : half transfer flag clear for channel 7
bits : 26 - 26 (1 bit)
TEIF7 : transfer error flag clear for channel 7
bits : 27 - 27 (1 bit)
channel x configuration register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
TCIE : transfer complete interrupt enable
bits : 1 - 1 (1 bit)
HTIE : half transfer interrupt enable
bits : 2 - 2 (1 bit)
TEIE : transfer error interrupt enable
bits : 3 - 3 (1 bit)
DIR : data transfer direction
bits : 4 - 4 (1 bit)
CIRC : circular mode
bits : 5 - 5 (1 bit)
PINC : peripheral increment mode
bits : 6 - 6 (1 bit)
MINC : memory increment mode
bits : 7 - 7 (1 bit)
PSIZE : peripheral size
bits : 8 - 9 (2 bit)
MSIZE : memory size
bits : 10 - 11 (2 bit)
PL : priority level
bits : 12 - 13 (2 bit)
MEM2MEM : memory-to-memory mode
bits : 14 - 14 (1 bit)
SECM : ecure mode
bits : 17 - 17 (1 bit)
SSEC : ecurity of the DMA transfer from the source
bits : 18 - 18 (1 bit)
DSEC : ecurity of the DMA transfer to the destination
bits : 19 - 19 (1 bit)
PRIV : rivileged mode
bits : 20 - 20 (1 bit)
channel x number of data to transfer register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : number of data to transfer (0 to 218 - 1)
bits : 0 - 17 (18 bit)
channel x peripheral address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : peripheral address
bits : 0 - 31 (32 bit)
channel x memory address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : peripheral address
bits : 0 - 31 (32 bit)
channel x configuration register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
TCIE : transfer complete interrupt enable
bits : 1 - 1 (1 bit)
HTIE : half transfer interrupt enable
bits : 2 - 2 (1 bit)
TEIE : transfer error interrupt enable
bits : 3 - 3 (1 bit)
DIR : data transfer direction
bits : 4 - 4 (1 bit)
CIRC : circular mode
bits : 5 - 5 (1 bit)
PINC : peripheral increment mode
bits : 6 - 6 (1 bit)
MINC : memory increment mode
bits : 7 - 7 (1 bit)
PSIZE : peripheral size
bits : 8 - 9 (2 bit)
MSIZE : memory size
bits : 10 - 11 (2 bit)
PL : priority level
bits : 12 - 13 (2 bit)
MEM2MEM : memory-to-memory mode
bits : 14 - 14 (1 bit)
SECM : ecure mode
bits : 17 - 17 (1 bit)
SSEC : ecurity of the DMA transfer from the source
bits : 18 - 18 (1 bit)
DSEC : ecurity of the DMA transfer to the destination
bits : 19 - 19 (1 bit)
PRIV : rivileged mode
bits : 20 - 20 (1 bit)
channel x number of data to transfer register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : number of data to transfer (0 to 218 - 1)
bits : 0 - 17 (18 bit)
channel x peripheral address register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : peripheral address
bits : 0 - 31 (32 bit)
channel x memory address register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : peripheral address
bits : 0 - 31 (32 bit)
channel x configuration register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
TCIE : transfer complete interrupt enable
bits : 1 - 1 (1 bit)
HTIE : half transfer interrupt enable
bits : 2 - 2 (1 bit)
TEIE : transfer error interrupt enable
bits : 3 - 3 (1 bit)
DIR : data transfer direction
bits : 4 - 4 (1 bit)
CIRC : circular mode
bits : 5 - 5 (1 bit)
PINC : peripheral increment mode
bits : 6 - 6 (1 bit)
MINC : memory increment mode
bits : 7 - 7 (1 bit)
PSIZE : peripheral size
bits : 8 - 9 (2 bit)
MSIZE : memory size
bits : 10 - 11 (2 bit)
PL : priority level
bits : 12 - 13 (2 bit)
MEM2MEM : memory-to-memory mode
bits : 14 - 14 (1 bit)
SECM : ecure mode
bits : 17 - 17 (1 bit)
SSEC : ecurity of the DMA transfer from the source
bits : 18 - 18 (1 bit)
DSEC : ecurity of the DMA transfer to the destination
bits : 19 - 19 (1 bit)
PRIV : rivileged mode
bits : 20 - 20 (1 bit)
channel x number of data to transfer register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : number of data to transfer (0 to 218 - 1)
bits : 0 - 17 (18 bit)
channel x peripheral address register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : peripheral address
bits : 0 - 31 (32 bit)
channel x memory address register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : peripheral address
bits : 0 - 31 (32 bit)
channel x configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
TCIE : transfer complete interrupt enable
bits : 1 - 1 (1 bit)
HTIE : half transfer interrupt enable
bits : 2 - 2 (1 bit)
TEIE : transfer error interrupt enable
bits : 3 - 3 (1 bit)
DIR : data transfer direction
bits : 4 - 4 (1 bit)
CIRC : circular mode
bits : 5 - 5 (1 bit)
PINC : peripheral increment mode
bits : 6 - 6 (1 bit)
MINC : memory increment mode
bits : 7 - 7 (1 bit)
PSIZE : peripheral size
bits : 8 - 9 (2 bit)
MSIZE : memory size
bits : 10 - 11 (2 bit)
PL : priority level
bits : 12 - 13 (2 bit)
MEM2MEM : memory-to-memory mode
bits : 14 - 14 (1 bit)
SECM : ecure mode
bits : 17 - 17 (1 bit)
SSEC : ecurity of the DMA transfer from the source
bits : 18 - 18 (1 bit)
DSEC : ecurity of the DMA transfer to the destination
bits : 19 - 19 (1 bit)
PRIV : rivileged mode
bits : 20 - 20 (1 bit)
channel x configuration register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : channel enable
bits : 0 - 0 (1 bit)
TCIE : transfer complete interrupt enable
bits : 1 - 1 (1 bit)
HTIE : half transfer interrupt enable
bits : 2 - 2 (1 bit)
TEIE : transfer error interrupt enable
bits : 3 - 3 (1 bit)
DIR : data transfer direction
bits : 4 - 4 (1 bit)
CIRC : circular mode
bits : 5 - 5 (1 bit)
PINC : peripheral increment mode
bits : 6 - 6 (1 bit)
MINC : memory increment mode
bits : 7 - 7 (1 bit)
PSIZE : peripheral size
bits : 8 - 9 (2 bit)
MSIZE : memory size
bits : 10 - 11 (2 bit)
PL : priority level
bits : 12 - 13 (2 bit)
MEM2MEM : memory-to-memory mode
bits : 14 - 14 (1 bit)
SECM : ecure mode
bits : 17 - 17 (1 bit)
SSEC : ecurity of the DMA transfer from the source
bits : 18 - 18 (1 bit)
DSEC : ecurity of the DMA transfer to the destination
bits : 19 - 19 (1 bit)
PRIV : rivileged mode
bits : 20 - 20 (1 bit)
channel x number of data to transfer register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : number of data to transfer (0 to 218 - 1)
bits : 0 - 17 (18 bit)
channel x peripheral address register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : peripheral address
bits : 0 - 31 (32 bit)
channel x memory address register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : peripheral address
bits : 0 - 31 (32 bit)
channel x number of data to transfer register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : number of data to transfer (0 to 218 - 1)
bits : 0 - 17 (18 bit)
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