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LPTIM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

ISR

CR

CMP

ARR

CNT

LPTIM1_OR (OR)

RCR

ICR

IER

CFGR


ISR

interrupt and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPM ARRM EXTTRIG CMPOK ARROK UP DOWN UE REPOK

CMPM : Compare match
bits : 0 - 0 (1 bit)

ARRM : Autoreload match
bits : 1 - 1 (1 bit)

EXTTRIG : External trigger edge event
bits : 2 - 2 (1 bit)

CMPOK : Compare register update OK
bits : 3 - 3 (1 bit)

ARROK : Autoreload register update OK
bits : 4 - 4 (1 bit)

UP : Counter direction change down to up
bits : 5 - 5 (1 bit)

DOWN : Counter direction change up to down
bits : 6 - 6 (1 bit)

UE : LPTIM update event occurred
bits : 7 - 7 (1 bit)

REPOK : Repetition register update Ok
bits : 8 - 8 (1 bit)


CR

control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE SNGSTRT CNTSTRT COUNTRST RSTARE

ENABLE : ENABLE
bits : 0 - 0 (1 bit)

SNGSTRT : SNGSTRT
bits : 1 - 1 (1 bit)

CNTSTRT : CNTSTRT
bits : 2 - 2 (1 bit)

COUNTRST : COUNTRST
bits : 3 - 3 (1 bit)

RSTARE : RSTARE
bits : 4 - 4 (1 bit)


CMP

compare register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMP CMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP

CMP : CMP
bits : 0 - 15 (16 bit)


ARR

autoreload register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARR ARR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR

ARR : Auto reload value
bits : 0 - 15 (16 bit)


CNT

counter register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Counter value
bits : 0 - 15 (16 bit)


LPTIM1_OR (OR)

option register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPTIM1_OR LPTIM1_OR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OR_0 OR_1

OR_0 : Option register bit 0
bits : 0 - 0 (1 bit)

OR_1 : Option register bit 1
bits : 1 - 1 (1 bit)


RCR

repetition register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR RCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REP

REP : Repetition register value
bits : 0 - 7 (8 bit)


ICR

interrupt clear register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICR ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPMCF ARRMCF EXTTRIGCF CMPOKCF ARROKCF UPCF DOWNCF UECF REPOKCF

CMPMCF : compare match Clear Flag
bits : 0 - 0 (1 bit)

ARRMCF : Autoreload match Clear Flag
bits : 1 - 1 (1 bit)

EXTTRIGCF : External trigger valid edge Clear Flag
bits : 2 - 2 (1 bit)

CMPOKCF : Compare register update OK Clear Flag
bits : 3 - 3 (1 bit)

ARROKCF : Autoreload register update OK Clear Flag
bits : 4 - 4 (1 bit)

UPCF : Direction change to UP Clear Flag
bits : 5 - 5 (1 bit)

DOWNCF : Direction change to down Clear Flag
bits : 6 - 6 (1 bit)

UECF : Update event clear flag
bits : 7 - 7 (1 bit)

REPOKCF : Repetition register update OK clear flag
bits : 8 - 8 (1 bit)


IER

interrupt enable register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPMIE ARRMIE EXTTRIGIE CMPOKIE ARROKIE UPIE DOWNIE UEIE REPOKIE

CMPMIE : Compare match Interrupt Enable
bits : 0 - 0 (1 bit)

ARRMIE : Autoreload match Interrupt Enable
bits : 1 - 1 (1 bit)

EXTTRIGIE : External trigger valid edge Interrupt Enable
bits : 2 - 2 (1 bit)

CMPOKIE : Compare register update OK Interrupt Enable
bits : 3 - 3 (1 bit)

ARROKIE : Autoreload register update OK Interrupt Enable
bits : 4 - 4 (1 bit)

UPIE : Direction change to UP Interrupt Enable
bits : 5 - 5 (1 bit)

DOWNIE : Direction change to down Interrupt Enable
bits : 6 - 6 (1 bit)

UEIE : Update event interrupt enable
bits : 7 - 7 (1 bit)

REPOKIE : Repetition register update OK interrupt Enable
bits : 8 - 8 (1 bit)


CFGR

configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKSEL CKPOL CKFLT TRGFLT PRESC TRIGSEL TRIGEN TIMOUT WAVE WAVPOL PRELOAD COUNTMODE ENC

CKSEL : CKSEL
bits : 0 - 0 (1 bit)

CKPOL : CKPOL
bits : 1 - 2 (2 bit)

CKFLT : CKFLT
bits : 3 - 4 (2 bit)

TRGFLT : TRGFLT
bits : 6 - 7 (2 bit)

PRESC : PRESC
bits : 9 - 11 (3 bit)

TRIGSEL : TRIGSEL
bits : 13 - 15 (3 bit)

TRIGEN : TRIGEN
bits : 17 - 18 (2 bit)

TIMOUT : TIMOUT
bits : 19 - 19 (1 bit)

WAVE : WAVE
bits : 20 - 20 (1 bit)

WAVPOL : WAVPOL
bits : 21 - 21 (1 bit)

PRELOAD : PRELOAD
bits : 22 - 22 (1 bit)

COUNTMODE : COUNTMODE
bits : 23 - 23 (1 bit)

ENC : ENC
bits : 24 - 24 (1 bit)



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