\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Power control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPMS : Low-power mode selection for CPU1
bits : 0 - 2 (3 bit)
SUBGHZSPINSSSEL : sub-GHz SPI NSS source select
bits : 3 - 3 (1 bit)
FPDR : Flash memory power down mode during LPRun for CPU1
bits : 4 - 4 (1 bit)
FPDS : Flash memory power down mode during LPSleep for CPU1
bits : 5 - 5 (1 bit)
DBP : Disable backup domain write protection
bits : 8 - 8 (1 bit)
VOS : Voltage scaling range selection
bits : 9 - 10 (2 bit)
LPR : Low-power run
bits : 14 - 14 (1 bit)
Power status register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WUF1 : Wakeup flag 1
bits : 0 - 0 (1 bit)
WUF2 : Wakeup flag 2
bits : 1 - 1 (1 bit)
WUF3 : Wakeup flag 3
bits : 2 - 2 (1 bit)
WPVDF : Wakeup PVD flag
bits : 8 - 8 (1 bit)
WRFBUSYF : Radio BUSY wakeup flag
bits : 11 - 11 (1 bit)
WUFI : Internal wakeup interrupt flag
bits : 15 - 15 (1 bit)
Power status register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFBUSYS : Radio BUSY signal status
bits : 1 - 1 (1 bit)
RFBUSYMS : Radio BUSY masked signal status
bits : 2 - 2 (1 bit)
SMPSRDY : SMPS ready flag
bits : 3 - 3 (1 bit)
LDORDY : LDO ready flag
bits : 4 - 4 (1 bit)
RFEOLF : Radio end of life flag
bits : 5 - 5 (1 bit)
REGMRS : regulator2 low power flag
bits : 6 - 6 (1 bit)
FLASHRDY : Flash ready
bits : 7 - 7 (1 bit)
REGLPS : regulator1 started
bits : 8 - 8 (1 bit)
REGLPF : regulator1 low power flag
bits : 9 - 9 (1 bit)
VOSF : Voltage scaling flag
bits : 10 - 10 (1 bit)
PVDO : Power voltage detector output
bits : 11 - 11 (1 bit)
PVMO3 : Peripheral voltage monitoring output: VDDA vs. 1.62 V
bits : 14 - 14 (1 bit)
Power status clear register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CWUF1 : Clear wakeup flag 1
bits : 0 - 0 (1 bit)
CWUF2 : Clear wakeup flag 2
bits : 1 - 1 (1 bit)
CWUF3 : Clear wakeup flag 3
bits : 2 - 2 (1 bit)
CWPVDF : Clear wakeup PVD interrupt flag
bits : 8 - 8 (1 bit)
CWRFBUSYF : Clear wakeup Radio BUSY flag
bits : 11 - 11 (1 bit)
Power control register 5
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFEOLEN : Enable Radio End Of Life detector enabled
bits : 14 - 14 (1 bit)
SMPSEN : Enable SMPS Step Down converter SMPS mode enabled.
bits : 15 - 15 (1 bit)
Power Port A pull-up control register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PU0 : PU0
bits : 0 - 0 (1 bit)
PU1 : PU1
bits : 1 - 1 (1 bit)
PU2 : PU2
bits : 2 - 2 (1 bit)
PU3 : PU3
bits : 3 - 3 (1 bit)
PU4 : PU4
bits : 4 - 4 (1 bit)
PU5 : PU5
bits : 5 - 5 (1 bit)
PU6 : PU6
bits : 6 - 6 (1 bit)
PU7 : PU7
bits : 7 - 7 (1 bit)
PU8 : PU8
bits : 8 - 8 (1 bit)
PU9 : PU9
bits : 9 - 9 (1 bit)
PU10 : PU10
bits : 10 - 10 (1 bit)
PU11 : PU11
bits : 11 - 11 (1 bit)
PU12 : PU12
bits : 12 - 12 (1 bit)
PU13 : Port PA[y] pull-up bit y (y=0 to 13)
bits : 13 - 13 (1 bit)
PU14 : PU14
bits : 14 - 14 (1 bit)
PU15 : Port PA15 pull-up
bits : 15 - 15 (1 bit)
Power Port A pull-down control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD0 : PD0
bits : 0 - 0 (1 bit)
PD1 : PD1
bits : 1 - 1 (1 bit)
PD2 : PD2
bits : 2 - 2 (1 bit)
PD3 : PD3
bits : 3 - 3 (1 bit)
PD4 : PD4
bits : 4 - 4 (1 bit)
PD5 : PD5
bits : 5 - 5 (1 bit)
PD6 : PD6
bits : 6 - 6 (1 bit)
PD7 : PD7
bits : 7 - 7 (1 bit)
PD8 : PD8
bits : 8 - 8 (1 bit)
PD9 : PD9
bits : 9 - 9 (1 bit)
PD10 : PD10
bits : 10 - 10 (1 bit)
PD11 : PD11
bits : 11 - 11 (1 bit)
PD12 : Port PA[y] pull-down (y=0 to 12)
bits : 12 - 12 (1 bit)
PD13 : PD13
bits : 13 - 13 (1 bit)
PD14 : ull-down
bits : 14 - 14 (1 bit)
PD15 : PD15
bits : 15 - 15 (1 bit)
Power Port B pull-up control register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PU0 : PU0
bits : 0 - 0 (1 bit)
PU1 : PU1
bits : 1 - 1 (1 bit)
PU2 : PU2
bits : 2 - 2 (1 bit)
PU3 : PU3
bits : 3 - 3 (1 bit)
PU4 : PU4
bits : 4 - 4 (1 bit)
PU5 : PU5
bits : 5 - 5 (1 bit)
PU6 : PU6
bits : 6 - 6 (1 bit)
PU7 : PU7
bits : 7 - 7 (1 bit)
PU8 : PU8
bits : 8 - 8 (1 bit)
PU9 : PU9
bits : 9 - 9 (1 bit)
PU10 : PU10
bits : 10 - 10 (1 bit)
PU11 : PU11
bits : 11 - 11 (1 bit)
PU12 : PU12
bits : 12 - 12 (1 bit)
PU13 : PU13
bits : 13 - 13 (1 bit)
PU14 : PU14
bits : 14 - 14 (1 bit)
PU15 : Port PB[y] pull-up (y=0 to 15)
bits : 15 - 15 (1 bit)
Power Port B pull-down control register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD0 : PD0
bits : 0 - 0 (1 bit)
PD1 : PD1
bits : 1 - 1 (1 bit)
PD2 : PD2
bits : 2 - 2 (1 bit)
PD3 : Port PB[y] pull-down (y=0 to 3)
bits : 3 - 3 (1 bit)
PD4 : PD4
bits : 4 - 4 (1 bit)
PD5 : PD5
bits : 5 - 5 (1 bit)
PD6 : PD6
bits : 6 - 6 (1 bit)
PD7 : PD7
bits : 7 - 7 (1 bit)
PD8 : PD8
bits : 8 - 8 (1 bit)
PD9 : PD9
bits : 9 - 9 (1 bit)
PD10 : PD10
bits : 10 - 10 (1 bit)
PD11 : PD11
bits : 11 - 11 (1 bit)
PD12 : PD12
bits : 12 - 12 (1 bit)
PD13 : PD13
bits : 13 - 13 (1 bit)
PD14 : PD14
bits : 14 - 14 (1 bit)
PD15 : Port PB[y] pull-down (y=5 to 15)
bits : 15 - 15 (1 bit)
Power Port C pull-up control register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PU0 : PU0
bits : 0 - 0 (1 bit)
PU1 : PU1
bits : 1 - 1 (1 bit)
PU2 : PU2
bits : 2 - 2 (1 bit)
PU3 : PU3
bits : 3 - 3 (1 bit)
PU4 : PU4
bits : 4 - 4 (1 bit)
PU5 : PU5
bits : 5 - 5 (1 bit)
PU6 : PU6
bits : 6 - 6 (1 bit)
PU13 : PU13
bits : 13 - 13 (1 bit)
PU14 : PU14
bits : 14 - 14 (1 bit)
PU15 : Port PC[y] pull-up (y=13 to 15)
bits : 15 - 15 (1 bit)
Power Port C pull-down control register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD0 : PD0
bits : 0 - 0 (1 bit)
PD1 : PD1
bits : 1 - 1 (1 bit)
PD2 : PD2
bits : 2 - 2 (1 bit)
PD3 : PD3
bits : 3 - 3 (1 bit)
PD4 : PD4
bits : 4 - 4 (1 bit)
PD5 : PD5
bits : 5 - 5 (1 bit)
PD6 : PD6
bits : 6 - 6 (1 bit)
PD13 : PD13
bits : 13 - 13 (1 bit)
PD14 : PD14
bits : 14 - 14 (1 bit)
PD15 : Port PC[y] pull-down (y=13 to 15)
bits : 15 - 15 (1 bit)
Power control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PVDE : Power voltage detector enable
bits : 0 - 0 (1 bit)
PLS : Power voltage detector level selection.
bits : 1 - 3 (3 bit)
PVME3 : Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V
bits : 6 - 6 (1 bit)
Power Port H pull-up control register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PU3 : pull-up
bits : 3 - 3 (1 bit)
Power Port H pull-down control register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD3 : pull-down
bits : 3 - 3 (1 bit)
Power control register 3
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EWUP1 : Enable Wakeup pin WKUP1 for CPU1
bits : 0 - 0 (1 bit)
EWUP2 : Enable Wakeup pin WKUP2 for CPU1
bits : 1 - 1 (1 bit)
EWUP3 : Enable Wakeup pin WKUP3 for CPU1
bits : 2 - 2 (1 bit)
EULPEN : Ultra-low-power enable
bits : 7 - 7 (1 bit)
EWPVD : Enable wakeup PVD for CPU1
bits : 8 - 8 (1 bit)
RRS : SRAM2 retention in Standby mode
bits : 9 - 9 (1 bit)
APC : Apply pull-up and pull-down configuration from CPU1
bits : 10 - 10 (1 bit)
EWRFBUSY : Enable Radio BUSY Wakeup from Standby for CPU1
bits : 11 - 11 (1 bit)
EWRFIRQ : akeup for CPU1
bits : 13 - 13 (1 bit)
EIWUL : Enable internal wakeup line for CPU1
bits : 15 - 15 (1 bit)
Power extended status and status clear register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C1CSSF : Clear CPU1 Stop Standby flags
bits : 0 - 0 (1 bit)
access : write-only
C1SBF : System Standby flag for CPU1. (no core states retained)
bits : 8 - 8 (1 bit)
access : read-only
C1STOP2F : System Stop2 flag for CPU1. (partial core states retained)
bits : 9 - 9 (1 bit)
access : read-only
C1STOPF : System Stop0, 1 flag for CPU1. (All core states retained)
bits : 10 - 10 (1 bit)
access : read-only
C1DS : CPU1 deepsleep mode
bits : 14 - 14 (1 bit)
access : read-only
Power SPI3 control register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSS : sub-GHz SPI NSS control
bits : 15 - 15 (1 bit)
Power control register 4
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WP1 : Wakeup pin WKUP1 polarity
bits : 0 - 0 (1 bit)
WP2 : Wakeup pin WKUP2 polarity
bits : 1 - 1 (1 bit)
WP3 : Wakeup pin WKUP3 polarity
bits : 2 - 2 (1 bit)
VBE : VBAT battery charging enable
bits : 8 - 8 (1 bit)
VBRS : VBAT battery charging resistor selection
bits : 9 - 9 (1 bit)
WRFBUSYP : Wakeup Radio BUSY polarity
bits : 11 - 11 (1 bit)
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