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SYSCFG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection :

Registers

MEMRMP

EXTICR3

EXTICR4

SCSR

CFGR2

SWPR

RFDCR

SKR

CFGR1

EXTICR1

EXTICR2


MEMRMP

memory remap register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMRMP MEMRMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEM_MODE

MEM_MODE : Memory mapping selection
bits : 0 - 2 (3 bit)


EXTICR3

external interrupt configuration register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR3 EXTICR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI8 EXTI9 EXTI10 EXTI11

EXTI8 : EXTI 8 configuration bits
bits : 0 - 2 (3 bit)

EXTI9 : EXTI 9 configuration bits
bits : 4 - 6 (3 bit)

EXTI10 : EXTI 10 configuration bits
bits : 8 - 10 (3 bit)

EXTI11 : EXTI 11 configuration bits
bits : 12 - 14 (3 bit)


EXTICR4

external interrupt configuration register 4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR4 EXTICR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI12 EXTI13 EXTI14 EXTI15

EXTI12 : EXTI12 configuration bits
bits : 0 - 2 (3 bit)

EXTI13 : EXTI13 configuration bits
bits : 4 - 6 (3 bit)

EXTI14 : EXTI14 configuration bits
bits : 8 - 10 (3 bit)

EXTI15 : EXTI15 configuration bits
bits : 12 - 14 (3 bit)


SCSR

SCSR
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCSR SCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRAM2ER SRAMBSY PKASRAMBSY

SRAM2ER : SRAM2 erase
bits : 0 - 0 (1 bit)
access : read-write

SRAMBSY : SRAM1, SRAM2 and PKA SRAM busy by erase operation
bits : 1 - 1 (1 bit)
access : read-only

PKASRAMBSY : PKA SRAM busy by erase operation
bits : 8 - 8 (1 bit)
access : read-only


CFGR2

CFGR2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR2 CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLL SPL PVDL ECCL SPF

CLL : CPU1 LOCKUP (Hardfault) output enable bit
bits : 0 - 0 (1 bit)
access : read-write

SPL : SRAM2 parity lock bit
bits : 1 - 1 (1 bit)
access : read-write

PVDL : PVD lock enable bit
bits : 2 - 2 (1 bit)
access : read-write

ECCL : ECC Lock
bits : 3 - 3 (1 bit)
access : read-write

SPF : SRAM2 parity error flag
bits : 8 - 8 (1 bit)
access : read-write


SWPR

SWPR
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWPR SWPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0WP P1WP P2WP P3WP P4WP P5WP P6WP P7WP P8WP P9WP P10WP P11WP P12WP P13WP P14WP P15WP P16WP P17WP P18WP P19WP P20WP P21WP P22WP P23WP P24WP P25WP P26WP P27WP P28WP P29WP P30WP P31WP

P0WP : SRAM2 1Kbyte page 0 write protection
bits : 0 - 0 (1 bit)

P1WP : SRAM2 1Kbyte page 1 write protection
bits : 1 - 1 (1 bit)

P2WP : SRAM2 1Kbyte page 2 write protection
bits : 2 - 2 (1 bit)

P3WP : SRAM2 1Kbyte page 3 write protection
bits : 3 - 3 (1 bit)

P4WP : SRAM2 1Kbyte page 4 write protection
bits : 4 - 4 (1 bit)

P5WP : SRAM2 1Kbyte page 5 write protection
bits : 5 - 5 (1 bit)

P6WP : SRAM2 1Kbyte page 6 write protection
bits : 6 - 6 (1 bit)

P7WP : SRAM2 1Kbyte page 7 write protection
bits : 7 - 7 (1 bit)

P8WP : SRAM2 1Kbyte page 8 write protection
bits : 8 - 8 (1 bit)

P9WP : SRAM2 1Kbyte page 9 write protection
bits : 9 - 9 (1 bit)

P10WP : SRAM2 1Kbyte page 10 write protection
bits : 10 - 10 (1 bit)

P11WP : SRAM2 1Kbyte page 11 write protection
bits : 11 - 11 (1 bit)

P12WP : SRAM2 1Kbyte page 12 write protection
bits : 12 - 12 (1 bit)

P13WP : SRAM2 1Kbyte page 13 write protection
bits : 13 - 13 (1 bit)

P14WP : SRAM2 1Kbyte page 14 write protection
bits : 14 - 14 (1 bit)

P15WP : SRAM2 1Kbyte page 15 write protection
bits : 15 - 15 (1 bit)

P16WP : SRAM2 1Kbyte page 16 write protection
bits : 16 - 16 (1 bit)

P17WP : SRAM2 1Kbyte page 17 write protection
bits : 17 - 17 (1 bit)

P18WP : SRAM2 1Kbyte page 18 write protection
bits : 18 - 18 (1 bit)

P19WP : SRAM2 1Kbyte page 19 write protection
bits : 19 - 19 (1 bit)

P20WP : SRAM2 1Kbyte page 20 write protection
bits : 20 - 20 (1 bit)

P21WP : SRAM2 1Kbyte page 21 write protection
bits : 21 - 21 (1 bit)

P22WP : SRAM2 1Kbyte page 22 write protection
bits : 22 - 22 (1 bit)

P23WP : SRAM2 1Kbyte page 23 write protection
bits : 23 - 23 (1 bit)

P24WP : SRAM2 1Kbyte page 24 write protection
bits : 24 - 24 (1 bit)

P25WP : SRAM2 1Kbyte page 25 write protection
bits : 25 - 25 (1 bit)

P26WP : SRAM2 1Kbyte page 26 write protection
bits : 26 - 26 (1 bit)

P27WP : SRAM2 1Kbyte page 27 write protection
bits : 27 - 27 (1 bit)

P28WP : SRAM2 1Kbyte page 28 write protection
bits : 28 - 28 (1 bit)

P29WP : SRAM2 1Kbyte page 29 write protection
bits : 29 - 29 (1 bit)

P30WP : SRAM2 1Kbyte page 30 write protection
bits : 30 - 30 (1 bit)

P31WP : SRAM2 1Kbyte page 31 write protection
bits : 31 - 31 (1 bit)


RFDCR

radio debug control register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RFDCR RFDCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFTBSEL

RFTBSEL : radio debug test bus selection
bits : 0 - 0 (1 bit)


SKR

SKR
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SKR SKR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : SRAM2 write protection key for software erase
bits : 0 - 7 (8 bit)


CFGR1

configuration register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR1 CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOOSTEN I2C_PB6_FMP I2C_PB7_FMP I2C_PB8_FMP I2C_PB9_FMP I2C1_FMP I2C2_FMP I2C3_FMP

BOOSTEN : I/O analog switch voltage booster enable
bits : 8 - 8 (1 bit)

I2C_PB6_FMP : Fast-mode Plus (Fm+) driving capability activation on PB6
bits : 16 - 16 (1 bit)

I2C_PB7_FMP : Fast-mode Plus (Fm+) driving capability activation on PB7
bits : 17 - 17 (1 bit)

I2C_PB8_FMP : Fast-mode Plus (Fm+) driving capability activation on PB8
bits : 18 - 18 (1 bit)

I2C_PB9_FMP : Fast-mode Plus (Fm+) driving capability activation on PB9
bits : 19 - 19 (1 bit)

I2C1_FMP : I2C1 Fast-mode Plus driving capability activation
bits : 20 - 20 (1 bit)

I2C2_FMP : I2C2 Fast-mode Plus driving capability activation
bits : 21 - 21 (1 bit)

I2C3_FMP : I2C3 Fast-mode Plus driving capability activation
bits : 22 - 22 (1 bit)


EXTICR1

external interrupt configuration register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR1 EXTICR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0 EXTI1 EXTI2 EXTI3

EXTI0 : EXTI 0 configuration bits
bits : 0 - 2 (3 bit)

EXTI1 : EXTI 1 configuration bits
bits : 4 - 6 (3 bit)

EXTI2 : EXTI 2 configuration bits
bits : 8 - 10 (3 bit)

EXTI3 : EXTI 3 configuration bits
bits : 12 - 14 (3 bit)


EXTICR2

external interrupt configuration register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR2 EXTICR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI4 EXTI5 EXTI6 EXTI7

EXTI4 : EXTI 4 configuration bits
bits : 0 - 2 (3 bit)

EXTI5 : EXTI 5 configuration bits
bits : 4 - 6 (3 bit)

EXTI6 : EXTI 6 configuration bits
bits : 8 - 10 (3 bit)

EXTI7 : EXTI 7 configuration bits
bits : 12 - 14 (3 bit)



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